host1x/hw/opcodes.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Tegra host1x opcodes
0004  *
0005  * Copyright (c) 2022 NVIDIA Corporation.
0006  */
0007
0008 #ifndef __HOST1X_OPCODES_H
0009 #define __HOST1X_OPCODES_H
0010
0011 #include <linux/types.h>
0012
0013 static inline u32 host1x_class_host_wait_syncpt(
0014     unsigned indx, unsigned threshold)
0015 {
0016     return host1x_uclass_wait_syncpt_indx_f(indx)
0017         | host1x_uclass_wait_syncpt_thresh_f(threshold);
0018 }
0019
0020 static inline u32 host1x_class_host_load_syncpt_base(
0021     unsigned indx, unsigned threshold)
0022 {
0023     return host1x_uclass_load_syncpt_base_base_indx_f(indx)
0024         | host1x_uclass_load_syncpt_base_value_f(threshold);
0025 }
0026
0027 static inline u32 host1x_class_host_wait_syncpt_base(
0028     unsigned indx, unsigned base_indx, unsigned offset)
0029 {
0030     return host1x_uclass_wait_syncpt_base_indx_f(indx)
0031         | host1x_uclass_wait_syncpt_base_base_indx_f(base_indx)
0032         | host1x_uclass_wait_syncpt_base_offset_f(offset);
0033 }
0034
0035 static inline u32 host1x_class_host_incr_syncpt_base(
0036     unsigned base_indx, unsigned offset)
0037 {
0038     return host1x_uclass_incr_syncpt_base_base_indx_f(base_indx)
0039         | host1x_uclass_incr_syncpt_base_offset_f(offset);
0040 }
0041
0042 static inline u32 host1x_class_host_incr_syncpt(
0043     unsigned cond, unsigned indx)
0044 {
0045     return host1x_uclass_incr_syncpt_cond_f(cond)
0046         | host1x_uclass_incr_syncpt_indx_f(indx);
0047 }
0048
0049 static inline u32 host1x_class_host_indoff_reg_write(
0050     unsigned mod_id, unsigned offset, bool auto_inc)
0051 {
0052     u32 v = host1x_uclass_indoff_indbe_f(0xf)
0053         | host1x_uclass_indoff_indmodid_f(mod_id)
0054         | host1x_uclass_indoff_indroffset_f(offset);
0055     if (auto_inc)
0056         v |= host1x_uclass_indoff_autoinc_f(1);
0057     return v;
0058 }
0059
0060 static inline u32 host1x_class_host_indoff_reg_read(
0061     unsigned mod_id, unsigned offset, bool auto_inc)
0062 {
0063     u32 v = host1x_uclass_indoff_indmodid_f(mod_id)
0064         | host1x_uclass_indoff_indroffset_f(offset)
0065         | host1x_uclass_indoff_rwn_read_v();
0066     if (auto_inc)
0067         v |= host1x_uclass_indoff_autoinc_f(1);
0068     return v;
0069 }
0070
0071 static inline u32 host1x_opcode_setclass(
0072     unsigned class_id, unsigned offset, unsigned mask)
0073 {
0074     return (0 << 28) | (offset << 16) | (class_id << 6) | mask;
0075 }
0076
0077 static inline u32 host1x_opcode_incr(unsigned offset, unsigned count)
0078 {
0079     return (1 << 28) | (offset << 16) | count;
0080 }
0081
0082 static inline u32 host1x_opcode_nonincr(unsigned offset, unsigned count)
0083 {
0084     return (2 << 28) | (offset << 16) | count;
0085 }
0086
0087 static inline u32 host1x_opcode_mask(unsigned offset, unsigned mask)
0088 {
0089     return (3 << 28) | (offset << 16) | mask;
0090 }
0091
0092 static inline u32 host1x_opcode_imm(unsigned offset, unsigned value)
0093 {
0094     return (4 << 28) | (offset << 16) | value;
0095 }
0096
0097 static inline u32 host1x_opcode_imm_incr_syncpt(unsigned cond, unsigned indx)
0098 {
0099     return host1x_opcode_imm(host1x_uclass_incr_syncpt_r(),
0100         host1x_class_host_incr_syncpt(cond, indx));
0101 }
0102
0103 static inline u32 host1x_opcode_restart(unsigned address)
0104 {
0105     return (5 << 28) | (address >> 4);
0106 }
0107
0108 static inline u32 host1x_opcode_gather(unsigned count)
0109 {
0110     return (6 << 28) | count;
0111 }
0112
0113 static inline u32 host1x_opcode_gather_nonincr(unsigned offset, unsigned count)
0114 {
0115     return (6 << 28) | (offset << 16) | BIT(15) | count;
0116 }
0117
0118 static inline u32 host1x_opcode_gather_incr(unsigned offset, unsigned count)
0119 {
0120     return (6 << 28) | (offset << 16) | BIT(15) | BIT(14) | count;
0121 }
0122
0123 static inline u32 host1x_opcode_setstreamid(unsigned streamid)
0124 {
0125     return (7 << 28) | streamid;
0126 }
0127
0128 static inline u32 host1x_opcode_setpayload(unsigned payload)
0129 {
0130     return (9 << 28) | payload;
0131 }
0132
0133 static inline u32 host1x_opcode_gather_wide(unsigned count)
0134 {
0135     return (12 << 28) | count;
0136 }
0137
0138 static inline u32 host1x_opcode_acquire_mlock(unsigned mlock)
0139 {
0140     return (14 << 28) | (0 << 24) | mlock;
0141 }
0142
0143 static inline u32 host1x_opcode_release_mlock(unsigned mlock)
0144 {
0145     return (14 << 28) | (1 << 24) | mlock;
0146 }
0147
0148 #define HOST1X_OPCODE_NOP host1x_opcode_nonincr(0, 0)
0149
0150 #endif