host1x/hw/intr_hw.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Tegra host1x Interrupt Management
0004  *
0005  * Copyright (C) 2010 Google, Inc.
0006  * Copyright (c) 2010-2013, NVIDIA Corporation.
0007  */
0008
0009 #include <linux/interrupt.h>
0010 #include <linux/irq.h>
0011 #include <linux/io.h>
0012
0013 #include "../intr.h"
0014 #include "../dev.h"
0015
0016 /*
0017  * Sync point threshold interrupt service function
0018  * Handles sync point threshold triggers, in interrupt context
0019  */
0020 static void host1x_intr_syncpt_handle(struct host1x_syncpt *syncpt)
0021 {
0022     unsigned int id = syncpt->id;
0023     struct host1x *host = syncpt->host;
0024
0025     host1x_sync_writel(host, BIT(id % 32),
0026         HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id / 32));
0027     host1x_sync_writel(host, BIT(id % 32),
0028         HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id / 32));
0029
0030     schedule_work(&syncpt->intr.work);
0031 }
0032
0033 static irqreturn_t syncpt_thresh_isr(int irq, void *dev_id)
0034 {
0035     struct host1x *host = dev_id;
0036     unsigned long reg;
0037     unsigned int i, id;
0038
0039     for (i = 0; i < DIV_ROUND_UP(host->info->nb_pts, 32); i++) {
0040         reg = host1x_sync_readl(host,
0041             HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i));
0042         for_each_set_bit(id, &reg, 32) {
0043             struct host1x_syncpt *syncpt =
0044                 host->syncpt + (i * 32 + id);
0045             host1x_intr_syncpt_handle(syncpt);
0046         }
0047     }
0048
0049     return IRQ_HANDLED;
0050 }
0051
0052 static void _host1x_intr_disable_all_syncpt_intrs(struct host1x *host)
0053 {
0054     unsigned int i;
0055
0056     for (i = 0; i < DIV_ROUND_UP(host->info->nb_pts, 32); ++i) {
0057         host1x_sync_writel(host, 0xffffffffu,
0058             HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(i));
0059         host1x_sync_writel(host, 0xffffffffu,
0060             HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(i));
0061     }
0062 }
0063
0064 static void intr_hw_init(struct host1x *host, u32 cpm)
0065 {
0066 #if HOST1X_HW < 6
0067     /* disable the ip_busy_timeout. this prevents write drops */
0068     host1x_sync_writel(host, 0, HOST1X_SYNC_IP_BUSY_TIMEOUT);
0069
0070     /*
0071      * increase the auto-ack timout to the maximum value. 2d will hang
0072      * otherwise on Tegra2.
0073      */
0074     host1x_sync_writel(host, 0xff, HOST1X_SYNC_CTXSW_TIMEOUT_CFG);
0075
0076     /* update host clocks per usec */
0077     host1x_sync_writel(host, cpm, HOST1X_SYNC_USEC_CLK);
0078 #endif
0079 #if HOST1X_HW >= 8
0080     u32 id;
0081
0082     /*
0083      * Program threshold interrupt destination among 8 lines per VM,
0084      * per syncpoint. For now, just direct all to the first interrupt
0085      * line.
0086      */
0087     for (id = 0; id < host->info->nb_pts; id++)
0088         host1x_sync_writel(host, 0, HOST1X_SYNC_SYNCPT_INTR_DEST(id));
0089 #endif
0090 }
0091
0092 static int
0093 _host1x_intr_init_host_sync(struct host1x *host, u32 cpm,
0094                 void (*syncpt_thresh_work)(struct work_struct *))
0095 {
0096     unsigned int i;
0097     int err;
0098
0099     host1x_hw_intr_disable_all_syncpt_intrs(host);
0100
0101     for (i = 0; i < host->info->nb_pts; i++)
0102         INIT_WORK(&host->syncpt[i].intr.work, syncpt_thresh_work);
0103
0104     err = devm_request_irq(host->dev, host->intr_syncpt_irq,
0105                    syncpt_thresh_isr, IRQF_SHARED,
0106                    "host1x_syncpt", host);
0107     if (err < 0) {
0108         WARN_ON(1);
0109         return err;
0110     }
0111
0112     intr_hw_init(host, cpm);
0113
0114     return 0;
0115 }
0116
0117 static void _host1x_intr_set_syncpt_threshold(struct host1x *host,
0118                           unsigned int id,
0119                           u32 thresh)
0120 {
0121     host1x_sync_writel(host, thresh, HOST1X_SYNC_SYNCPT_INT_THRESH(id));
0122 }
0123
0124 static void _host1x_intr_enable_syncpt_intr(struct host1x *host,
0125                         unsigned int id)
0126 {
0127     host1x_sync_writel(host, BIT(id % 32),
0128         HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id / 32));
0129 }
0130
0131 static void _host1x_intr_disable_syncpt_intr(struct host1x *host,
0132                          unsigned int id)
0133 {
0134     host1x_sync_writel(host, BIT(id % 32),
0135         HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id / 32));
0136     host1x_sync_writel(host, BIT(id % 32),
0137         HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id / 32));
0138 }
0139
0140 static int _host1x_free_syncpt_irq(struct host1x *host)
0141 {
0142     unsigned int i;
0143
0144     devm_free_irq(host->dev, host->intr_syncpt_irq, host);
0145
0146     for (i = 0; i < host->info->nb_pts; i++)
0147         cancel_work_sync(&host->syncpt[i].intr.work);
0148
0149     return 0;
0150 }
0151
0152 static const struct host1x_intr_ops host1x_intr_ops = {
0153     .init_host_sync = _host1x_intr_init_host_sync,
0154     .set_syncpt_threshold = _host1x_intr_set_syncpt_threshold,
0155     .enable_syncpt_intr = _host1x_intr_enable_syncpt_intr,
0156     .disable_syncpt_intr = _host1x_intr_disable_syncpt_intr,
0157     .disable_all_syncpt_intrs = _host1x_intr_disable_all_syncpt_intrs,
0158     .free_syncpt_irq = _host1x_free_syncpt_irq,
0159 };