host1x/hw/hw_host1x04_uclass.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2013 NVIDIA Corporation.
0004  */
0005
0006  /*
0007   * Function naming determines intended use:
0008   *
0009   *     <x>_r(void) : Returns the offset for register <x>.
0010   *
0011   *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
0012   *
0013   *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
0014   *
0015   *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
0016   *         and masked to place it at field <y> of register <x>.  This value
0017   *         can be |'d with others to produce a full register value for
0018   *         register <x>.
0019   *
0020   *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
0021   *         value can be ~'d and then &'d to clear the value of field <y> for
0022   *         register <x>.
0023   *
0024   *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
0025   *         to place it at field <y> of register <x>.  This value can be |'d
0026   *         with others to produce a full register value for <x>.
0027   *
0028   *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
0029   *         <x> value 'r' after being shifted to place its LSB at bit 0.
0030   *         This value is suitable for direct comparison with other unshifted
0031   *         values appropriate for use in field <y> of register <x>.
0032   *
0033   *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
0034   *         field <y> of register <x>.  This value is suitable for direct
0035   *         comparison with unshifted values appropriate for use in field <y>
0036   *         of register <x>.
0037   */
0038
0039 #ifndef HOST1X_HW_HOST1X04_UCLASS_H
0040 #define HOST1X_HW_HOST1X04_UCLASS_H
0041
0042 static inline u32 host1x_uclass_incr_syncpt_r(void)
0043 {
0044     return 0x0;
0045 }
0046 #define HOST1X_UCLASS_INCR_SYNCPT \
0047     host1x_uclass_incr_syncpt_r()
0048 static inline u32 host1x_uclass_incr_syncpt_cond_f(u32 v)
0049 {
0050     return (v & 0xff) << 8;
0051 }
0052 #define HOST1X_UCLASS_INCR_SYNCPT_COND_F(v) \
0053     host1x_uclass_incr_syncpt_cond_f(v)
0054 static inline u32 host1x_uclass_incr_syncpt_indx_f(u32 v)
0055 {
0056     return (v & 0xff) << 0;
0057 }
0058 #define HOST1X_UCLASS_INCR_SYNCPT_INDX_F(v) \
0059     host1x_uclass_incr_syncpt_indx_f(v)
0060 static inline u32 host1x_uclass_wait_syncpt_r(void)
0061 {
0062     return 0x8;
0063 }
0064 #define HOST1X_UCLASS_WAIT_SYNCPT \
0065     host1x_uclass_wait_syncpt_r()
0066 static inline u32 host1x_uclass_wait_syncpt_indx_f(u32 v)
0067 {
0068     return (v & 0xff) << 24;
0069 }
0070 #define HOST1X_UCLASS_WAIT_SYNCPT_INDX_F(v) \
0071     host1x_uclass_wait_syncpt_indx_f(v)
0072 static inline u32 host1x_uclass_wait_syncpt_thresh_f(u32 v)
0073 {
0074     return (v & 0xffffff) << 0;
0075 }
0076 #define HOST1X_UCLASS_WAIT_SYNCPT_THRESH_F(v) \
0077     host1x_uclass_wait_syncpt_thresh_f(v)
0078 static inline u32 host1x_uclass_wait_syncpt_base_r(void)
0079 {
0080     return 0x9;
0081 }
0082 #define HOST1X_UCLASS_WAIT_SYNCPT_BASE \
0083     host1x_uclass_wait_syncpt_base_r()
0084 static inline u32 host1x_uclass_wait_syncpt_base_indx_f(u32 v)
0085 {
0086     return (v & 0xff) << 24;
0087 }
0088 #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_INDX_F(v) \
0089     host1x_uclass_wait_syncpt_base_indx_f(v)
0090 static inline u32 host1x_uclass_wait_syncpt_base_base_indx_f(u32 v)
0091 {
0092     return (v & 0xff) << 16;
0093 }
0094 #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_BASE_INDX_F(v) \
0095     host1x_uclass_wait_syncpt_base_base_indx_f(v)
0096 static inline u32 host1x_uclass_wait_syncpt_base_offset_f(u32 v)
0097 {
0098     return (v & 0xffff) << 0;
0099 }
0100 #define HOST1X_UCLASS_WAIT_SYNCPT_BASE_OFFSET_F(v) \
0101     host1x_uclass_wait_syncpt_base_offset_f(v)
0102 static inline u32 host1x_uclass_load_syncpt_base_r(void)
0103 {
0104     return 0xb;
0105 }
0106 #define HOST1X_UCLASS_LOAD_SYNCPT_BASE \
0107     host1x_uclass_load_syncpt_base_r()
0108 static inline u32 host1x_uclass_load_syncpt_base_base_indx_f(u32 v)
0109 {
0110     return (v & 0xff) << 24;
0111 }
0112 #define HOST1X_UCLASS_LOAD_SYNCPT_BASE_BASE_INDX_F(v) \
0113     host1x_uclass_load_syncpt_base_base_indx_f(v)
0114 static inline u32 host1x_uclass_load_syncpt_base_value_f(u32 v)
0115 {
0116     return (v & 0xffffff) << 0;
0117 }
0118 #define HOST1X_UCLASS_LOAD_SYNCPT_BASE_VALUE_F(v) \
0119     host1x_uclass_load_syncpt_base_value_f(v)
0120 static inline u32 host1x_uclass_incr_syncpt_base_base_indx_f(u32 v)
0121 {
0122     return (v & 0xff) << 24;
0123 }
0124 #define HOST1X_UCLASS_INCR_SYNCPT_BASE_BASE_INDX_F(v) \
0125     host1x_uclass_incr_syncpt_base_base_indx_f(v)
0126 static inline u32 host1x_uclass_incr_syncpt_base_offset_f(u32 v)
0127 {
0128     return (v & 0xffffff) << 0;
0129 }
0130 #define HOST1X_UCLASS_INCR_SYNCPT_BASE_OFFSET_F(v) \
0131     host1x_uclass_incr_syncpt_base_offset_f(v)
0132 static inline u32 host1x_uclass_indoff_r(void)
0133 {
0134     return 0x2d;
0135 }
0136 #define HOST1X_UCLASS_INDOFF \
0137     host1x_uclass_indoff_r()
0138 static inline u32 host1x_uclass_indoff_indbe_f(u32 v)
0139 {
0140     return (v & 0xf) << 28;
0141 }
0142 #define HOST1X_UCLASS_INDOFF_INDBE_F(v) \
0143     host1x_uclass_indoff_indbe_f(v)
0144 static inline u32 host1x_uclass_indoff_autoinc_f(u32 v)
0145 {
0146     return (v & 0x1) << 27;
0147 }
0148 #define HOST1X_UCLASS_INDOFF_AUTOINC_F(v) \
0149     host1x_uclass_indoff_autoinc_f(v)
0150 static inline u32 host1x_uclass_indoff_indmodid_f(u32 v)
0151 {
0152     return (v & 0xff) << 18;
0153 }
0154 #define HOST1X_UCLASS_INDOFF_INDMODID_F(v) \
0155     host1x_uclass_indoff_indmodid_f(v)
0156 static inline u32 host1x_uclass_indoff_indroffset_f(u32 v)
0157 {
0158     return (v & 0xffff) << 2;
0159 }
0160 #define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
0161     host1x_uclass_indoff_indroffset_f(v)
0162 static inline u32 host1x_uclass_indoff_rwn_read_v(void)
0163 {
0164     return 1;
0165 }
0166 #define HOST1X_UCLASS_INDOFF_INDROFFSET_F(v) \
0167     host1x_uclass_indoff_indroffset_f(v)
0168 static inline u32 host1x_uclass_load_syncpt_payload_32_r(void)
0169 {
0170     return 0x4e;
0171 }
0172 #define HOST1X_UCLASS_LOAD_SYNCPT_PAYLOAD_32 \
0173     host1x_uclass_load_syncpt_payload_32_r()
0174 static inline u32 host1x_uclass_wait_syncpt_32_r(void)
0175 {
0176     return 0x50;
0177 }
0178 #define HOST1X_UCLASS_WAIT_SYNCPT_32 \
0179     host1x_uclass_wait_syncpt_32_r()
0180
0181 #endif