host1x/hw/hw_host1x02_sync.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2013 NVIDIA Corporation.
0004  */
0005
0006  /*
0007   * Function naming determines intended use:
0008   *
0009   *     <x>_r(void) : Returns the offset for register <x>.
0010   *
0011   *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
0012   *
0013   *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
0014   *
0015   *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
0016   *         and masked to place it at field <y> of register <x>.  This value
0017   *         can be |'d with others to produce a full register value for
0018   *         register <x>.
0019   *
0020   *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
0021   *         value can be ~'d and then &'d to clear the value of field <y> for
0022   *         register <x>.
0023   *
0024   *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
0025   *         to place it at field <y> of register <x>.  This value can be |'d
0026   *         with others to produce a full register value for <x>.
0027   *
0028   *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
0029   *         <x> value 'r' after being shifted to place its LSB at bit 0.
0030   *         This value is suitable for direct comparison with other unshifted
0031   *         values appropriate for use in field <y> of register <x>.
0032   *
0033   *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
0034   *         field <y> of register <x>.  This value is suitable for direct
0035   *         comparison with unshifted values appropriate for use in field <y>
0036   *         of register <x>.
0037   */
0038
0039 #ifndef HOST1X_HW_HOST1X02_SYNC_H
0040 #define HOST1X_HW_HOST1X02_SYNC_H
0041
0042 #define REGISTER_STRIDE 4
0043
0044 static inline u32 host1x_sync_syncpt_r(unsigned int id)
0045 {
0046     return 0x400 + id * REGISTER_STRIDE;
0047 }
0048 #define HOST1X_SYNC_SYNCPT(id) \
0049     host1x_sync_syncpt_r(id)
0050 static inline u32 host1x_sync_syncpt_thresh_cpu0_int_status_r(unsigned int id)
0051 {
0052     return 0x40 + id * REGISTER_STRIDE;
0053 }
0054 #define HOST1X_SYNC_SYNCPT_THRESH_CPU0_INT_STATUS(id) \
0055     host1x_sync_syncpt_thresh_cpu0_int_status_r(id)
0056 static inline u32 host1x_sync_syncpt_thresh_int_disable_r(unsigned int id)
0057 {
0058     return 0x60 + id * REGISTER_STRIDE;
0059 }
0060 #define HOST1X_SYNC_SYNCPT_THRESH_INT_DISABLE(id) \
0061     host1x_sync_syncpt_thresh_int_disable_r(id)
0062 static inline u32 host1x_sync_syncpt_thresh_int_enable_cpu0_r(unsigned int id)
0063 {
0064     return 0x68 + id * REGISTER_STRIDE;
0065 }
0066 #define HOST1X_SYNC_SYNCPT_THRESH_INT_ENABLE_CPU0(id) \
0067     host1x_sync_syncpt_thresh_int_enable_cpu0_r(id)
0068 static inline u32 host1x_sync_cf_setup_r(unsigned int channel)
0069 {
0070     return 0x80 + channel * REGISTER_STRIDE;
0071 }
0072 #define HOST1X_SYNC_CF_SETUP(channel) \
0073     host1x_sync_cf_setup_r(channel)
0074 static inline u32 host1x_sync_cf_setup_base_v(u32 r)
0075 {
0076     return (r >> 0) & 0x3ff;
0077 }
0078 #define HOST1X_SYNC_CF_SETUP_BASE_V(r) \
0079     host1x_sync_cf_setup_base_v(r)
0080 static inline u32 host1x_sync_cf_setup_limit_v(u32 r)
0081 {
0082     return (r >> 16) & 0x3ff;
0083 }
0084 #define HOST1X_SYNC_CF_SETUP_LIMIT_V(r) \
0085     host1x_sync_cf_setup_limit_v(r)
0086 static inline u32 host1x_sync_cmdproc_stop_r(void)
0087 {
0088     return 0xac;
0089 }
0090 #define HOST1X_SYNC_CMDPROC_STOP \
0091     host1x_sync_cmdproc_stop_r()
0092 static inline u32 host1x_sync_ch_teardown_r(void)
0093 {
0094     return 0xb0;
0095 }
0096 #define HOST1X_SYNC_CH_TEARDOWN \
0097     host1x_sync_ch_teardown_r()
0098 static inline u32 host1x_sync_usec_clk_r(void)
0099 {
0100     return 0x1a4;
0101 }
0102 #define HOST1X_SYNC_USEC_CLK \
0103     host1x_sync_usec_clk_r()
0104 static inline u32 host1x_sync_ctxsw_timeout_cfg_r(void)
0105 {
0106     return 0x1a8;
0107 }
0108 #define HOST1X_SYNC_CTXSW_TIMEOUT_CFG \
0109     host1x_sync_ctxsw_timeout_cfg_r()
0110 static inline u32 host1x_sync_ip_busy_timeout_r(void)
0111 {
0112     return 0x1bc;
0113 }
0114 #define HOST1X_SYNC_IP_BUSY_TIMEOUT \
0115     host1x_sync_ip_busy_timeout_r()
0116 static inline u32 host1x_sync_mlock_owner_r(unsigned int id)
0117 {
0118     return 0x340 + id * REGISTER_STRIDE;
0119 }
0120 #define HOST1X_SYNC_MLOCK_OWNER(id) \
0121     host1x_sync_mlock_owner_r(id)
0122 static inline u32 host1x_sync_mlock_owner_chid_v(u32 v)
0123 {
0124     return (v >> 8) & 0xf;
0125 }
0126 #define HOST1X_SYNC_MLOCK_OWNER_CHID_V(v) \
0127     host1x_sync_mlock_owner_chid_v(v)
0128 static inline u32 host1x_sync_mlock_owner_cpu_owns_v(u32 r)
0129 {
0130     return (r >> 1) & 0x1;
0131 }
0132 #define HOST1X_SYNC_MLOCK_OWNER_CPU_OWNS_V(r) \
0133     host1x_sync_mlock_owner_cpu_owns_v(r)
0134 static inline u32 host1x_sync_mlock_owner_ch_owns_v(u32 r)
0135 {
0136     return (r >> 0) & 0x1;
0137 }
0138 #define HOST1X_SYNC_MLOCK_OWNER_CH_OWNS_V(r) \
0139     host1x_sync_mlock_owner_ch_owns_v(r)
0140 static inline u32 host1x_sync_syncpt_int_thresh_r(unsigned int id)
0141 {
0142     return 0x500 + id * REGISTER_STRIDE;
0143 }
0144 #define HOST1X_SYNC_SYNCPT_INT_THRESH(id) \
0145     host1x_sync_syncpt_int_thresh_r(id)
0146 static inline u32 host1x_sync_syncpt_base_r(unsigned int id)
0147 {
0148     return 0x600 + id * REGISTER_STRIDE;
0149 }
0150 #define HOST1X_SYNC_SYNCPT_BASE(id) \
0151     host1x_sync_syncpt_base_r(id)
0152 static inline u32 host1x_sync_syncpt_cpu_incr_r(unsigned int id)
0153 {
0154     return 0x700 + id * REGISTER_STRIDE;
0155 }
0156 #define HOST1X_SYNC_SYNCPT_CPU_INCR(id) \
0157     host1x_sync_syncpt_cpu_incr_r(id)
0158 static inline u32 host1x_sync_cbread_r(unsigned int channel)
0159 {
0160     return 0x720 + channel * REGISTER_STRIDE;
0161 }
0162 #define HOST1X_SYNC_CBREAD(channel) \
0163     host1x_sync_cbread_r(channel)
0164 static inline u32 host1x_sync_cfpeek_ctrl_r(void)
0165 {
0166     return 0x74c;
0167 }
0168 #define HOST1X_SYNC_CFPEEK_CTRL \
0169     host1x_sync_cfpeek_ctrl_r()
0170 static inline u32 host1x_sync_cfpeek_ctrl_addr_f(u32 v)
0171 {
0172     return (v & 0x3ff) << 0;
0173 }
0174 #define HOST1X_SYNC_CFPEEK_CTRL_ADDR_F(v) \
0175     host1x_sync_cfpeek_ctrl_addr_f(v)
0176 static inline u32 host1x_sync_cfpeek_ctrl_channr_f(u32 v)
0177 {
0178     return (v & 0xf) << 16;
0179 }
0180 #define HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(v) \
0181     host1x_sync_cfpeek_ctrl_channr_f(v)
0182 static inline u32 host1x_sync_cfpeek_ctrl_ena_f(u32 v)
0183 {
0184     return (v & 0x1) << 31;
0185 }
0186 #define HOST1X_SYNC_CFPEEK_CTRL_ENA_F(v) \
0187     host1x_sync_cfpeek_ctrl_ena_f(v)
0188 static inline u32 host1x_sync_cfpeek_read_r(void)
0189 {
0190     return 0x750;
0191 }
0192 #define HOST1X_SYNC_CFPEEK_READ \
0193     host1x_sync_cfpeek_read_r()
0194 static inline u32 host1x_sync_cfpeek_ptrs_r(void)
0195 {
0196     return 0x754;
0197 }
0198 #define HOST1X_SYNC_CFPEEK_PTRS \
0199     host1x_sync_cfpeek_ptrs_r()
0200 static inline u32 host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(u32 r)
0201 {
0202     return (r >> 0) & 0x3ff;
0203 }
0204 #define HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_V(r) \
0205     host1x_sync_cfpeek_ptrs_cf_rd_ptr_v(r)
0206 static inline u32 host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(u32 r)
0207 {
0208     return (r >> 16) & 0x3ff;
0209 }
0210 #define HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_V(r) \
0211     host1x_sync_cfpeek_ptrs_cf_wr_ptr_v(r)
0212 static inline u32 host1x_sync_cbstat_r(unsigned int channel)
0213 {
0214     return 0x758 + channel * REGISTER_STRIDE;
0215 }
0216 #define HOST1X_SYNC_CBSTAT(channel) \
0217     host1x_sync_cbstat_r(channel)
0218 static inline u32 host1x_sync_cbstat_cboffset_v(u32 r)
0219 {
0220     return (r >> 0) & 0xffff;
0221 }
0222 #define HOST1X_SYNC_CBSTAT_CBOFFSET_V(r) \
0223     host1x_sync_cbstat_cboffset_v(r)
0224 static inline u32 host1x_sync_cbstat_cbclass_v(u32 r)
0225 {
0226     return (r >> 16) & 0x3ff;
0227 }
0228 #define HOST1X_SYNC_CBSTAT_CBCLASS_V(r) \
0229     host1x_sync_cbstat_cbclass_v(r)
0230
0231 #endif