host1x/hw/hw_host1x01_channel.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2012-2013, NVIDIA Corporation.
0004  */
0005
0006  /*
0007   * Function naming determines intended use:
0008   *
0009   *     <x>_r(void) : Returns the offset for register <x>.
0010   *
0011   *     <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
0012   *
0013   *     <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
0014   *
0015   *     <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
0016   *         and masked to place it at field <y> of register <x>.  This value
0017   *         can be |'d with others to produce a full register value for
0018   *         register <x>.
0019   *
0020   *     <x>_<y>_m(void) : Returns a mask for field <y> of register <x>.  This
0021   *         value can be ~'d and then &'d to clear the value of field <y> for
0022   *         register <x>.
0023   *
0024   *     <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
0025   *         to place it at field <y> of register <x>.  This value can be |'d
0026   *         with others to produce a full register value for <x>.
0027   *
0028   *     <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
0029   *         <x> value 'r' after being shifted to place its LSB at bit 0.
0030   *         This value is suitable for direct comparison with other unshifted
0031   *         values appropriate for use in field <y> of register <x>.
0032   *
0033   *     <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
0034   *         field <y> of register <x>.  This value is suitable for direct
0035   *         comparison with unshifted values appropriate for use in field <y>
0036   *         of register <x>.
0037   */
0038
0039 #ifndef __hw_host1x_channel_host1x_h__
0040 #define __hw_host1x_channel_host1x_h__
0041
0042 static inline u32 host1x_channel_fifostat_r(void)
0043 {
0044     return 0x0;
0045 }
0046 #define HOST1X_CHANNEL_FIFOSTAT \
0047     host1x_channel_fifostat_r()
0048 static inline u32 host1x_channel_fifostat_cfempty_v(u32 r)
0049 {
0050     return (r >> 10) & 0x1;
0051 }
0052 #define HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_V(r) \
0053     host1x_channel_fifostat_cfempty_v(r)
0054 static inline u32 host1x_channel_dmastart_r(void)
0055 {
0056     return 0x14;
0057 }
0058 #define HOST1X_CHANNEL_DMASTART \
0059     host1x_channel_dmastart_r()
0060 static inline u32 host1x_channel_dmaput_r(void)
0061 {
0062     return 0x18;
0063 }
0064 #define HOST1X_CHANNEL_DMAPUT \
0065     host1x_channel_dmaput_r()
0066 static inline u32 host1x_channel_dmaget_r(void)
0067 {
0068     return 0x1c;
0069 }
0070 #define HOST1X_CHANNEL_DMAGET \
0071     host1x_channel_dmaget_r()
0072 static inline u32 host1x_channel_dmaend_r(void)
0073 {
0074     return 0x20;
0075 }
0076 #define HOST1X_CHANNEL_DMAEND \
0077     host1x_channel_dmaend_r()
0078 static inline u32 host1x_channel_dmactrl_r(void)
0079 {
0080     return 0x24;
0081 }
0082 #define HOST1X_CHANNEL_DMACTRL \
0083     host1x_channel_dmactrl_r()
0084 static inline u32 host1x_channel_dmactrl_dmastop(void)
0085 {
0086     return 1 << 0;
0087 }
0088 #define HOST1X_CHANNEL_DMACTRL_DMASTOP \
0089     host1x_channel_dmactrl_dmastop()
0090 static inline u32 host1x_channel_dmactrl_dmastop_v(u32 r)
0091 {
0092     return (r >> 0) & 0x1;
0093 }
0094 #define HOST1X_CHANNEL_DMACTRL_DMASTOP_V(r) \
0095     host1x_channel_dmactrl_dmastop_v(r)
0096 static inline u32 host1x_channel_dmactrl_dmagetrst(void)
0097 {
0098     return 1 << 1;
0099 }
0100 #define HOST1X_CHANNEL_DMACTRL_DMAGETRST \
0101     host1x_channel_dmactrl_dmagetrst()
0102 static inline u32 host1x_channel_dmactrl_dmainitget(void)
0103 {
0104     return 1 << 2;
0105 }
0106 #define HOST1X_CHANNEL_DMACTRL_DMAINITGET \
0107     host1x_channel_dmactrl_dmainitget()
0108 #endif