host1x/hw/debug_hw_1x06.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2010 Google, Inc.
0004  * Author: Erik Gilling <konkers@android.com>
0005  *
0006  * Copyright (C) 2011-2017 NVIDIA Corporation
0007  */
0008
0009 #include "../dev.h"
0010 #include "../debug.h"
0011 #include "../cdma.h"
0012 #include "../channel.h"
0013
0014 static void host1x_debug_show_channel_cdma(struct host1x *host,
0015                        struct host1x_channel *ch,
0016                        struct output *o)
0017 {
0018     struct host1x_cdma *cdma = &ch->cdma;
0019     dma_addr_t dmastart = 0, dmaend = 0;
0020     u32 dmaput, dmaget, dmactrl;
0021     u32 offset, class;
0022     u32 ch_stat;
0023
0024 #if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) && HOST1X_HW >= 6
0025     dmastart = host1x_ch_readl(ch, HOST1X_CHANNEL_DMASTART_HI);
0026     dmastart <<= 32;
0027 #endif
0028     dmastart |= host1x_ch_readl(ch, HOST1X_CHANNEL_DMASTART);
0029
0030 #if defined(CONFIG_ARCH_DMA_ADDR_T_64BIT) && HOST1X_HW >= 6
0031     dmaend = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAEND_HI);
0032     dmaend <<= 32;
0033 #endif
0034     dmaend |= host1x_ch_readl(ch, HOST1X_CHANNEL_DMAEND);
0035
0036     dmaput = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT);
0037     dmaget = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET);
0038     dmactrl = host1x_ch_readl(ch, HOST1X_CHANNEL_DMACTRL);
0039     offset = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDP_OFFSET);
0040     class = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDP_CLASS);
0041     ch_stat = host1x_ch_readl(ch, HOST1X_CHANNEL_CHANNELSTAT);
0042
0043     host1x_debug_output(o, "%u-%s: ", ch->id, dev_name(ch->dev));
0044
0045     if (dmactrl & HOST1X_CHANNEL_DMACTRL_DMASTOP ||
0046         !ch->cdma.push_buffer.mapped) {
0047         host1x_debug_output(o, "inactive\n\n");
0048         return;
0049     }
0050
0051     if (class == HOST1X_CLASS_HOST1X && offset == HOST1X_UCLASS_WAIT_SYNCPT)
0052         host1x_debug_output(o, "waiting on syncpt\n");
0053     else
0054         host1x_debug_output(o, "active class %02x, offset %04x\n",
0055                     class, offset);
0056
0057     host1x_debug_output(o, "DMASTART %pad, DMAEND %pad\n", &dmastart, &dmaend);
0058     host1x_debug_output(o, "DMAPUT %08x DMAGET %08x DMACTL %08x\n",
0059                 dmaput, dmaget, dmactrl);
0060     host1x_debug_output(o, "CHANNELSTAT %02x\n", ch_stat);
0061
0062     show_channel_gathers(o, cdma);
0063     host1x_debug_output(o, "\n");
0064 }
0065
0066 static void host1x_debug_show_channel_fifo(struct host1x *host,
0067                        struct host1x_channel *ch,
0068                        struct output *o)
0069 {
0070 #if HOST1X_HW <= 6
0071     u32 rd_ptr, wr_ptr, start, end;
0072     u32 payload = INVALID_PAYLOAD;
0073     unsigned int data_count = 0;
0074 #endif
0075     u32 val;
0076
0077     host1x_debug_output(o, "%u: fifo:\n", ch->id);
0078
0079     val = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDFIFO_STAT);
0080     host1x_debug_output(o, "CMDFIFO_STAT %08x\n", val);
0081     if (val & HOST1X_CHANNEL_CMDFIFO_STAT_EMPTY) {
0082         host1x_debug_output(o, "[empty]\n");
0083         return;
0084     }
0085
0086     val = host1x_ch_readl(ch, HOST1X_CHANNEL_CMDFIFO_RDATA);
0087     host1x_debug_output(o, "CMDFIFO_RDATA %08x\n", val);
0088
0089 #if HOST1X_HW <= 6
0090     /* Peek pointer values are invalid during SLCG, so disable it */
0091     host1x_hypervisor_writel(host, 0x1, HOST1X_HV_ICG_EN_OVERRIDE);
0092
0093     val = 0;
0094     val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE;
0095     val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(ch->id);
0096     host1x_hypervisor_writel(host, val, HOST1X_HV_CMDFIFO_PEEK_CTRL);
0097
0098     val = host1x_hypervisor_readl(host, HOST1X_HV_CMDFIFO_PEEK_PTRS);
0099     rd_ptr = HOST1X_HV_CMDFIFO_PEEK_PTRS_RD_PTR_V(val);
0100     wr_ptr = HOST1X_HV_CMDFIFO_PEEK_PTRS_WR_PTR_V(val);
0101
0102     val = host1x_hypervisor_readl(host, HOST1X_HV_CMDFIFO_SETUP(ch->id));
0103     start = HOST1X_HV_CMDFIFO_SETUP_BASE_V(val);
0104     end = HOST1X_HV_CMDFIFO_SETUP_LIMIT_V(val);
0105
0106     do {
0107         val = 0;
0108         val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_ENABLE;
0109         val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_CHANNEL(ch->id);
0110         val |= HOST1X_HV_CMDFIFO_PEEK_CTRL_ADDR(rd_ptr);
0111         host1x_hypervisor_writel(host, val,
0112                      HOST1X_HV_CMDFIFO_PEEK_CTRL);
0113
0114         val = host1x_hypervisor_readl(host,
0115                           HOST1X_HV_CMDFIFO_PEEK_READ);
0116
0117         if (!data_count) {
0118             host1x_debug_output(o, "%03x 0x%08x: ",
0119                         rd_ptr - start, val);
0120             data_count = show_channel_command(o, val, &payload);
0121         } else {
0122             host1x_debug_cont(o, "%08x%s", val,
0123                       data_count > 1 ? ", " : "])\n");
0124             data_count--;
0125         }
0126
0127         if (rd_ptr == end)
0128             rd_ptr = start;
0129         else
0130             rd_ptr++;
0131     } while (rd_ptr != wr_ptr);
0132
0133     if (data_count)
0134         host1x_debug_cont(o, ", ...])\n");
0135     host1x_debug_output(o, "\n");
0136
0137     host1x_hypervisor_writel(host, 0x0, HOST1X_HV_CMDFIFO_PEEK_CTRL);
0138     host1x_hypervisor_writel(host, 0x0, HOST1X_HV_ICG_EN_OVERRIDE);
0139 #endif
0140 }
0141
0142 static void host1x_debug_show_mlocks(struct host1x *host, struct output *o)
0143 {
0144     /* TODO */
0145 }