host1x/hw/debug_hw_1x01.c

0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2010 Google, Inc.
0004  * Author: Erik Gilling <konkers@android.com>
0005  *
0006  * Copyright (C) 2011-2013 NVIDIA Corporation
0007  */
0008
0009 #include "../dev.h"
0010 #include "../debug.h"
0011 #include "../cdma.h"
0012 #include "../channel.h"
0013
0014 static void host1x_debug_show_channel_cdma(struct host1x *host,
0015                        struct host1x_channel *ch,
0016                        struct output *o)
0017 {
0018     struct host1x_cdma *cdma = &ch->cdma;
0019     dma_addr_t dmastart, dmaend;
0020     u32 dmaput, dmaget, dmactrl;
0021     u32 cbstat, cbread;
0022     u32 val, base, baseval;
0023
0024     dmastart = host1x_ch_readl(ch, HOST1X_CHANNEL_DMASTART);
0025     dmaend = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAEND);
0026     dmaput = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAPUT);
0027     dmaget = host1x_ch_readl(ch, HOST1X_CHANNEL_DMAGET);
0028     dmactrl = host1x_ch_readl(ch, HOST1X_CHANNEL_DMACTRL);
0029     cbread = host1x_sync_readl(host, HOST1X_SYNC_CBREAD(ch->id));
0030     cbstat = host1x_sync_readl(host, HOST1X_SYNC_CBSTAT(ch->id));
0031
0032     host1x_debug_output(o, "%u-%s: ", ch->id, dev_name(ch->dev));
0033
0034     if (HOST1X_CHANNEL_DMACTRL_DMASTOP_V(dmactrl) ||
0035         !ch->cdma.push_buffer.mapped) {
0036         host1x_debug_output(o, "inactive\n\n");
0037         return;
0038     }
0039
0040     if (HOST1X_SYNC_CBSTAT_CBCLASS_V(cbstat) == HOST1X_CLASS_HOST1X &&
0041         HOST1X_SYNC_CBSTAT_CBOFFSET_V(cbstat) ==
0042             HOST1X_UCLASS_WAIT_SYNCPT)
0043         host1x_debug_output(o, "waiting on syncpt %d val %d\n",
0044                     cbread >> 24, cbread & 0xffffff);
0045     else if (HOST1X_SYNC_CBSTAT_CBCLASS_V(cbstat) ==
0046                 HOST1X_CLASS_HOST1X &&
0047          HOST1X_SYNC_CBSTAT_CBOFFSET_V(cbstat) ==
0048                 HOST1X_UCLASS_WAIT_SYNCPT_BASE) {
0049         base = (cbread >> 16) & 0xff;
0050         baseval =
0051             host1x_sync_readl(host, HOST1X_SYNC_SYNCPT_BASE(base));
0052         val = cbread & 0xffff;
0053         host1x_debug_output(o, "waiting on syncpt %d val %d (base %d = %d; offset = %d)\n",
0054                     cbread >> 24, baseval + val, base,
0055                     baseval, val);
0056     } else
0057         host1x_debug_output(o, "active class %02x, offset %04x, val %08x\n",
0058                     HOST1X_SYNC_CBSTAT_CBCLASS_V(cbstat),
0059                     HOST1X_SYNC_CBSTAT_CBOFFSET_V(cbstat),
0060                     cbread);
0061
0062     host1x_debug_output(o, "DMASTART %pad, DMAEND %pad\n", &dmastart, &dmaend);
0063     host1x_debug_output(o, "DMAPUT %08x DMAGET %08x DMACTL %08x\n",
0064                 dmaput, dmaget, dmactrl);
0065     host1x_debug_output(o, "CBREAD %08x CBSTAT %08x\n", cbread, cbstat);
0066
0067     show_channel_gathers(o, cdma);
0068     host1x_debug_output(o, "\n");
0069 }
0070
0071 static void host1x_debug_show_channel_fifo(struct host1x *host,
0072                        struct host1x_channel *ch,
0073                        struct output *o)
0074 {
0075     u32 val, rd_ptr, wr_ptr, start, end;
0076     unsigned int data_count = 0;
0077
0078     host1x_debug_output(o, "%u: fifo:\n", ch->id);
0079
0080     val = host1x_ch_readl(ch, HOST1X_CHANNEL_FIFOSTAT);
0081     host1x_debug_output(o, "FIFOSTAT %08x\n", val);
0082     if (HOST1X_CHANNEL_FIFOSTAT_CFEMPTY_V(val)) {
0083         host1x_debug_output(o, "[empty]\n");
0084         return;
0085     }
0086
0087     host1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL);
0088     host1x_sync_writel(host, HOST1X_SYNC_CFPEEK_CTRL_ENA_F(1) |
0089                HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(ch->id),
0090                HOST1X_SYNC_CFPEEK_CTRL);
0091
0092     val = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_PTRS);
0093     rd_ptr = HOST1X_SYNC_CFPEEK_PTRS_CF_RD_PTR_V(val);
0094     wr_ptr = HOST1X_SYNC_CFPEEK_PTRS_CF_WR_PTR_V(val);
0095
0096     val = host1x_sync_readl(host, HOST1X_SYNC_CF_SETUP(ch->id));
0097     start = HOST1X_SYNC_CF_SETUP_BASE_V(val);
0098     end = HOST1X_SYNC_CF_SETUP_LIMIT_V(val);
0099
0100     do {
0101         host1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL);
0102         host1x_sync_writel(host, HOST1X_SYNC_CFPEEK_CTRL_ENA_F(1) |
0103                    HOST1X_SYNC_CFPEEK_CTRL_CHANNR_F(ch->id) |
0104                    HOST1X_SYNC_CFPEEK_CTRL_ADDR_F(rd_ptr),
0105                    HOST1X_SYNC_CFPEEK_CTRL);
0106         val = host1x_sync_readl(host, HOST1X_SYNC_CFPEEK_READ);
0107
0108         if (!data_count) {
0109             host1x_debug_output(o, "%08x: ", val);
0110             data_count = show_channel_command(o, val, NULL);
0111         } else {
0112             host1x_debug_cont(o, "%08x%s", val,
0113                       data_count > 1 ? ", " : "])\n");
0114             data_count--;
0115         }
0116
0117         if (rd_ptr == end)
0118             rd_ptr = start;
0119         else
0120             rd_ptr++;
0121     } while (rd_ptr != wr_ptr);
0122
0123     if (data_count)
0124         host1x_debug_cont(o, ", ...])\n");
0125     host1x_debug_output(o, "\n");
0126
0127     host1x_sync_writel(host, 0x0, HOST1X_SYNC_CFPEEK_CTRL);
0128 }
0129
0130 static void host1x_debug_show_mlocks(struct host1x *host, struct output *o)
0131 {
0132     unsigned int i;
0133
0134     host1x_debug_output(o, "---- mlocks ----\n");
0135
0136     for (i = 0; i < host1x_syncpt_nb_mlocks(host); i++) {
0137         u32 owner =
0138             host1x_sync_readl(host, HOST1X_SYNC_MLOCK_OWNER(i));
0139         if (HOST1X_SYNC_MLOCK_OWNER_CH_OWNS_V(owner))
0140             host1x_debug_output(o, "%u: locked by channel %u\n",
0141                 i, HOST1X_SYNC_MLOCK_OWNER_CHID_V(owner));
0142         else if (HOST1X_SYNC_MLOCK_OWNER_CPU_OWNS_V(owner))
0143             host1x_debug_output(o, "%u: locked by cpu\n", i);
0144         else
0145             host1x_debug_output(o, "%u: unlocked\n", i);
0146     }
0147
0148     host1x_debug_output(o, "\n");
0149 }