gpu/host1x/cdma.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Tegra host1x Command DMA
0004  *
0005  * Copyright (c) 2010-2013, NVIDIA Corporation.
0006  */
0007
0008 #ifndef __HOST1X_CDMA_H
0009 #define __HOST1X_CDMA_H
0010
0011 #include <linux/sched.h>
0012 #include <linux/completion.h>
0013 #include <linux/list.h>
0014
0015 struct host1x_syncpt;
0016 struct host1x_userctx_timeout;
0017 struct host1x_job;
0018
0019 /*
0020  * cdma
0021  *
0022  * This is in charge of a host command DMA channel.
0023  * Sends ops to a push buffer, and takes responsibility for unpinning
0024  * (& possibly freeing) of memory after those ops have completed.
0025  * Producer:
0026  *  begin
0027  *      push - send ops to the push buffer
0028  *  end - start command DMA and enqueue handles to be unpinned
0029  * Consumer:
0030  *  update - call to update sync queue and push buffer, unpin memory
0031  */
0032
0033 struct push_buffer {
0034     void *mapped;           /* mapped pushbuffer memory */
0035     dma_addr_t dma;         /* device address of pushbuffer */
0036     dma_addr_t phys;        /* physical address of pushbuffer */
0037     u32 fence;          /* index we've written */
0038     u32 pos;            /* index to write to */
0039     u32 size;
0040     u32 alloc_size;
0041 };
0042
0043 struct buffer_timeout {
0044     struct delayed_work wq;     /* work queue */
0045     bool initialized;       /* timer one-time setup flag */
0046     struct host1x_syncpt *syncpt;   /* buffer completion syncpt */
0047     u32 syncpt_val;         /* syncpt value when completed */
0048     ktime_t start_ktime;        /* starting time */
0049     /* context timeout information */
0050     struct host1x_client *client;
0051 };
0052
0053 enum cdma_event {
0054     CDMA_EVENT_NONE,        /* not waiting for any event */
0055     CDMA_EVENT_SYNC_QUEUE_EMPTY,    /* wait for empty sync queue */
0056     CDMA_EVENT_PUSH_BUFFER_SPACE    /* wait for space in push buffer */
0057 };
0058
0059 struct host1x_cdma {
0060     struct mutex lock;      /* controls access to shared state */
0061     struct completion complete; /* signalled when event occurs */
0062     enum cdma_event event;      /* event that complete is waiting for */
0063     unsigned int slots_used;    /* pb slots used in current submit */
0064     unsigned int slots_free;    /* pb slots free in current submit */
0065     unsigned int first_get;     /* DMAGET value, where submit begins */
0066     unsigned int last_pos;      /* last value written to DMAPUT */
0067     struct push_buffer push_buffer; /* channel's push buffer */
0068     struct list_head sync_queue;    /* job queue */
0069     struct buffer_timeout timeout;  /* channel's timeout state/wq */
0070     bool running;
0071     bool torndown;
0072 };
0073
0074 #define cdma_to_channel(cdma) container_of(cdma, struct host1x_channel, cdma)
0075 #define cdma_to_host1x(cdma) dev_get_drvdata(cdma_to_channel(cdma)->dev->parent)
0076 #define pb_to_cdma(pb) container_of(pb, struct host1x_cdma, push_buffer)
0077
0078 int host1x_cdma_init(struct host1x_cdma *cdma);
0079 int host1x_cdma_deinit(struct host1x_cdma *cdma);
0080 int host1x_cdma_begin(struct host1x_cdma *cdma, struct host1x_job *job);
0081 void host1x_cdma_push(struct host1x_cdma *cdma, u32 op1, u32 op2);
0082 void host1x_cdma_push_wide(struct host1x_cdma *cdma, u32 op1, u32 op2,
0083                u32 op3, u32 op4);
0084 void host1x_cdma_end(struct host1x_cdma *cdma, struct host1x_job *job);
0085 void host1x_cdma_update(struct host1x_cdma *cdma);
0086 void host1x_cdma_peek(struct host1x_cdma *cdma, u32 dmaget, int slot,
0087               u32 *out);
0088 unsigned int host1x_cdma_wait_locked(struct host1x_cdma *cdma,
0089                      enum cdma_event event);
0090 void host1x_cdma_update_sync_queue(struct host1x_cdma *cdma,
0091                    struct device *dev);
0092 #endif