drm/xlnx/zynqmp_dpsub.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * ZynqMP DPSUB Subsystem Driver
0004  *
0005  * Copyright (C) 2017 - 2020 Xilinx, Inc.
0006  *
0007  * Authors:
0008  * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
0009  * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
0010  */
0011
0012 #ifndef _ZYNQMP_DPSUB_H_
0013 #define _ZYNQMP_DPSUB_H_
0014
0015 struct clk;
0016 struct device;
0017 struct drm_device;
0018 struct zynqmp_disp;
0019 struct zynqmp_dp;
0020
0021 enum zynqmp_dpsub_format {
0022     ZYNQMP_DPSUB_FORMAT_RGB,
0023     ZYNQMP_DPSUB_FORMAT_YCRCB444,
0024     ZYNQMP_DPSUB_FORMAT_YCRCB422,
0025     ZYNQMP_DPSUB_FORMAT_YONLY,
0026 };
0027
0028 /**
0029  * struct zynqmp_dpsub - ZynqMP DisplayPort Subsystem
0030  * @drm: The DRM/KMS device
0031  * @dev: The physical device
0032  * @apb_clk: The APB clock
0033  * @disp: The display controller
0034  * @dp: The DisplayPort controller
0035  * @dma_align: DMA alignment constraint (must be a power of 2)
0036  */
0037 struct zynqmp_dpsub {
0038     struct drm_device drm;
0039     struct device *dev;
0040
0041     struct clk *apb_clk;
0042
0043     struct zynqmp_disp *disp;
0044     struct zynqmp_dp *dp;
0045
0046     unsigned int dma_align;
0047 };
0048
0049 static inline struct zynqmp_dpsub *to_zynqmp_dpsub(struct drm_device *drm)
0050 {
0051     return container_of(drm, struct zynqmp_dpsub, drm);
0052 }
0053
0054 #endif /* _ZYNQMP_DPSUB_H_ */