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0028 #include <drm/drm_atomic.h>
0029 #include <drm/drm_atomic_helper.h>
0030 #include <drm/drm_damage_helper.h>
0031 #include <drm/drm_fourcc.h>
0032 #include <drm/drm_plane_helper.h>
0033 #include <drm/drm_vblank.h>
0034
0035 #include "vmwgfx_kms.h"
0036 #include "vmw_surface_cache.h"
0037
0038 #define vmw_crtc_to_stdu(x) \
0039 container_of(x, struct vmw_screen_target_display_unit, base.crtc)
0040 #define vmw_encoder_to_stdu(x) \
0041 container_of(x, struct vmw_screen_target_display_unit, base.encoder)
0042 #define vmw_connector_to_stdu(x) \
0043 container_of(x, struct vmw_screen_target_display_unit, base.connector)
0044
0045
0046
0047 enum stdu_content_type {
0048 SAME_AS_DISPLAY = 0,
0049 SEPARATE_SURFACE,
0050 SEPARATE_BO
0051 };
0052
0053
0054
0055
0056
0057
0058
0059
0060
0061
0062
0063
0064
0065
0066
0067
0068 struct vmw_stdu_dirty {
0069 struct vmw_kms_dirty base;
0070 SVGA3dTransferType transfer;
0071 s32 left, right, top, bottom;
0072 s32 fb_left, fb_top;
0073 u32 pitch;
0074 union {
0075 struct vmw_buffer_object *buf;
0076 u32 sid;
0077 };
0078 };
0079
0080
0081
0082
0083
0084 struct vmw_stdu_update {
0085 SVGA3dCmdHeader header;
0086 SVGA3dCmdUpdateGBScreenTarget body;
0087 };
0088
0089 struct vmw_stdu_dma {
0090 SVGA3dCmdHeader header;
0091 SVGA3dCmdSurfaceDMA body;
0092 };
0093
0094 struct vmw_stdu_surface_copy {
0095 SVGA3dCmdHeader header;
0096 SVGA3dCmdSurfaceCopy body;
0097 };
0098
0099 struct vmw_stdu_update_gb_image {
0100 SVGA3dCmdHeader header;
0101 SVGA3dCmdUpdateGBImage body;
0102 };
0103
0104
0105
0106
0107
0108
0109
0110
0111
0112
0113
0114
0115
0116
0117
0118
0119 struct vmw_screen_target_display_unit {
0120 struct vmw_display_unit base;
0121 struct vmw_surface *display_srf;
0122 enum stdu_content_type content_fb_type;
0123 s32 display_width, display_height;
0124
0125 bool defined;
0126
0127
0128 unsigned int cpp;
0129 };
0130
0131
0132
0133 static void vmw_stdu_destroy(struct vmw_screen_target_display_unit *stdu);
0134
0135
0136
0137
0138
0139
0140
0141 static bool vmw_stdu_use_cpu_blit(const struct vmw_private *vmw)
0142 {
0143 return !(vmw->capabilities & SVGA_CAP_3D) || vmw->vram_size < (32 * 1024 * 1024);
0144 }
0145
0146
0147
0148
0149
0150
0151
0152 static void vmw_stdu_crtc_destroy(struct drm_crtc *crtc)
0153 {
0154 vmw_stdu_destroy(vmw_crtc_to_stdu(crtc));
0155 }
0156
0157
0158
0159
0160
0161
0162
0163
0164
0165
0166
0167
0168
0169
0170
0171
0172 static int vmw_stdu_define_st(struct vmw_private *dev_priv,
0173 struct vmw_screen_target_display_unit *stdu,
0174 struct drm_display_mode *mode,
0175 int crtc_x, int crtc_y)
0176 {
0177 struct {
0178 SVGA3dCmdHeader header;
0179 SVGA3dCmdDefineGBScreenTarget body;
0180 } *cmd;
0181
0182 cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
0183 if (unlikely(cmd == NULL))
0184 return -ENOMEM;
0185
0186 cmd->header.id = SVGA_3D_CMD_DEFINE_GB_SCREENTARGET;
0187 cmd->header.size = sizeof(cmd->body);
0188
0189 cmd->body.stid = stdu->base.unit;
0190 cmd->body.width = mode->hdisplay;
0191 cmd->body.height = mode->vdisplay;
0192 cmd->body.flags = (0 == cmd->body.stid) ? SVGA_STFLAG_PRIMARY : 0;
0193 cmd->body.dpi = 0;
0194 cmd->body.xRoot = crtc_x;
0195 cmd->body.yRoot = crtc_y;
0196
0197 stdu->base.set_gui_x = cmd->body.xRoot;
0198 stdu->base.set_gui_y = cmd->body.yRoot;
0199
0200 vmw_cmd_commit(dev_priv, sizeof(*cmd));
0201
0202 stdu->defined = true;
0203 stdu->display_width = mode->hdisplay;
0204 stdu->display_height = mode->vdisplay;
0205
0206 return 0;
0207 }
0208
0209
0210
0211
0212
0213
0214
0215
0216
0217
0218
0219
0220 static int vmw_stdu_bind_st(struct vmw_private *dev_priv,
0221 struct vmw_screen_target_display_unit *stdu,
0222 const struct vmw_resource *res)
0223 {
0224 SVGA3dSurfaceImageId image;
0225
0226 struct {
0227 SVGA3dCmdHeader header;
0228 SVGA3dCmdBindGBScreenTarget body;
0229 } *cmd;
0230
0231
0232 if (!stdu->defined) {
0233 DRM_ERROR("No screen target defined\n");
0234 return -EINVAL;
0235 }
0236
0237
0238 memset(&image, 0, sizeof(image));
0239 image.sid = res ? res->id : SVGA3D_INVALID_ID;
0240
0241 cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
0242 if (unlikely(cmd == NULL))
0243 return -ENOMEM;
0244
0245 cmd->header.id = SVGA_3D_CMD_BIND_GB_SCREENTARGET;
0246 cmd->header.size = sizeof(cmd->body);
0247
0248 cmd->body.stid = stdu->base.unit;
0249 cmd->body.image = image;
0250
0251 vmw_cmd_commit(dev_priv, sizeof(*cmd));
0252
0253 return 0;
0254 }
0255
0256
0257
0258
0259
0260
0261
0262
0263
0264
0265
0266
0267 static void vmw_stdu_populate_update(void *cmd, int unit,
0268 s32 left, s32 right, s32 top, s32 bottom)
0269 {
0270 struct vmw_stdu_update *update = cmd;
0271
0272 update->header.id = SVGA_3D_CMD_UPDATE_GB_SCREENTARGET;
0273 update->header.size = sizeof(update->body);
0274
0275 update->body.stid = unit;
0276 update->body.rect.x = left;
0277 update->body.rect.y = top;
0278 update->body.rect.w = right - left;
0279 update->body.rect.h = bottom - top;
0280 }
0281
0282
0283
0284
0285
0286
0287
0288
0289
0290
0291
0292
0293
0294
0295 static int vmw_stdu_update_st(struct vmw_private *dev_priv,
0296 struct vmw_screen_target_display_unit *stdu)
0297 {
0298 struct vmw_stdu_update *cmd;
0299
0300 if (!stdu->defined) {
0301 DRM_ERROR("No screen target defined");
0302 return -EINVAL;
0303 }
0304
0305 cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
0306 if (unlikely(cmd == NULL))
0307 return -ENOMEM;
0308
0309 vmw_stdu_populate_update(cmd, stdu->base.unit,
0310 0, stdu->display_width,
0311 0, stdu->display_height);
0312
0313 vmw_cmd_commit(dev_priv, sizeof(*cmd));
0314
0315 return 0;
0316 }
0317
0318
0319
0320
0321
0322
0323
0324
0325
0326 static int vmw_stdu_destroy_st(struct vmw_private *dev_priv,
0327 struct vmw_screen_target_display_unit *stdu)
0328 {
0329 int ret;
0330
0331 struct {
0332 SVGA3dCmdHeader header;
0333 SVGA3dCmdDestroyGBScreenTarget body;
0334 } *cmd;
0335
0336
0337
0338 if (unlikely(!stdu->defined))
0339 return 0;
0340
0341 cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
0342 if (unlikely(cmd == NULL))
0343 return -ENOMEM;
0344
0345 cmd->header.id = SVGA_3D_CMD_DESTROY_GB_SCREENTARGET;
0346 cmd->header.size = sizeof(cmd->body);
0347
0348 cmd->body.stid = stdu->base.unit;
0349
0350 vmw_cmd_commit(dev_priv, sizeof(*cmd));
0351
0352
0353 ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ);
0354 if (unlikely(ret != 0))
0355 DRM_ERROR("Failed to sync with HW");
0356
0357 stdu->defined = false;
0358 stdu->display_width = 0;
0359 stdu->display_height = 0;
0360
0361 return ret;
0362 }
0363
0364
0365
0366
0367
0368
0369
0370
0371
0372
0373 static void vmw_stdu_crtc_mode_set_nofb(struct drm_crtc *crtc)
0374 {
0375 struct vmw_private *dev_priv;
0376 struct vmw_screen_target_display_unit *stdu;
0377 struct drm_connector_state *conn_state;
0378 struct vmw_connector_state *vmw_conn_state;
0379 int x, y, ret;
0380
0381 stdu = vmw_crtc_to_stdu(crtc);
0382 dev_priv = vmw_priv(crtc->dev);
0383 conn_state = stdu->base.connector.state;
0384 vmw_conn_state = vmw_connector_state_to_vcs(conn_state);
0385
0386 if (stdu->defined) {
0387 ret = vmw_stdu_bind_st(dev_priv, stdu, NULL);
0388 if (ret)
0389 DRM_ERROR("Failed to blank CRTC\n");
0390
0391 (void) vmw_stdu_update_st(dev_priv, stdu);
0392
0393 ret = vmw_stdu_destroy_st(dev_priv, stdu);
0394 if (ret)
0395 DRM_ERROR("Failed to destroy Screen Target\n");
0396
0397 stdu->content_fb_type = SAME_AS_DISPLAY;
0398 }
0399
0400 if (!crtc->state->enable)
0401 return;
0402
0403 x = vmw_conn_state->gui_x;
0404 y = vmw_conn_state->gui_y;
0405
0406 vmw_svga_enable(dev_priv);
0407 ret = vmw_stdu_define_st(dev_priv, stdu, &crtc->mode, x, y);
0408
0409 if (ret)
0410 DRM_ERROR("Failed to define Screen Target of size %dx%d\n",
0411 crtc->x, crtc->y);
0412 }
0413
0414
0415 static void vmw_stdu_crtc_helper_prepare(struct drm_crtc *crtc)
0416 {
0417 }
0418
0419 static void vmw_stdu_crtc_atomic_enable(struct drm_crtc *crtc,
0420 struct drm_atomic_state *state)
0421 {
0422 }
0423
0424 static void vmw_stdu_crtc_atomic_disable(struct drm_crtc *crtc,
0425 struct drm_atomic_state *state)
0426 {
0427 struct vmw_private *dev_priv;
0428 struct vmw_screen_target_display_unit *stdu;
0429 int ret;
0430
0431
0432 if (!crtc) {
0433 DRM_ERROR("CRTC is NULL\n");
0434 return;
0435 }
0436
0437 stdu = vmw_crtc_to_stdu(crtc);
0438 dev_priv = vmw_priv(crtc->dev);
0439
0440 if (stdu->defined) {
0441 ret = vmw_stdu_bind_st(dev_priv, stdu, NULL);
0442 if (ret)
0443 DRM_ERROR("Failed to blank CRTC\n");
0444
0445 (void) vmw_stdu_update_st(dev_priv, stdu);
0446
0447 ret = vmw_stdu_destroy_st(dev_priv, stdu);
0448 if (ret)
0449 DRM_ERROR("Failed to destroy Screen Target\n");
0450
0451 stdu->content_fb_type = SAME_AS_DISPLAY;
0452 }
0453 }
0454
0455
0456
0457
0458
0459
0460
0461
0462
0463 static void vmw_stdu_bo_clip(struct vmw_kms_dirty *dirty)
0464 {
0465 struct vmw_stdu_dirty *ddirty =
0466 container_of(dirty, struct vmw_stdu_dirty, base);
0467 struct vmw_stdu_dma *cmd = dirty->cmd;
0468 struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
0469
0470 blit += dirty->num_hits;
0471 blit->srcx = dirty->fb_x;
0472 blit->srcy = dirty->fb_y;
0473 blit->x = dirty->unit_x1;
0474 blit->y = dirty->unit_y1;
0475 blit->d = 1;
0476 blit->w = dirty->unit_x2 - dirty->unit_x1;
0477 blit->h = dirty->unit_y2 - dirty->unit_y1;
0478 dirty->num_hits++;
0479
0480 if (ddirty->transfer != SVGA3D_WRITE_HOST_VRAM)
0481 return;
0482
0483
0484 ddirty->left = min_t(s32, ddirty->left, dirty->unit_x1);
0485 ddirty->top = min_t(s32, ddirty->top, dirty->unit_y1);
0486 ddirty->right = max_t(s32, ddirty->right, dirty->unit_x2);
0487 ddirty->bottom = max_t(s32, ddirty->bottom, dirty->unit_y2);
0488 }
0489
0490
0491
0492
0493
0494
0495
0496
0497
0498 static void vmw_stdu_bo_fifo_commit(struct vmw_kms_dirty *dirty)
0499 {
0500 struct vmw_stdu_dirty *ddirty =
0501 container_of(dirty, struct vmw_stdu_dirty, base);
0502 struct vmw_screen_target_display_unit *stdu =
0503 container_of(dirty->unit, typeof(*stdu), base);
0504 struct vmw_stdu_dma *cmd = dirty->cmd;
0505 struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
0506 SVGA3dCmdSurfaceDMASuffix *suffix =
0507 (SVGA3dCmdSurfaceDMASuffix *) &blit[dirty->num_hits];
0508 size_t blit_size = sizeof(*blit) * dirty->num_hits + sizeof(*suffix);
0509
0510 if (!dirty->num_hits) {
0511 vmw_cmd_commit(dirty->dev_priv, 0);
0512 return;
0513 }
0514
0515 cmd->header.id = SVGA_3D_CMD_SURFACE_DMA;
0516 cmd->header.size = sizeof(cmd->body) + blit_size;
0517 vmw_bo_get_guest_ptr(&ddirty->buf->base, &cmd->body.guest.ptr);
0518 cmd->body.guest.pitch = ddirty->pitch;
0519 cmd->body.host.sid = stdu->display_srf->res.id;
0520 cmd->body.host.face = 0;
0521 cmd->body.host.mipmap = 0;
0522 cmd->body.transfer = ddirty->transfer;
0523 suffix->suffixSize = sizeof(*suffix);
0524 suffix->maximumOffset = ddirty->buf->base.base.size;
0525
0526 if (ddirty->transfer == SVGA3D_WRITE_HOST_VRAM) {
0527 blit_size += sizeof(struct vmw_stdu_update);
0528
0529 vmw_stdu_populate_update(&suffix[1], stdu->base.unit,
0530 ddirty->left, ddirty->right,
0531 ddirty->top, ddirty->bottom);
0532 }
0533
0534 vmw_cmd_commit(dirty->dev_priv, sizeof(*cmd) + blit_size);
0535
0536 stdu->display_srf->res.res_dirty = true;
0537 ddirty->left = ddirty->top = S32_MAX;
0538 ddirty->right = ddirty->bottom = S32_MIN;
0539 }
0540
0541
0542
0543
0544
0545
0546
0547
0548
0549 static void vmw_stdu_bo_cpu_clip(struct vmw_kms_dirty *dirty)
0550 {
0551 struct vmw_stdu_dirty *ddirty =
0552 container_of(dirty, struct vmw_stdu_dirty, base);
0553
0554 dirty->num_hits = 1;
0555
0556
0557 ddirty->left = min_t(s32, ddirty->left, dirty->unit_x1);
0558 ddirty->top = min_t(s32, ddirty->top, dirty->unit_y1);
0559 ddirty->right = max_t(s32, ddirty->right, dirty->unit_x2);
0560 ddirty->bottom = max_t(s32, ddirty->bottom, dirty->unit_y2);
0561
0562
0563
0564
0565
0566
0567 ddirty->fb_left = min_t(s32, ddirty->fb_left, dirty->fb_x);
0568 ddirty->fb_top = min_t(s32, ddirty->fb_top, dirty->fb_y);
0569 }
0570
0571
0572
0573
0574
0575
0576
0577
0578
0579
0580 static void vmw_stdu_bo_cpu_commit(struct vmw_kms_dirty *dirty)
0581 {
0582 struct vmw_stdu_dirty *ddirty =
0583 container_of(dirty, struct vmw_stdu_dirty, base);
0584 struct vmw_screen_target_display_unit *stdu =
0585 container_of(dirty->unit, typeof(*stdu), base);
0586 s32 width, height;
0587 s32 src_pitch, dst_pitch;
0588 struct ttm_buffer_object *src_bo, *dst_bo;
0589 u32 src_offset, dst_offset;
0590 struct vmw_diff_cpy diff = VMW_CPU_BLIT_DIFF_INITIALIZER(stdu->cpp);
0591
0592 if (!dirty->num_hits)
0593 return;
0594
0595 width = ddirty->right - ddirty->left;
0596 height = ddirty->bottom - ddirty->top;
0597
0598 if (width == 0 || height == 0)
0599 return;
0600
0601
0602 dst_pitch = stdu->display_srf->metadata.base_size.width * stdu->cpp;
0603 dst_bo = &stdu->display_srf->res.backup->base;
0604 dst_offset = ddirty->top * dst_pitch + ddirty->left * stdu->cpp;
0605
0606 src_pitch = ddirty->pitch;
0607 src_bo = &ddirty->buf->base;
0608 src_offset = ddirty->fb_top * src_pitch + ddirty->fb_left * stdu->cpp;
0609
0610
0611 if (ddirty->transfer != SVGA3D_WRITE_HOST_VRAM) {
0612 swap(dst_pitch, src_pitch);
0613 swap(dst_bo, src_bo);
0614 swap(src_offset, dst_offset);
0615 }
0616
0617 (void) vmw_bo_cpu_blit(dst_bo, dst_offset, dst_pitch,
0618 src_bo, src_offset, src_pitch,
0619 width * stdu->cpp, height, &diff);
0620
0621 if (ddirty->transfer == SVGA3D_WRITE_HOST_VRAM &&
0622 drm_rect_visible(&diff.rect)) {
0623 struct vmw_private *dev_priv;
0624 struct vmw_stdu_update *cmd;
0625 struct drm_clip_rect region;
0626 int ret;
0627
0628
0629 region.x1 = diff.rect.x1;
0630 region.x2 = diff.rect.x2;
0631 region.y1 = diff.rect.y1;
0632 region.y2 = diff.rect.y2;
0633 ret = vmw_kms_update_proxy(&stdu->display_srf->res, ®ion,
0634 1, 1);
0635 if (ret)
0636 goto out_cleanup;
0637
0638
0639 dev_priv = vmw_priv(stdu->base.crtc.dev);
0640 cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
0641 if (!cmd)
0642 goto out_cleanup;
0643
0644 vmw_stdu_populate_update(cmd, stdu->base.unit,
0645 region.x1, region.x2,
0646 region.y1, region.y2);
0647
0648 vmw_cmd_commit(dev_priv, sizeof(*cmd));
0649 }
0650
0651 out_cleanup:
0652 ddirty->left = ddirty->top = ddirty->fb_left = ddirty->fb_top = S32_MAX;
0653 ddirty->right = ddirty->bottom = S32_MIN;
0654 }
0655
0656
0657
0658
0659
0660
0661
0662
0663
0664
0665
0666
0667
0668
0669
0670
0671
0672
0673
0674
0675
0676
0677
0678
0679
0680
0681 int vmw_kms_stdu_dma(struct vmw_private *dev_priv,
0682 struct drm_file *file_priv,
0683 struct vmw_framebuffer *vfb,
0684 struct drm_vmw_fence_rep __user *user_fence_rep,
0685 struct drm_clip_rect *clips,
0686 struct drm_vmw_rect *vclips,
0687 uint32_t num_clips,
0688 int increment,
0689 bool to_surface,
0690 bool interruptible,
0691 struct drm_crtc *crtc)
0692 {
0693 struct vmw_buffer_object *buf =
0694 container_of(vfb, struct vmw_framebuffer_bo, base)->buffer;
0695 struct vmw_stdu_dirty ddirty;
0696 int ret;
0697 bool cpu_blit = vmw_stdu_use_cpu_blit(dev_priv);
0698 DECLARE_VAL_CONTEXT(val_ctx, NULL, 0);
0699
0700
0701
0702
0703
0704
0705 ret = vmw_validation_add_bo(&val_ctx, buf, false, cpu_blit);
0706 if (ret)
0707 return ret;
0708
0709 ret = vmw_validation_prepare(&val_ctx, NULL, interruptible);
0710 if (ret)
0711 goto out_unref;
0712
0713 ddirty.transfer = (to_surface) ? SVGA3D_WRITE_HOST_VRAM :
0714 SVGA3D_READ_HOST_VRAM;
0715 ddirty.left = ddirty.top = S32_MAX;
0716 ddirty.right = ddirty.bottom = S32_MIN;
0717 ddirty.fb_left = ddirty.fb_top = S32_MAX;
0718 ddirty.pitch = vfb->base.pitches[0];
0719 ddirty.buf = buf;
0720 ddirty.base.fifo_commit = vmw_stdu_bo_fifo_commit;
0721 ddirty.base.clip = vmw_stdu_bo_clip;
0722 ddirty.base.fifo_reserve_size = sizeof(struct vmw_stdu_dma) +
0723 num_clips * sizeof(SVGA3dCopyBox) +
0724 sizeof(SVGA3dCmdSurfaceDMASuffix);
0725 if (to_surface)
0726 ddirty.base.fifo_reserve_size += sizeof(struct vmw_stdu_update);
0727
0728
0729 if (cpu_blit) {
0730 ddirty.base.fifo_commit = vmw_stdu_bo_cpu_commit;
0731 ddirty.base.clip = vmw_stdu_bo_cpu_clip;
0732 ddirty.base.fifo_reserve_size = 0;
0733 }
0734
0735 ddirty.base.crtc = crtc;
0736
0737 ret = vmw_kms_helper_dirty(dev_priv, vfb, clips, vclips,
0738 0, 0, num_clips, increment, &ddirty.base);
0739
0740 vmw_kms_helper_validation_finish(dev_priv, file_priv, &val_ctx, NULL,
0741 user_fence_rep);
0742 return ret;
0743
0744 out_unref:
0745 vmw_validation_unref_lists(&val_ctx);
0746 return ret;
0747 }
0748
0749
0750
0751
0752
0753
0754
0755
0756
0757 static void vmw_kms_stdu_surface_clip(struct vmw_kms_dirty *dirty)
0758 {
0759 struct vmw_stdu_dirty *sdirty =
0760 container_of(dirty, struct vmw_stdu_dirty, base);
0761 struct vmw_stdu_surface_copy *cmd = dirty->cmd;
0762 struct vmw_screen_target_display_unit *stdu =
0763 container_of(dirty->unit, typeof(*stdu), base);
0764
0765 if (sdirty->sid != stdu->display_srf->res.id) {
0766 struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
0767
0768 blit += dirty->num_hits;
0769 blit->srcx = dirty->fb_x;
0770 blit->srcy = dirty->fb_y;
0771 blit->x = dirty->unit_x1;
0772 blit->y = dirty->unit_y1;
0773 blit->d = 1;
0774 blit->w = dirty->unit_x2 - dirty->unit_x1;
0775 blit->h = dirty->unit_y2 - dirty->unit_y1;
0776 }
0777
0778 dirty->num_hits++;
0779
0780
0781 sdirty->left = min_t(s32, sdirty->left, dirty->unit_x1);
0782 sdirty->top = min_t(s32, sdirty->top, dirty->unit_y1);
0783 sdirty->right = max_t(s32, sdirty->right, dirty->unit_x2);
0784 sdirty->bottom = max_t(s32, sdirty->bottom, dirty->unit_y2);
0785 }
0786
0787
0788
0789
0790
0791
0792
0793
0794
0795
0796 static void vmw_kms_stdu_surface_fifo_commit(struct vmw_kms_dirty *dirty)
0797 {
0798 struct vmw_stdu_dirty *sdirty =
0799 container_of(dirty, struct vmw_stdu_dirty, base);
0800 struct vmw_screen_target_display_unit *stdu =
0801 container_of(dirty->unit, typeof(*stdu), base);
0802 struct vmw_stdu_surface_copy *cmd = dirty->cmd;
0803 struct vmw_stdu_update *update;
0804 size_t blit_size = sizeof(SVGA3dCopyBox) * dirty->num_hits;
0805 size_t commit_size;
0806
0807 if (!dirty->num_hits) {
0808 vmw_cmd_commit(dirty->dev_priv, 0);
0809 return;
0810 }
0811
0812 if (sdirty->sid != stdu->display_srf->res.id) {
0813 struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
0814
0815 cmd->header.id = SVGA_3D_CMD_SURFACE_COPY;
0816 cmd->header.size = sizeof(cmd->body) + blit_size;
0817 cmd->body.src.sid = sdirty->sid;
0818 cmd->body.dest.sid = stdu->display_srf->res.id;
0819 update = (struct vmw_stdu_update *) &blit[dirty->num_hits];
0820 commit_size = sizeof(*cmd) + blit_size + sizeof(*update);
0821 stdu->display_srf->res.res_dirty = true;
0822 } else {
0823 update = dirty->cmd;
0824 commit_size = sizeof(*update);
0825 }
0826
0827 vmw_stdu_populate_update(update, stdu->base.unit, sdirty->left,
0828 sdirty->right, sdirty->top, sdirty->bottom);
0829
0830 vmw_cmd_commit(dirty->dev_priv, commit_size);
0831
0832 sdirty->left = sdirty->top = S32_MAX;
0833 sdirty->right = sdirty->bottom = S32_MIN;
0834 }
0835
0836
0837
0838
0839
0840
0841
0842
0843
0844
0845
0846
0847
0848
0849
0850
0851
0852
0853
0854
0855
0856
0857
0858 int vmw_kms_stdu_surface_dirty(struct vmw_private *dev_priv,
0859 struct vmw_framebuffer *framebuffer,
0860 struct drm_clip_rect *clips,
0861 struct drm_vmw_rect *vclips,
0862 struct vmw_resource *srf,
0863 s32 dest_x,
0864 s32 dest_y,
0865 unsigned num_clips, int inc,
0866 struct vmw_fence_obj **out_fence,
0867 struct drm_crtc *crtc)
0868 {
0869 struct vmw_framebuffer_surface *vfbs =
0870 container_of(framebuffer, typeof(*vfbs), base);
0871 struct vmw_stdu_dirty sdirty;
0872 DECLARE_VAL_CONTEXT(val_ctx, NULL, 0);
0873 int ret;
0874
0875 if (!srf)
0876 srf = &vfbs->surface->res;
0877
0878 ret = vmw_validation_add_resource(&val_ctx, srf, 0, VMW_RES_DIRTY_NONE,
0879 NULL, NULL);
0880 if (ret)
0881 return ret;
0882
0883 ret = vmw_validation_prepare(&val_ctx, &dev_priv->cmdbuf_mutex, true);
0884 if (ret)
0885 goto out_unref;
0886
0887 if (vfbs->is_bo_proxy) {
0888 ret = vmw_kms_update_proxy(srf, clips, num_clips, inc);
0889 if (ret)
0890 goto out_finish;
0891 }
0892
0893 sdirty.base.fifo_commit = vmw_kms_stdu_surface_fifo_commit;
0894 sdirty.base.clip = vmw_kms_stdu_surface_clip;
0895 sdirty.base.fifo_reserve_size = sizeof(struct vmw_stdu_surface_copy) +
0896 sizeof(SVGA3dCopyBox) * num_clips +
0897 sizeof(struct vmw_stdu_update);
0898 sdirty.base.crtc = crtc;
0899 sdirty.sid = srf->id;
0900 sdirty.left = sdirty.top = S32_MAX;
0901 sdirty.right = sdirty.bottom = S32_MIN;
0902
0903 ret = vmw_kms_helper_dirty(dev_priv, framebuffer, clips, vclips,
0904 dest_x, dest_y, num_clips, inc,
0905 &sdirty.base);
0906 out_finish:
0907 vmw_kms_helper_validation_finish(dev_priv, NULL, &val_ctx, out_fence,
0908 NULL);
0909
0910 return ret;
0911
0912 out_unref:
0913 vmw_validation_unref_lists(&val_ctx);
0914 return ret;
0915 }
0916
0917
0918
0919
0920
0921 static const struct drm_crtc_funcs vmw_stdu_crtc_funcs = {
0922 .gamma_set = vmw_du_crtc_gamma_set,
0923 .destroy = vmw_stdu_crtc_destroy,
0924 .reset = vmw_du_crtc_reset,
0925 .atomic_duplicate_state = vmw_du_crtc_duplicate_state,
0926 .atomic_destroy_state = vmw_du_crtc_destroy_state,
0927 .set_config = drm_atomic_helper_set_config,
0928 .page_flip = drm_atomic_helper_page_flip,
0929 .get_vblank_counter = vmw_get_vblank_counter,
0930 .enable_vblank = vmw_enable_vblank,
0931 .disable_vblank = vmw_disable_vblank,
0932 };
0933
0934
0935
0936
0937
0938
0939
0940
0941
0942
0943
0944
0945
0946
0947
0948
0949
0950 static void vmw_stdu_encoder_destroy(struct drm_encoder *encoder)
0951 {
0952 vmw_stdu_destroy(vmw_encoder_to_stdu(encoder));
0953 }
0954
0955 static const struct drm_encoder_funcs vmw_stdu_encoder_funcs = {
0956 .destroy = vmw_stdu_encoder_destroy,
0957 };
0958
0959
0960
0961
0962
0963
0964
0965
0966
0967
0968
0969
0970
0971
0972
0973
0974
0975 static void vmw_stdu_connector_destroy(struct drm_connector *connector)
0976 {
0977 vmw_stdu_destroy(vmw_connector_to_stdu(connector));
0978 }
0979
0980
0981
0982 static const struct drm_connector_funcs vmw_stdu_connector_funcs = {
0983 .dpms = vmw_du_connector_dpms,
0984 .detect = vmw_du_connector_detect,
0985 .fill_modes = vmw_du_connector_fill_modes,
0986 .destroy = vmw_stdu_connector_destroy,
0987 .reset = vmw_du_connector_reset,
0988 .atomic_duplicate_state = vmw_du_connector_duplicate_state,
0989 .atomic_destroy_state = vmw_du_connector_destroy_state,
0990 };
0991
0992
0993 static const struct
0994 drm_connector_helper_funcs vmw_stdu_connector_helper_funcs = {
0995 };
0996
0997
0998
0999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015 static void
1016 vmw_stdu_primary_plane_cleanup_fb(struct drm_plane *plane,
1017 struct drm_plane_state *old_state)
1018 {
1019 struct vmw_plane_state *vps = vmw_plane_state_to_vps(old_state);
1020
1021 if (vps->surf)
1022 WARN_ON(!vps->pinned);
1023
1024 vmw_du_plane_cleanup_fb(plane, old_state);
1025
1026 vps->content_fb_type = SAME_AS_DISPLAY;
1027 vps->cpp = 0;
1028 }
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044 static int
1045 vmw_stdu_primary_plane_prepare_fb(struct drm_plane *plane,
1046 struct drm_plane_state *new_state)
1047 {
1048 struct vmw_private *dev_priv = vmw_priv(plane->dev);
1049 struct drm_framebuffer *new_fb = new_state->fb;
1050 struct vmw_framebuffer *vfb;
1051 struct vmw_plane_state *vps = vmw_plane_state_to_vps(new_state);
1052 enum stdu_content_type new_content_type;
1053 struct vmw_framebuffer_surface *new_vfbs;
1054 uint32_t hdisplay = new_state->crtc_w, vdisplay = new_state->crtc_h;
1055 int ret;
1056
1057
1058 if (!new_fb) {
1059 if (vps->surf) {
1060 WARN_ON(vps->pinned != 0);
1061 vmw_surface_unreference(&vps->surf);
1062 }
1063
1064 return 0;
1065 }
1066
1067 vfb = vmw_framebuffer_to_vfb(new_fb);
1068 new_vfbs = (vfb->bo) ? NULL : vmw_framebuffer_to_vfbs(new_fb);
1069
1070 if (new_vfbs &&
1071 new_vfbs->surface->metadata.base_size.width == hdisplay &&
1072 new_vfbs->surface->metadata.base_size.height == vdisplay)
1073 new_content_type = SAME_AS_DISPLAY;
1074 else if (vfb->bo)
1075 new_content_type = SEPARATE_BO;
1076 else
1077 new_content_type = SEPARATE_SURFACE;
1078
1079 if (new_content_type != SAME_AS_DISPLAY) {
1080 struct vmw_surface_metadata metadata = {0};
1081
1082
1083
1084
1085
1086 if (new_content_type == SEPARATE_BO) {
1087
1088 switch (new_fb->format->cpp[0]*8) {
1089 case 32:
1090 metadata.format = SVGA3D_X8R8G8B8;
1091 break;
1092
1093 case 16:
1094 metadata.format = SVGA3D_R5G6B5;
1095 break;
1096
1097 case 8:
1098 metadata.format = SVGA3D_P8;
1099 break;
1100
1101 default:
1102 DRM_ERROR("Invalid format\n");
1103 return -EINVAL;
1104 }
1105
1106 metadata.mip_levels[0] = 1;
1107 metadata.num_sizes = 1;
1108 metadata.scanout = true;
1109 } else {
1110 metadata = new_vfbs->surface->metadata;
1111 }
1112
1113 metadata.base_size.width = hdisplay;
1114 metadata.base_size.height = vdisplay;
1115 metadata.base_size.depth = 1;
1116
1117 if (vps->surf) {
1118 struct drm_vmw_size cur_base_size =
1119 vps->surf->metadata.base_size;
1120
1121 if (cur_base_size.width != metadata.base_size.width ||
1122 cur_base_size.height != metadata.base_size.height ||
1123 vps->surf->metadata.format != metadata.format) {
1124 WARN_ON(vps->pinned != 0);
1125 vmw_surface_unreference(&vps->surf);
1126 }
1127
1128 }
1129
1130 if (!vps->surf) {
1131 ret = vmw_gb_surface_define(dev_priv, &metadata,
1132 &vps->surf);
1133 if (ret != 0) {
1134 DRM_ERROR("Couldn't allocate STDU surface.\n");
1135 return ret;
1136 }
1137 }
1138 } else {
1139
1140
1141
1142
1143
1144
1145 if (vps->surf) {
1146 WARN_ON(vps->pinned != 0);
1147 vmw_surface_unreference(&vps->surf);
1148 }
1149
1150 vps->surf = vmw_surface_reference(new_vfbs->surface);
1151 }
1152
1153 if (vps->surf) {
1154
1155
1156 ret = vmw_resource_pin(&vps->surf->res, false);
1157 if (ret)
1158 goto out_srf_unref;
1159
1160 vps->pinned++;
1161 }
1162
1163 vps->content_fb_type = new_content_type;
1164
1165
1166
1167
1168
1169
1170
1171 if (vps->content_fb_type == SEPARATE_BO &&
1172 vmw_stdu_use_cpu_blit(dev_priv))
1173 vps->cpp = new_fb->pitches[0] / new_fb->width;
1174
1175 return 0;
1176
1177 out_srf_unref:
1178 vmw_surface_unreference(&vps->surf);
1179 return ret;
1180 }
1181
1182 static uint32_t vmw_stdu_bo_fifo_size(struct vmw_du_update_plane *update,
1183 uint32_t num_hits)
1184 {
1185 return sizeof(struct vmw_stdu_dma) + sizeof(SVGA3dCopyBox) * num_hits +
1186 sizeof(SVGA3dCmdSurfaceDMASuffix) +
1187 sizeof(struct vmw_stdu_update);
1188 }
1189
1190 static uint32_t vmw_stdu_bo_fifo_size_cpu(struct vmw_du_update_plane *update,
1191 uint32_t num_hits)
1192 {
1193 return sizeof(struct vmw_stdu_update_gb_image) +
1194 sizeof(struct vmw_stdu_update);
1195 }
1196
1197 static uint32_t vmw_stdu_bo_populate_dma(struct vmw_du_update_plane *update,
1198 void *cmd, uint32_t num_hits)
1199 {
1200 struct vmw_screen_target_display_unit *stdu;
1201 struct vmw_framebuffer_bo *vfbbo;
1202 struct vmw_stdu_dma *cmd_dma = cmd;
1203
1204 stdu = container_of(update->du, typeof(*stdu), base);
1205 vfbbo = container_of(update->vfb, typeof(*vfbbo), base);
1206
1207 cmd_dma->header.id = SVGA_3D_CMD_SURFACE_DMA;
1208 cmd_dma->header.size = sizeof(cmd_dma->body) +
1209 sizeof(struct SVGA3dCopyBox) * num_hits +
1210 sizeof(SVGA3dCmdSurfaceDMASuffix);
1211 vmw_bo_get_guest_ptr(&vfbbo->buffer->base, &cmd_dma->body.guest.ptr);
1212 cmd_dma->body.guest.pitch = update->vfb->base.pitches[0];
1213 cmd_dma->body.host.sid = stdu->display_srf->res.id;
1214 cmd_dma->body.host.face = 0;
1215 cmd_dma->body.host.mipmap = 0;
1216 cmd_dma->body.transfer = SVGA3D_WRITE_HOST_VRAM;
1217
1218 return sizeof(*cmd_dma);
1219 }
1220
1221 static uint32_t vmw_stdu_bo_populate_clip(struct vmw_du_update_plane *update,
1222 void *cmd, struct drm_rect *clip,
1223 uint32_t fb_x, uint32_t fb_y)
1224 {
1225 struct SVGA3dCopyBox *box = cmd;
1226
1227 box->srcx = fb_x;
1228 box->srcy = fb_y;
1229 box->srcz = 0;
1230 box->x = clip->x1;
1231 box->y = clip->y1;
1232 box->z = 0;
1233 box->w = drm_rect_width(clip);
1234 box->h = drm_rect_height(clip);
1235 box->d = 1;
1236
1237 return sizeof(*box);
1238 }
1239
1240 static uint32_t vmw_stdu_bo_populate_update(struct vmw_du_update_plane *update,
1241 void *cmd, struct drm_rect *bb)
1242 {
1243 struct vmw_screen_target_display_unit *stdu;
1244 struct vmw_framebuffer_bo *vfbbo;
1245 SVGA3dCmdSurfaceDMASuffix *suffix = cmd;
1246
1247 stdu = container_of(update->du, typeof(*stdu), base);
1248 vfbbo = container_of(update->vfb, typeof(*vfbbo), base);
1249
1250 suffix->suffixSize = sizeof(*suffix);
1251 suffix->maximumOffset = vfbbo->buffer->base.base.size;
1252
1253 vmw_stdu_populate_update(&suffix[1], stdu->base.unit, bb->x1, bb->x2,
1254 bb->y1, bb->y2);
1255
1256 return sizeof(*suffix) + sizeof(struct vmw_stdu_update);
1257 }
1258
1259 static uint32_t vmw_stdu_bo_pre_clip_cpu(struct vmw_du_update_plane *update,
1260 void *cmd, uint32_t num_hits)
1261 {
1262 struct vmw_du_update_plane_buffer *bo_update =
1263 container_of(update, typeof(*bo_update), base);
1264
1265 bo_update->fb_left = INT_MAX;
1266 bo_update->fb_top = INT_MAX;
1267
1268 return 0;
1269 }
1270
1271 static uint32_t vmw_stdu_bo_clip_cpu(struct vmw_du_update_plane *update,
1272 void *cmd, struct drm_rect *clip,
1273 uint32_t fb_x, uint32_t fb_y)
1274 {
1275 struct vmw_du_update_plane_buffer *bo_update =
1276 container_of(update, typeof(*bo_update), base);
1277
1278 bo_update->fb_left = min_t(int, bo_update->fb_left, fb_x);
1279 bo_update->fb_top = min_t(int, bo_update->fb_top, fb_y);
1280
1281 return 0;
1282 }
1283
1284 static uint32_t
1285 vmw_stdu_bo_populate_update_cpu(struct vmw_du_update_plane *update, void *cmd,
1286 struct drm_rect *bb)
1287 {
1288 struct vmw_du_update_plane_buffer *bo_update;
1289 struct vmw_screen_target_display_unit *stdu;
1290 struct vmw_framebuffer_bo *vfbbo;
1291 struct vmw_diff_cpy diff = VMW_CPU_BLIT_DIFF_INITIALIZER(0);
1292 struct vmw_stdu_update_gb_image *cmd_img = cmd;
1293 struct vmw_stdu_update *cmd_update;
1294 struct ttm_buffer_object *src_bo, *dst_bo;
1295 u32 src_offset, dst_offset;
1296 s32 src_pitch, dst_pitch;
1297 s32 width, height;
1298
1299 bo_update = container_of(update, typeof(*bo_update), base);
1300 stdu = container_of(update->du, typeof(*stdu), base);
1301 vfbbo = container_of(update->vfb, typeof(*vfbbo), base);
1302
1303 width = bb->x2 - bb->x1;
1304 height = bb->y2 - bb->y1;
1305
1306 diff.cpp = stdu->cpp;
1307
1308 dst_bo = &stdu->display_srf->res.backup->base;
1309 dst_pitch = stdu->display_srf->metadata.base_size.width * stdu->cpp;
1310 dst_offset = bb->y1 * dst_pitch + bb->x1 * stdu->cpp;
1311
1312 src_bo = &vfbbo->buffer->base;
1313 src_pitch = update->vfb->base.pitches[0];
1314 src_offset = bo_update->fb_top * src_pitch + bo_update->fb_left *
1315 stdu->cpp;
1316
1317 (void) vmw_bo_cpu_blit(dst_bo, dst_offset, dst_pitch, src_bo,
1318 src_offset, src_pitch, width * stdu->cpp, height,
1319 &diff);
1320
1321 if (drm_rect_visible(&diff.rect)) {
1322 SVGA3dBox *box = &cmd_img->body.box;
1323
1324 cmd_img->header.id = SVGA_3D_CMD_UPDATE_GB_IMAGE;
1325 cmd_img->header.size = sizeof(cmd_img->body);
1326 cmd_img->body.image.sid = stdu->display_srf->res.id;
1327 cmd_img->body.image.face = 0;
1328 cmd_img->body.image.mipmap = 0;
1329
1330 box->x = diff.rect.x1;
1331 box->y = diff.rect.y1;
1332 box->z = 0;
1333 box->w = drm_rect_width(&diff.rect);
1334 box->h = drm_rect_height(&diff.rect);
1335 box->d = 1;
1336
1337 cmd_update = (struct vmw_stdu_update *)&cmd_img[1];
1338 vmw_stdu_populate_update(cmd_update, stdu->base.unit,
1339 diff.rect.x1, diff.rect.x2,
1340 diff.rect.y1, diff.rect.y2);
1341
1342 return sizeof(*cmd_img) + sizeof(*cmd_update);
1343 }
1344
1345 return 0;
1346 }
1347
1348
1349
1350
1351
1352
1353
1354
1355
1356
1357
1358
1359
1360 static int vmw_stdu_plane_update_bo(struct vmw_private *dev_priv,
1361 struct drm_plane *plane,
1362 struct drm_plane_state *old_state,
1363 struct vmw_framebuffer *vfb,
1364 struct vmw_fence_obj **out_fence)
1365 {
1366 struct vmw_du_update_plane_buffer bo_update;
1367
1368 memset(&bo_update, 0, sizeof(struct vmw_du_update_plane_buffer));
1369 bo_update.base.plane = plane;
1370 bo_update.base.old_state = old_state;
1371 bo_update.base.dev_priv = dev_priv;
1372 bo_update.base.du = vmw_crtc_to_du(plane->state->crtc);
1373 bo_update.base.vfb = vfb;
1374 bo_update.base.out_fence = out_fence;
1375 bo_update.base.mutex = NULL;
1376 bo_update.base.cpu_blit = vmw_stdu_use_cpu_blit(dev_priv);
1377 bo_update.base.intr = false;
1378
1379
1380
1381
1382
1383 if (bo_update.base.cpu_blit) {
1384 bo_update.base.calc_fifo_size = vmw_stdu_bo_fifo_size_cpu;
1385 bo_update.base.pre_clip = vmw_stdu_bo_pre_clip_cpu;
1386 bo_update.base.clip = vmw_stdu_bo_clip_cpu;
1387 bo_update.base.post_clip = vmw_stdu_bo_populate_update_cpu;
1388 } else {
1389 bo_update.base.calc_fifo_size = vmw_stdu_bo_fifo_size;
1390 bo_update.base.pre_clip = vmw_stdu_bo_populate_dma;
1391 bo_update.base.clip = vmw_stdu_bo_populate_clip;
1392 bo_update.base.post_clip = vmw_stdu_bo_populate_update;
1393 }
1394
1395 return vmw_du_helper_plane_update(&bo_update.base);
1396 }
1397
1398 static uint32_t
1399 vmw_stdu_surface_fifo_size_same_display(struct vmw_du_update_plane *update,
1400 uint32_t num_hits)
1401 {
1402 struct vmw_framebuffer_surface *vfbs;
1403 uint32_t size = 0;
1404
1405 vfbs = container_of(update->vfb, typeof(*vfbs), base);
1406
1407 if (vfbs->is_bo_proxy)
1408 size += sizeof(struct vmw_stdu_update_gb_image) * num_hits;
1409
1410 size += sizeof(struct vmw_stdu_update);
1411
1412 return size;
1413 }
1414
1415 static uint32_t vmw_stdu_surface_fifo_size(struct vmw_du_update_plane *update,
1416 uint32_t num_hits)
1417 {
1418 struct vmw_framebuffer_surface *vfbs;
1419 uint32_t size = 0;
1420
1421 vfbs = container_of(update->vfb, typeof(*vfbs), base);
1422
1423 if (vfbs->is_bo_proxy)
1424 size += sizeof(struct vmw_stdu_update_gb_image) * num_hits;
1425
1426 size += sizeof(struct vmw_stdu_surface_copy) + sizeof(SVGA3dCopyBox) *
1427 num_hits + sizeof(struct vmw_stdu_update);
1428
1429 return size;
1430 }
1431
1432 static uint32_t
1433 vmw_stdu_surface_update_proxy(struct vmw_du_update_plane *update, void *cmd)
1434 {
1435 struct vmw_framebuffer_surface *vfbs;
1436 struct drm_plane_state *state = update->plane->state;
1437 struct drm_plane_state *old_state = update->old_state;
1438 struct vmw_stdu_update_gb_image *cmd_update = cmd;
1439 struct drm_atomic_helper_damage_iter iter;
1440 struct drm_rect clip;
1441 uint32_t copy_size = 0;
1442
1443 vfbs = container_of(update->vfb, typeof(*vfbs), base);
1444
1445
1446
1447
1448
1449 drm_atomic_helper_damage_iter_init(&iter, old_state, state);
1450 drm_atomic_for_each_plane_damage(&iter, &clip) {
1451 SVGA3dBox *box = &cmd_update->body.box;
1452
1453 cmd_update->header.id = SVGA_3D_CMD_UPDATE_GB_IMAGE;
1454 cmd_update->header.size = sizeof(cmd_update->body);
1455 cmd_update->body.image.sid = vfbs->surface->res.id;
1456 cmd_update->body.image.face = 0;
1457 cmd_update->body.image.mipmap = 0;
1458
1459 box->x = clip.x1;
1460 box->y = clip.y1;
1461 box->z = 0;
1462 box->w = drm_rect_width(&clip);
1463 box->h = drm_rect_height(&clip);
1464 box->d = 1;
1465
1466 copy_size += sizeof(*cmd_update);
1467 cmd_update++;
1468 }
1469
1470 return copy_size;
1471 }
1472
1473 static uint32_t
1474 vmw_stdu_surface_populate_copy(struct vmw_du_update_plane *update, void *cmd,
1475 uint32_t num_hits)
1476 {
1477 struct vmw_screen_target_display_unit *stdu;
1478 struct vmw_framebuffer_surface *vfbs;
1479 struct vmw_stdu_surface_copy *cmd_copy = cmd;
1480
1481 stdu = container_of(update->du, typeof(*stdu), base);
1482 vfbs = container_of(update->vfb, typeof(*vfbs), base);
1483
1484 cmd_copy->header.id = SVGA_3D_CMD_SURFACE_COPY;
1485 cmd_copy->header.size = sizeof(cmd_copy->body) + sizeof(SVGA3dCopyBox) *
1486 num_hits;
1487 cmd_copy->body.src.sid = vfbs->surface->res.id;
1488 cmd_copy->body.dest.sid = stdu->display_srf->res.id;
1489
1490 return sizeof(*cmd_copy);
1491 }
1492
1493 static uint32_t
1494 vmw_stdu_surface_populate_clip(struct vmw_du_update_plane *update, void *cmd,
1495 struct drm_rect *clip, uint32_t fb_x,
1496 uint32_t fb_y)
1497 {
1498 struct SVGA3dCopyBox *box = cmd;
1499
1500 box->srcx = fb_x;
1501 box->srcy = fb_y;
1502 box->srcz = 0;
1503 box->x = clip->x1;
1504 box->y = clip->y1;
1505 box->z = 0;
1506 box->w = drm_rect_width(clip);
1507 box->h = drm_rect_height(clip);
1508 box->d = 1;
1509
1510 return sizeof(*box);
1511 }
1512
1513 static uint32_t
1514 vmw_stdu_surface_populate_update(struct vmw_du_update_plane *update, void *cmd,
1515 struct drm_rect *bb)
1516 {
1517 vmw_stdu_populate_update(cmd, update->du->unit, bb->x1, bb->x2, bb->y1,
1518 bb->y2);
1519
1520 return sizeof(struct vmw_stdu_update);
1521 }
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531
1532
1533
1534
1535 static int vmw_stdu_plane_update_surface(struct vmw_private *dev_priv,
1536 struct drm_plane *plane,
1537 struct drm_plane_state *old_state,
1538 struct vmw_framebuffer *vfb,
1539 struct vmw_fence_obj **out_fence)
1540 {
1541 struct vmw_du_update_plane srf_update;
1542 struct vmw_screen_target_display_unit *stdu;
1543 struct vmw_framebuffer_surface *vfbs;
1544
1545 stdu = vmw_crtc_to_stdu(plane->state->crtc);
1546 vfbs = container_of(vfb, typeof(*vfbs), base);
1547
1548 memset(&srf_update, 0, sizeof(struct vmw_du_update_plane));
1549 srf_update.plane = plane;
1550 srf_update.old_state = old_state;
1551 srf_update.dev_priv = dev_priv;
1552 srf_update.du = vmw_crtc_to_du(plane->state->crtc);
1553 srf_update.vfb = vfb;
1554 srf_update.out_fence = out_fence;
1555 srf_update.mutex = &dev_priv->cmdbuf_mutex;
1556 srf_update.cpu_blit = false;
1557 srf_update.intr = true;
1558
1559 if (vfbs->is_bo_proxy)
1560 srf_update.post_prepare = vmw_stdu_surface_update_proxy;
1561
1562 if (vfbs->surface->res.id != stdu->display_srf->res.id) {
1563 srf_update.calc_fifo_size = vmw_stdu_surface_fifo_size;
1564 srf_update.pre_clip = vmw_stdu_surface_populate_copy;
1565 srf_update.clip = vmw_stdu_surface_populate_clip;
1566 } else {
1567 srf_update.calc_fifo_size =
1568 vmw_stdu_surface_fifo_size_same_display;
1569 }
1570
1571 srf_update.post_clip = vmw_stdu_surface_populate_update;
1572
1573 return vmw_du_helper_plane_update(&srf_update);
1574 }
1575
1576
1577
1578
1579
1580
1581
1582
1583
1584
1585
1586 static void
1587 vmw_stdu_primary_plane_atomic_update(struct drm_plane *plane,
1588 struct drm_atomic_state *state)
1589 {
1590 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane);
1591 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
1592 struct vmw_plane_state *vps = vmw_plane_state_to_vps(new_state);
1593 struct drm_crtc *crtc = new_state->crtc;
1594 struct vmw_screen_target_display_unit *stdu;
1595 struct drm_pending_vblank_event *event;
1596 struct vmw_fence_obj *fence = NULL;
1597 struct vmw_private *dev_priv;
1598 int ret;
1599
1600
1601 if (crtc && new_state->fb) {
1602 struct vmw_framebuffer *vfb =
1603 vmw_framebuffer_to_vfb(new_state->fb);
1604 stdu = vmw_crtc_to_stdu(crtc);
1605 dev_priv = vmw_priv(crtc->dev);
1606
1607 stdu->display_srf = vps->surf;
1608 stdu->content_fb_type = vps->content_fb_type;
1609 stdu->cpp = vps->cpp;
1610
1611 ret = vmw_stdu_bind_st(dev_priv, stdu, &stdu->display_srf->res);
1612 if (ret)
1613 DRM_ERROR("Failed to bind surface to STDU.\n");
1614
1615 if (vfb->bo)
1616 ret = vmw_stdu_plane_update_bo(dev_priv, plane,
1617 old_state, vfb, &fence);
1618 else
1619 ret = vmw_stdu_plane_update_surface(dev_priv, plane,
1620 old_state, vfb,
1621 &fence);
1622 if (ret)
1623 DRM_ERROR("Failed to update STDU.\n");
1624 } else {
1625 crtc = old_state->crtc;
1626 stdu = vmw_crtc_to_stdu(crtc);
1627 dev_priv = vmw_priv(crtc->dev);
1628
1629
1630 if (!stdu->defined)
1631 return;
1632
1633 ret = vmw_stdu_bind_st(dev_priv, stdu, NULL);
1634 if (ret)
1635 DRM_ERROR("Failed to blank STDU\n");
1636
1637 ret = vmw_stdu_update_st(dev_priv, stdu);
1638 if (ret)
1639 DRM_ERROR("Failed to update STDU.\n");
1640
1641 return;
1642 }
1643
1644
1645 event = crtc->state->event;
1646 if (event && fence) {
1647 struct drm_file *file_priv = event->base.file_priv;
1648
1649 ret = vmw_event_fence_action_queue(file_priv,
1650 fence,
1651 &event->base,
1652 &event->event.vbl.tv_sec,
1653 &event->event.vbl.tv_usec,
1654 true);
1655 if (ret)
1656 DRM_ERROR("Failed to queue event on fence.\n");
1657 else
1658 crtc->state->event = NULL;
1659 }
1660
1661 if (fence)
1662 vmw_fence_obj_unreference(&fence);
1663 }
1664
1665
1666 static const struct drm_plane_funcs vmw_stdu_plane_funcs = {
1667 .update_plane = drm_atomic_helper_update_plane,
1668 .disable_plane = drm_atomic_helper_disable_plane,
1669 .destroy = vmw_du_primary_plane_destroy,
1670 .reset = vmw_du_plane_reset,
1671 .atomic_duplicate_state = vmw_du_plane_duplicate_state,
1672 .atomic_destroy_state = vmw_du_plane_destroy_state,
1673 };
1674
1675 static const struct drm_plane_funcs vmw_stdu_cursor_funcs = {
1676 .update_plane = drm_atomic_helper_update_plane,
1677 .disable_plane = drm_atomic_helper_disable_plane,
1678 .destroy = vmw_du_cursor_plane_destroy,
1679 .reset = vmw_du_plane_reset,
1680 .atomic_duplicate_state = vmw_du_plane_duplicate_state,
1681 .atomic_destroy_state = vmw_du_plane_destroy_state,
1682 };
1683
1684
1685
1686
1687
1688 static const struct
1689 drm_plane_helper_funcs vmw_stdu_cursor_plane_helper_funcs = {
1690 .atomic_check = vmw_du_cursor_plane_atomic_check,
1691 .atomic_update = vmw_du_cursor_plane_atomic_update,
1692 .prepare_fb = vmw_du_cursor_plane_prepare_fb,
1693 .cleanup_fb = vmw_du_cursor_plane_cleanup_fb,
1694 };
1695
1696 static const struct
1697 drm_plane_helper_funcs vmw_stdu_primary_plane_helper_funcs = {
1698 .atomic_check = vmw_du_primary_plane_atomic_check,
1699 .atomic_update = vmw_stdu_primary_plane_atomic_update,
1700 .prepare_fb = vmw_stdu_primary_plane_prepare_fb,
1701 .cleanup_fb = vmw_stdu_primary_plane_cleanup_fb,
1702 };
1703
1704 static const struct drm_crtc_helper_funcs vmw_stdu_crtc_helper_funcs = {
1705 .prepare = vmw_stdu_crtc_helper_prepare,
1706 .mode_set_nofb = vmw_stdu_crtc_mode_set_nofb,
1707 .atomic_check = vmw_du_crtc_atomic_check,
1708 .atomic_begin = vmw_du_crtc_atomic_begin,
1709 .atomic_flush = vmw_du_crtc_atomic_flush,
1710 .atomic_enable = vmw_stdu_crtc_atomic_enable,
1711 .atomic_disable = vmw_stdu_crtc_atomic_disable,
1712 };
1713
1714
1715
1716
1717
1718
1719
1720
1721
1722
1723
1724
1725 static int vmw_stdu_init(struct vmw_private *dev_priv, unsigned unit)
1726 {
1727 struct vmw_screen_target_display_unit *stdu;
1728 struct drm_device *dev = &dev_priv->drm;
1729 struct drm_connector *connector;
1730 struct drm_encoder *encoder;
1731 struct drm_plane *primary;
1732 struct vmw_cursor_plane *cursor;
1733 struct drm_crtc *crtc;
1734 int ret;
1735
1736 stdu = kzalloc(sizeof(*stdu), GFP_KERNEL);
1737 if (!stdu)
1738 return -ENOMEM;
1739
1740 stdu->base.unit = unit;
1741 crtc = &stdu->base.crtc;
1742 encoder = &stdu->base.encoder;
1743 connector = &stdu->base.connector;
1744 primary = &stdu->base.primary;
1745 cursor = &stdu->base.cursor;
1746
1747 stdu->base.pref_active = (unit == 0);
1748 stdu->base.pref_width = dev_priv->initial_width;
1749 stdu->base.pref_height = dev_priv->initial_height;
1750 stdu->base.is_implicit = false;
1751
1752
1753 ret = drm_universal_plane_init(dev, primary,
1754 0, &vmw_stdu_plane_funcs,
1755 vmw_primary_plane_formats,
1756 ARRAY_SIZE(vmw_primary_plane_formats),
1757 NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
1758 if (ret) {
1759 DRM_ERROR("Failed to initialize primary plane");
1760 goto err_free;
1761 }
1762
1763 drm_plane_helper_add(primary, &vmw_stdu_primary_plane_helper_funcs);
1764 drm_plane_enable_fb_damage_clips(primary);
1765
1766
1767 ret = drm_universal_plane_init(dev, &cursor->base,
1768 0, &vmw_stdu_cursor_funcs,
1769 vmw_cursor_plane_formats,
1770 ARRAY_SIZE(vmw_cursor_plane_formats),
1771 NULL, DRM_PLANE_TYPE_CURSOR, NULL);
1772 if (ret) {
1773 DRM_ERROR("Failed to initialize cursor plane");
1774 drm_plane_cleanup(&stdu->base.primary);
1775 goto err_free;
1776 }
1777
1778 drm_plane_helper_add(&cursor->base, &vmw_stdu_cursor_plane_helper_funcs);
1779
1780 ret = drm_connector_init(dev, connector, &vmw_stdu_connector_funcs,
1781 DRM_MODE_CONNECTOR_VIRTUAL);
1782 if (ret) {
1783 DRM_ERROR("Failed to initialize connector\n");
1784 goto err_free;
1785 }
1786
1787 drm_connector_helper_add(connector, &vmw_stdu_connector_helper_funcs);
1788 connector->status = vmw_du_connector_detect(connector, false);
1789
1790 ret = drm_encoder_init(dev, encoder, &vmw_stdu_encoder_funcs,
1791 DRM_MODE_ENCODER_VIRTUAL, NULL);
1792 if (ret) {
1793 DRM_ERROR("Failed to initialize encoder\n");
1794 goto err_free_connector;
1795 }
1796
1797 (void) drm_connector_attach_encoder(connector, encoder);
1798 encoder->possible_crtcs = (1 << unit);
1799 encoder->possible_clones = 0;
1800
1801 ret = drm_connector_register(connector);
1802 if (ret) {
1803 DRM_ERROR("Failed to register connector\n");
1804 goto err_free_encoder;
1805 }
1806
1807 ret = drm_crtc_init_with_planes(dev, crtc, primary,
1808 &cursor->base,
1809 &vmw_stdu_crtc_funcs, NULL);
1810 if (ret) {
1811 DRM_ERROR("Failed to initialize CRTC\n");
1812 goto err_free_unregister;
1813 }
1814
1815 drm_crtc_helper_add(crtc, &vmw_stdu_crtc_helper_funcs);
1816
1817 drm_mode_crtc_set_gamma_size(crtc, 256);
1818
1819 drm_object_attach_property(&connector->base,
1820 dev_priv->hotplug_mode_update_property, 1);
1821 drm_object_attach_property(&connector->base,
1822 dev->mode_config.suggested_x_property, 0);
1823 drm_object_attach_property(&connector->base,
1824 dev->mode_config.suggested_y_property, 0);
1825 return 0;
1826
1827 err_free_unregister:
1828 drm_connector_unregister(connector);
1829 err_free_encoder:
1830 drm_encoder_cleanup(encoder);
1831 err_free_connector:
1832 drm_connector_cleanup(connector);
1833 err_free:
1834 kfree(stdu);
1835 return ret;
1836 }
1837
1838
1839
1840
1841
1842
1843
1844
1845
1846
1847 static void vmw_stdu_destroy(struct vmw_screen_target_display_unit *stdu)
1848 {
1849 vmw_du_cleanup(&stdu->base);
1850 kfree(stdu);
1851 }
1852
1853
1854
1855
1856
1857
1858
1859
1860
1861
1862
1863
1864
1865
1866
1867
1868
1869
1870
1871
1872
1873
1874 int vmw_kms_stdu_init_display(struct vmw_private *dev_priv)
1875 {
1876 struct drm_device *dev = &dev_priv->drm;
1877 int i, ret;
1878
1879
1880
1881 if (!dev_priv->has_mob)
1882 return -ENOSYS;
1883
1884 if (!(dev_priv->capabilities & SVGA_CAP_GBOBJECTS))
1885 return -ENOSYS;
1886
1887 ret = drm_vblank_init(dev, VMWGFX_NUM_DISPLAY_UNITS);
1888 if (unlikely(ret != 0))
1889 return ret;
1890
1891 dev_priv->active_display_unit = vmw_du_screen_target;
1892
1893 for (i = 0; i < VMWGFX_NUM_DISPLAY_UNITS; ++i) {
1894 ret = vmw_stdu_init(dev_priv, i);
1895
1896 if (unlikely(ret != 0)) {
1897 drm_err(&dev_priv->drm,
1898 "Failed to initialize STDU %d", i);
1899 return ret;
1900 }
1901 }
1902
1903 drm_mode_config_reset(dev);
1904
1905 return 0;
1906 }