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0028 #include <drm/drm_atomic.h>
0029 #include <drm/drm_atomic_helper.h>
0030 #include <drm/drm_damage_helper.h>
0031 #include <drm/drm_fourcc.h>
0032 #include <drm/drm_plane_helper.h>
0033 #include <drm/drm_vblank.h>
0034
0035 #include "vmwgfx_kms.h"
0036
0037 #define vmw_crtc_to_sou(x) \
0038 container_of(x, struct vmw_screen_object_unit, base.crtc)
0039 #define vmw_encoder_to_sou(x) \
0040 container_of(x, struct vmw_screen_object_unit, base.encoder)
0041 #define vmw_connector_to_sou(x) \
0042 container_of(x, struct vmw_screen_object_unit, base.connector)
0043
0044
0045
0046
0047
0048
0049
0050
0051
0052
0053
0054
0055
0056 struct vmw_kms_sou_surface_dirty {
0057 struct vmw_kms_dirty base;
0058 s32 left, right, top, bottom;
0059 s32 dst_x, dst_y;
0060 u32 sid;
0061 };
0062
0063
0064
0065
0066
0067 struct vmw_kms_sou_readback_blit {
0068 uint32 header;
0069 SVGAFifoCmdBlitScreenToGMRFB body;
0070 };
0071
0072 struct vmw_kms_sou_bo_blit {
0073 uint32 header;
0074 SVGAFifoCmdBlitGMRFBToScreen body;
0075 };
0076
0077 struct vmw_kms_sou_dirty_cmd {
0078 SVGA3dCmdHeader header;
0079 SVGA3dCmdBlitSurfaceToScreen body;
0080 };
0081
0082 struct vmw_kms_sou_define_gmrfb {
0083 uint32_t header;
0084 SVGAFifoCmdDefineGMRFB body;
0085 };
0086
0087
0088
0089
0090 struct vmw_screen_object_unit {
0091 struct vmw_display_unit base;
0092
0093 unsigned long buffer_size;
0094 struct vmw_buffer_object *buffer;
0095
0096 bool defined;
0097 };
0098
0099 static void vmw_sou_destroy(struct vmw_screen_object_unit *sou)
0100 {
0101 vmw_du_cleanup(&sou->base);
0102 kfree(sou);
0103 }
0104
0105
0106
0107
0108
0109
0110 static void vmw_sou_crtc_destroy(struct drm_crtc *crtc)
0111 {
0112 vmw_sou_destroy(vmw_crtc_to_sou(crtc));
0113 }
0114
0115
0116
0117
0118 static int vmw_sou_fifo_create(struct vmw_private *dev_priv,
0119 struct vmw_screen_object_unit *sou,
0120 int x, int y,
0121 struct drm_display_mode *mode)
0122 {
0123 size_t fifo_size;
0124
0125 struct {
0126 struct {
0127 uint32_t cmdType;
0128 } header;
0129 SVGAScreenObject obj;
0130 } *cmd;
0131
0132 BUG_ON(!sou->buffer);
0133
0134 fifo_size = sizeof(*cmd);
0135 cmd = VMW_CMD_RESERVE(dev_priv, fifo_size);
0136 if (unlikely(cmd == NULL))
0137 return -ENOMEM;
0138
0139 memset(cmd, 0, fifo_size);
0140 cmd->header.cmdType = SVGA_CMD_DEFINE_SCREEN;
0141 cmd->obj.structSize = sizeof(SVGAScreenObject);
0142 cmd->obj.id = sou->base.unit;
0143 cmd->obj.flags = SVGA_SCREEN_HAS_ROOT |
0144 (sou->base.unit == 0 ? SVGA_SCREEN_IS_PRIMARY : 0);
0145 cmd->obj.size.width = mode->hdisplay;
0146 cmd->obj.size.height = mode->vdisplay;
0147 cmd->obj.root.x = x;
0148 cmd->obj.root.y = y;
0149 sou->base.set_gui_x = cmd->obj.root.x;
0150 sou->base.set_gui_y = cmd->obj.root.y;
0151
0152
0153 vmw_bo_get_guest_ptr(&sou->buffer->base, &cmd->obj.backingStore.ptr);
0154 cmd->obj.backingStore.pitch = mode->hdisplay * 4;
0155
0156 vmw_cmd_commit(dev_priv, fifo_size);
0157
0158 sou->defined = true;
0159
0160 return 0;
0161 }
0162
0163
0164
0165
0166 static int vmw_sou_fifo_destroy(struct vmw_private *dev_priv,
0167 struct vmw_screen_object_unit *sou)
0168 {
0169 size_t fifo_size;
0170 int ret;
0171
0172 struct {
0173 struct {
0174 uint32_t cmdType;
0175 } header;
0176 SVGAFifoCmdDestroyScreen body;
0177 } *cmd;
0178
0179
0180 if (unlikely(!sou->defined))
0181 return 0;
0182
0183 fifo_size = sizeof(*cmd);
0184 cmd = VMW_CMD_RESERVE(dev_priv, fifo_size);
0185 if (unlikely(cmd == NULL))
0186 return -ENOMEM;
0187
0188 memset(cmd, 0, fifo_size);
0189 cmd->header.cmdType = SVGA_CMD_DESTROY_SCREEN;
0190 cmd->body.screenId = sou->base.unit;
0191
0192 vmw_cmd_commit(dev_priv, fifo_size);
0193
0194
0195 ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ);
0196 if (unlikely(ret != 0))
0197 DRM_ERROR("Failed to sync with HW");
0198 else
0199 sou->defined = false;
0200
0201 return ret;
0202 }
0203
0204
0205
0206
0207
0208
0209
0210
0211
0212 static void vmw_sou_crtc_mode_set_nofb(struct drm_crtc *crtc)
0213 {
0214 struct vmw_private *dev_priv;
0215 struct vmw_screen_object_unit *sou;
0216 struct vmw_framebuffer *vfb;
0217 struct drm_framebuffer *fb;
0218 struct drm_plane_state *ps;
0219 struct vmw_plane_state *vps;
0220 int ret;
0221
0222 sou = vmw_crtc_to_sou(crtc);
0223 dev_priv = vmw_priv(crtc->dev);
0224 ps = crtc->primary->state;
0225 fb = ps->fb;
0226 vps = vmw_plane_state_to_vps(ps);
0227
0228 vfb = (fb) ? vmw_framebuffer_to_vfb(fb) : NULL;
0229
0230 if (sou->defined) {
0231 ret = vmw_sou_fifo_destroy(dev_priv, sou);
0232 if (ret) {
0233 DRM_ERROR("Failed to destroy Screen Object\n");
0234 return;
0235 }
0236 }
0237
0238 if (vfb) {
0239 struct drm_connector_state *conn_state;
0240 struct vmw_connector_state *vmw_conn_state;
0241 int x, y;
0242
0243 sou->buffer = vps->bo;
0244 sou->buffer_size = vps->bo_size;
0245
0246 conn_state = sou->base.connector.state;
0247 vmw_conn_state = vmw_connector_state_to_vcs(conn_state);
0248
0249 x = vmw_conn_state->gui_x;
0250 y = vmw_conn_state->gui_y;
0251
0252 ret = vmw_sou_fifo_create(dev_priv, sou, x, y, &crtc->mode);
0253 if (ret)
0254 DRM_ERROR("Failed to define Screen Object %dx%d\n",
0255 crtc->x, crtc->y);
0256
0257 } else {
0258 sou->buffer = NULL;
0259 sou->buffer_size = 0;
0260 }
0261 }
0262
0263
0264
0265
0266
0267
0268
0269
0270 static void vmw_sou_crtc_helper_prepare(struct drm_crtc *crtc)
0271 {
0272 }
0273
0274
0275
0276
0277
0278
0279
0280
0281
0282 static void vmw_sou_crtc_atomic_enable(struct drm_crtc *crtc,
0283 struct drm_atomic_state *state)
0284 {
0285 }
0286
0287
0288
0289
0290
0291
0292
0293 static void vmw_sou_crtc_atomic_disable(struct drm_crtc *crtc,
0294 struct drm_atomic_state *state)
0295 {
0296 struct vmw_private *dev_priv;
0297 struct vmw_screen_object_unit *sou;
0298 int ret;
0299
0300
0301 if (!crtc) {
0302 DRM_ERROR("CRTC is NULL\n");
0303 return;
0304 }
0305
0306 sou = vmw_crtc_to_sou(crtc);
0307 dev_priv = vmw_priv(crtc->dev);
0308
0309 if (sou->defined) {
0310 ret = vmw_sou_fifo_destroy(dev_priv, sou);
0311 if (ret)
0312 DRM_ERROR("Failed to destroy Screen Object\n");
0313 }
0314 }
0315
0316 static const struct drm_crtc_funcs vmw_screen_object_crtc_funcs = {
0317 .gamma_set = vmw_du_crtc_gamma_set,
0318 .destroy = vmw_sou_crtc_destroy,
0319 .reset = vmw_du_crtc_reset,
0320 .atomic_duplicate_state = vmw_du_crtc_duplicate_state,
0321 .atomic_destroy_state = vmw_du_crtc_destroy_state,
0322 .set_config = drm_atomic_helper_set_config,
0323 .page_flip = drm_atomic_helper_page_flip,
0324 .get_vblank_counter = vmw_get_vblank_counter,
0325 .enable_vblank = vmw_enable_vblank,
0326 .disable_vblank = vmw_disable_vblank,
0327 };
0328
0329
0330
0331
0332
0333 static void vmw_sou_encoder_destroy(struct drm_encoder *encoder)
0334 {
0335 vmw_sou_destroy(vmw_encoder_to_sou(encoder));
0336 }
0337
0338 static const struct drm_encoder_funcs vmw_screen_object_encoder_funcs = {
0339 .destroy = vmw_sou_encoder_destroy,
0340 };
0341
0342
0343
0344
0345
0346 static void vmw_sou_connector_destroy(struct drm_connector *connector)
0347 {
0348 vmw_sou_destroy(vmw_connector_to_sou(connector));
0349 }
0350
0351 static const struct drm_connector_funcs vmw_sou_connector_funcs = {
0352 .dpms = vmw_du_connector_dpms,
0353 .detect = vmw_du_connector_detect,
0354 .fill_modes = vmw_du_connector_fill_modes,
0355 .destroy = vmw_sou_connector_destroy,
0356 .reset = vmw_du_connector_reset,
0357 .atomic_duplicate_state = vmw_du_connector_duplicate_state,
0358 .atomic_destroy_state = vmw_du_connector_destroy_state,
0359 };
0360
0361
0362 static const struct
0363 drm_connector_helper_funcs vmw_sou_connector_helper_funcs = {
0364 };
0365
0366
0367
0368
0369
0370
0371
0372
0373
0374
0375
0376
0377
0378
0379
0380
0381
0382 static void
0383 vmw_sou_primary_plane_cleanup_fb(struct drm_plane *plane,
0384 struct drm_plane_state *old_state)
0385 {
0386 struct vmw_plane_state *vps = vmw_plane_state_to_vps(old_state);
0387 struct drm_crtc *crtc = plane->state->crtc ?
0388 plane->state->crtc : old_state->crtc;
0389
0390 if (vps->bo)
0391 vmw_bo_unpin(vmw_priv(crtc->dev), vps->bo, false);
0392 vmw_bo_unreference(&vps->bo);
0393 vps->bo_size = 0;
0394
0395 vmw_du_plane_cleanup_fb(plane, old_state);
0396 }
0397
0398
0399
0400
0401
0402
0403
0404
0405
0406
0407
0408
0409 static int
0410 vmw_sou_primary_plane_prepare_fb(struct drm_plane *plane,
0411 struct drm_plane_state *new_state)
0412 {
0413 struct drm_framebuffer *new_fb = new_state->fb;
0414 struct drm_crtc *crtc = plane->state->crtc ?: new_state->crtc;
0415 struct vmw_plane_state *vps = vmw_plane_state_to_vps(new_state);
0416 struct vmw_private *dev_priv;
0417 size_t size;
0418 int ret;
0419
0420
0421 if (!new_fb) {
0422 vmw_bo_unreference(&vps->bo);
0423 vps->bo_size = 0;
0424
0425 return 0;
0426 }
0427
0428 size = new_state->crtc_w * new_state->crtc_h * 4;
0429 dev_priv = vmw_priv(crtc->dev);
0430
0431 if (vps->bo) {
0432 if (vps->bo_size == size) {
0433
0434
0435
0436
0437 return vmw_bo_pin_in_vram(dev_priv, vps->bo,
0438 true);
0439 }
0440
0441 vmw_bo_unreference(&vps->bo);
0442 vps->bo_size = 0;
0443 }
0444
0445 vmw_svga_enable(dev_priv);
0446
0447
0448
0449
0450 vmw_overlay_pause_all(dev_priv);
0451 ret = vmw_bo_create(dev_priv, size,
0452 &vmw_vram_placement,
0453 false, true, &vmw_bo_bo_free, &vps->bo);
0454 vmw_overlay_resume_all(dev_priv);
0455 if (ret) {
0456 vps->bo = NULL;
0457 return ret;
0458 }
0459
0460 vps->bo_size = size;
0461
0462
0463
0464
0465
0466 return vmw_bo_pin_in_vram(dev_priv, vps->bo, true);
0467 }
0468
0469 static uint32_t vmw_sou_bo_fifo_size(struct vmw_du_update_plane *update,
0470 uint32_t num_hits)
0471 {
0472 return sizeof(struct vmw_kms_sou_define_gmrfb) +
0473 sizeof(struct vmw_kms_sou_bo_blit) * num_hits;
0474 }
0475
0476 static uint32_t vmw_sou_bo_define_gmrfb(struct vmw_du_update_plane *update,
0477 void *cmd)
0478 {
0479 struct vmw_framebuffer_bo *vfbbo =
0480 container_of(update->vfb, typeof(*vfbbo), base);
0481 struct vmw_kms_sou_define_gmrfb *gmr = cmd;
0482 int depth = update->vfb->base.format->depth;
0483
0484
0485
0486
0487
0488 if (depth == 32)
0489 depth = 24;
0490
0491 gmr->header = SVGA_CMD_DEFINE_GMRFB;
0492
0493 gmr->body.format.bitsPerPixel = update->vfb->base.format->cpp[0] * 8;
0494 gmr->body.format.colorDepth = depth;
0495 gmr->body.format.reserved = 0;
0496 gmr->body.bytesPerLine = update->vfb->base.pitches[0];
0497 vmw_bo_get_guest_ptr(&vfbbo->buffer->base, &gmr->body.ptr);
0498
0499 return sizeof(*gmr);
0500 }
0501
0502 static uint32_t vmw_sou_bo_populate_clip(struct vmw_du_update_plane *update,
0503 void *cmd, struct drm_rect *clip,
0504 uint32_t fb_x, uint32_t fb_y)
0505 {
0506 struct vmw_kms_sou_bo_blit *blit = cmd;
0507
0508 blit->header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
0509 blit->body.destScreenId = update->du->unit;
0510 blit->body.srcOrigin.x = fb_x;
0511 blit->body.srcOrigin.y = fb_y;
0512 blit->body.destRect.left = clip->x1;
0513 blit->body.destRect.top = clip->y1;
0514 blit->body.destRect.right = clip->x2;
0515 blit->body.destRect.bottom = clip->y2;
0516
0517 return sizeof(*blit);
0518 }
0519
0520 static uint32_t vmw_stud_bo_post_clip(struct vmw_du_update_plane *update,
0521 void *cmd, struct drm_rect *bb)
0522 {
0523 return 0;
0524 }
0525
0526
0527
0528
0529
0530
0531
0532
0533
0534
0535
0536
0537
0538 static int vmw_sou_plane_update_bo(struct vmw_private *dev_priv,
0539 struct drm_plane *plane,
0540 struct drm_plane_state *old_state,
0541 struct vmw_framebuffer *vfb,
0542 struct vmw_fence_obj **out_fence)
0543 {
0544 struct vmw_du_update_plane_buffer bo_update;
0545
0546 memset(&bo_update, 0, sizeof(struct vmw_du_update_plane_buffer));
0547 bo_update.base.plane = plane;
0548 bo_update.base.old_state = old_state;
0549 bo_update.base.dev_priv = dev_priv;
0550 bo_update.base.du = vmw_crtc_to_du(plane->state->crtc);
0551 bo_update.base.vfb = vfb;
0552 bo_update.base.out_fence = out_fence;
0553 bo_update.base.mutex = NULL;
0554 bo_update.base.cpu_blit = false;
0555 bo_update.base.intr = true;
0556
0557 bo_update.base.calc_fifo_size = vmw_sou_bo_fifo_size;
0558 bo_update.base.post_prepare = vmw_sou_bo_define_gmrfb;
0559 bo_update.base.clip = vmw_sou_bo_populate_clip;
0560 bo_update.base.post_clip = vmw_stud_bo_post_clip;
0561
0562 return vmw_du_helper_plane_update(&bo_update.base);
0563 }
0564
0565 static uint32_t vmw_sou_surface_fifo_size(struct vmw_du_update_plane *update,
0566 uint32_t num_hits)
0567 {
0568 return sizeof(struct vmw_kms_sou_dirty_cmd) + sizeof(SVGASignedRect) *
0569 num_hits;
0570 }
0571
0572 static uint32_t vmw_sou_surface_post_prepare(struct vmw_du_update_plane *update,
0573 void *cmd)
0574 {
0575 struct vmw_du_update_plane_surface *srf_update;
0576
0577 srf_update = container_of(update, typeof(*srf_update), base);
0578
0579
0580
0581
0582
0583
0584 srf_update->cmd_start = cmd;
0585
0586 return 0;
0587 }
0588
0589 static uint32_t vmw_sou_surface_pre_clip(struct vmw_du_update_plane *update,
0590 void *cmd, uint32_t num_hits)
0591 {
0592 struct vmw_kms_sou_dirty_cmd *blit = cmd;
0593 struct vmw_framebuffer_surface *vfbs;
0594
0595 vfbs = container_of(update->vfb, typeof(*vfbs), base);
0596
0597 blit->header.id = SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN;
0598 blit->header.size = sizeof(blit->body) + sizeof(SVGASignedRect) *
0599 num_hits;
0600
0601 blit->body.srcImage.sid = vfbs->surface->res.id;
0602 blit->body.destScreenId = update->du->unit;
0603
0604
0605 blit->body.srcRect.left = 0;
0606 blit->body.srcRect.top = 0;
0607 blit->body.srcRect.right = 0;
0608 blit->body.srcRect.bottom = 0;
0609
0610 blit->body.destRect.left = 0;
0611 blit->body.destRect.top = 0;
0612 blit->body.destRect.right = 0;
0613 blit->body.destRect.bottom = 0;
0614
0615 return sizeof(*blit);
0616 }
0617
0618 static uint32_t vmw_sou_surface_clip_rect(struct vmw_du_update_plane *update,
0619 void *cmd, struct drm_rect *clip,
0620 uint32_t src_x, uint32_t src_y)
0621 {
0622 SVGASignedRect *rect = cmd;
0623
0624
0625
0626
0627
0628 rect->left = clip->x1;
0629 rect->top = clip->y1;
0630 rect->right = clip->x2;
0631 rect->bottom = clip->y2;
0632
0633 return sizeof(*rect);
0634 }
0635
0636 static uint32_t vmw_sou_surface_post_clip(struct vmw_du_update_plane *update,
0637 void *cmd, struct drm_rect *bb)
0638 {
0639 struct vmw_du_update_plane_surface *srf_update;
0640 struct drm_plane_state *state = update->plane->state;
0641 struct drm_rect src_bb;
0642 struct vmw_kms_sou_dirty_cmd *blit;
0643 SVGASignedRect *rect;
0644 uint32_t num_hits;
0645 int translate_src_x;
0646 int translate_src_y;
0647 int i;
0648
0649 srf_update = container_of(update, typeof(*srf_update), base);
0650
0651 blit = srf_update->cmd_start;
0652 rect = (SVGASignedRect *)&blit[1];
0653
0654 num_hits = (blit->header.size - sizeof(blit->body))/
0655 sizeof(SVGASignedRect);
0656
0657 src_bb = *bb;
0658
0659
0660 translate_src_x = (state->src_x >> 16) - state->crtc_x;
0661 translate_src_y = (state->src_y >> 16) - state->crtc_y;
0662
0663 drm_rect_translate(&src_bb, translate_src_x, translate_src_y);
0664
0665 blit->body.srcRect.left = src_bb.x1;
0666 blit->body.srcRect.top = src_bb.y1;
0667 blit->body.srcRect.right = src_bb.x2;
0668 blit->body.srcRect.bottom = src_bb.y2;
0669
0670 blit->body.destRect.left = bb->x1;
0671 blit->body.destRect.top = bb->y1;
0672 blit->body.destRect.right = bb->x2;
0673 blit->body.destRect.bottom = bb->y2;
0674
0675
0676 for (i = 0; i < num_hits; i++) {
0677 rect->left -= bb->x1;
0678 rect->top -= bb->y1;
0679 rect->right -= bb->x1;
0680 rect->bottom -= bb->y1;
0681 rect++;
0682 }
0683
0684 return 0;
0685 }
0686
0687
0688
0689
0690
0691
0692
0693
0694
0695
0696
0697
0698
0699 static int vmw_sou_plane_update_surface(struct vmw_private *dev_priv,
0700 struct drm_plane *plane,
0701 struct drm_plane_state *old_state,
0702 struct vmw_framebuffer *vfb,
0703 struct vmw_fence_obj **out_fence)
0704 {
0705 struct vmw_du_update_plane_surface srf_update;
0706
0707 memset(&srf_update, 0, sizeof(struct vmw_du_update_plane_surface));
0708 srf_update.base.plane = plane;
0709 srf_update.base.old_state = old_state;
0710 srf_update.base.dev_priv = dev_priv;
0711 srf_update.base.du = vmw_crtc_to_du(plane->state->crtc);
0712 srf_update.base.vfb = vfb;
0713 srf_update.base.out_fence = out_fence;
0714 srf_update.base.mutex = &dev_priv->cmdbuf_mutex;
0715 srf_update.base.cpu_blit = false;
0716 srf_update.base.intr = true;
0717
0718 srf_update.base.calc_fifo_size = vmw_sou_surface_fifo_size;
0719 srf_update.base.post_prepare = vmw_sou_surface_post_prepare;
0720 srf_update.base.pre_clip = vmw_sou_surface_pre_clip;
0721 srf_update.base.clip = vmw_sou_surface_clip_rect;
0722 srf_update.base.post_clip = vmw_sou_surface_post_clip;
0723
0724 return vmw_du_helper_plane_update(&srf_update.base);
0725 }
0726
0727 static void
0728 vmw_sou_primary_plane_atomic_update(struct drm_plane *plane,
0729 struct drm_atomic_state *state)
0730 {
0731 struct drm_plane_state *old_state = drm_atomic_get_old_plane_state(state, plane);
0732 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state, plane);
0733 struct drm_crtc *crtc = new_state->crtc;
0734 struct drm_pending_vblank_event *event = NULL;
0735 struct vmw_fence_obj *fence = NULL;
0736 int ret;
0737
0738
0739 if (crtc && new_state->fb) {
0740 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
0741 struct vmw_framebuffer *vfb =
0742 vmw_framebuffer_to_vfb(new_state->fb);
0743
0744 if (vfb->bo)
0745 ret = vmw_sou_plane_update_bo(dev_priv, plane,
0746 old_state, vfb, &fence);
0747 else
0748 ret = vmw_sou_plane_update_surface(dev_priv, plane,
0749 old_state, vfb,
0750 &fence);
0751 if (ret != 0)
0752 DRM_ERROR("Failed to update screen.\n");
0753 } else {
0754
0755 return;
0756 }
0757
0758
0759 event = crtc->state->event;
0760 if (event && fence) {
0761 struct drm_file *file_priv = event->base.file_priv;
0762
0763 ret = vmw_event_fence_action_queue(file_priv,
0764 fence,
0765 &event->base,
0766 &event->event.vbl.tv_sec,
0767 &event->event.vbl.tv_usec,
0768 true);
0769
0770 if (unlikely(ret != 0))
0771 DRM_ERROR("Failed to queue event on fence.\n");
0772 else
0773 crtc->state->event = NULL;
0774 }
0775
0776 if (fence)
0777 vmw_fence_obj_unreference(&fence);
0778 }
0779
0780
0781 static const struct drm_plane_funcs vmw_sou_plane_funcs = {
0782 .update_plane = drm_atomic_helper_update_plane,
0783 .disable_plane = drm_atomic_helper_disable_plane,
0784 .destroy = vmw_du_primary_plane_destroy,
0785 .reset = vmw_du_plane_reset,
0786 .atomic_duplicate_state = vmw_du_plane_duplicate_state,
0787 .atomic_destroy_state = vmw_du_plane_destroy_state,
0788 };
0789
0790 static const struct drm_plane_funcs vmw_sou_cursor_funcs = {
0791 .update_plane = drm_atomic_helper_update_plane,
0792 .disable_plane = drm_atomic_helper_disable_plane,
0793 .destroy = vmw_du_cursor_plane_destroy,
0794 .reset = vmw_du_plane_reset,
0795 .atomic_duplicate_state = vmw_du_plane_duplicate_state,
0796 .atomic_destroy_state = vmw_du_plane_destroy_state,
0797 };
0798
0799
0800
0801
0802 static const struct
0803 drm_plane_helper_funcs vmw_sou_cursor_plane_helper_funcs = {
0804 .atomic_check = vmw_du_cursor_plane_atomic_check,
0805 .atomic_update = vmw_du_cursor_plane_atomic_update,
0806 .prepare_fb = vmw_du_cursor_plane_prepare_fb,
0807 .cleanup_fb = vmw_du_cursor_plane_cleanup_fb,
0808 };
0809
0810 static const struct
0811 drm_plane_helper_funcs vmw_sou_primary_plane_helper_funcs = {
0812 .atomic_check = vmw_du_primary_plane_atomic_check,
0813 .atomic_update = vmw_sou_primary_plane_atomic_update,
0814 .prepare_fb = vmw_sou_primary_plane_prepare_fb,
0815 .cleanup_fb = vmw_sou_primary_plane_cleanup_fb,
0816 };
0817
0818 static const struct drm_crtc_helper_funcs vmw_sou_crtc_helper_funcs = {
0819 .prepare = vmw_sou_crtc_helper_prepare,
0820 .mode_set_nofb = vmw_sou_crtc_mode_set_nofb,
0821 .atomic_check = vmw_du_crtc_atomic_check,
0822 .atomic_begin = vmw_du_crtc_atomic_begin,
0823 .atomic_flush = vmw_du_crtc_atomic_flush,
0824 .atomic_enable = vmw_sou_crtc_atomic_enable,
0825 .atomic_disable = vmw_sou_crtc_atomic_disable,
0826 };
0827
0828
0829 static int vmw_sou_init(struct vmw_private *dev_priv, unsigned unit)
0830 {
0831 struct vmw_screen_object_unit *sou;
0832 struct drm_device *dev = &dev_priv->drm;
0833 struct drm_connector *connector;
0834 struct drm_encoder *encoder;
0835 struct drm_plane *primary;
0836 struct vmw_cursor_plane *cursor;
0837 struct drm_crtc *crtc;
0838 int ret;
0839
0840 sou = kzalloc(sizeof(*sou), GFP_KERNEL);
0841 if (!sou)
0842 return -ENOMEM;
0843
0844 sou->base.unit = unit;
0845 crtc = &sou->base.crtc;
0846 encoder = &sou->base.encoder;
0847 connector = &sou->base.connector;
0848 primary = &sou->base.primary;
0849 cursor = &sou->base.cursor;
0850
0851 sou->base.pref_active = (unit == 0);
0852 sou->base.pref_width = dev_priv->initial_width;
0853 sou->base.pref_height = dev_priv->initial_height;
0854 sou->base.pref_mode = NULL;
0855
0856
0857
0858
0859
0860 sou->base.is_implicit = false;
0861
0862
0863 ret = drm_universal_plane_init(dev, primary,
0864 0, &vmw_sou_plane_funcs,
0865 vmw_primary_plane_formats,
0866 ARRAY_SIZE(vmw_primary_plane_formats),
0867 NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
0868 if (ret) {
0869 DRM_ERROR("Failed to initialize primary plane");
0870 goto err_free;
0871 }
0872
0873 drm_plane_helper_add(primary, &vmw_sou_primary_plane_helper_funcs);
0874 drm_plane_enable_fb_damage_clips(primary);
0875
0876
0877 ret = drm_universal_plane_init(dev, &cursor->base,
0878 0, &vmw_sou_cursor_funcs,
0879 vmw_cursor_plane_formats,
0880 ARRAY_SIZE(vmw_cursor_plane_formats),
0881 NULL, DRM_PLANE_TYPE_CURSOR, NULL);
0882 if (ret) {
0883 DRM_ERROR("Failed to initialize cursor plane");
0884 drm_plane_cleanup(&sou->base.primary);
0885 goto err_free;
0886 }
0887
0888 drm_plane_helper_add(&cursor->base, &vmw_sou_cursor_plane_helper_funcs);
0889
0890 ret = drm_connector_init(dev, connector, &vmw_sou_connector_funcs,
0891 DRM_MODE_CONNECTOR_VIRTUAL);
0892 if (ret) {
0893 DRM_ERROR("Failed to initialize connector\n");
0894 goto err_free;
0895 }
0896
0897 drm_connector_helper_add(connector, &vmw_sou_connector_helper_funcs);
0898 connector->status = vmw_du_connector_detect(connector, true);
0899
0900 ret = drm_encoder_init(dev, encoder, &vmw_screen_object_encoder_funcs,
0901 DRM_MODE_ENCODER_VIRTUAL, NULL);
0902 if (ret) {
0903 DRM_ERROR("Failed to initialize encoder\n");
0904 goto err_free_connector;
0905 }
0906
0907 (void) drm_connector_attach_encoder(connector, encoder);
0908 encoder->possible_crtcs = (1 << unit);
0909 encoder->possible_clones = 0;
0910
0911 ret = drm_connector_register(connector);
0912 if (ret) {
0913 DRM_ERROR("Failed to register connector\n");
0914 goto err_free_encoder;
0915 }
0916
0917 ret = drm_crtc_init_with_planes(dev, crtc, primary,
0918 &cursor->base,
0919 &vmw_screen_object_crtc_funcs, NULL);
0920 if (ret) {
0921 DRM_ERROR("Failed to initialize CRTC\n");
0922 goto err_free_unregister;
0923 }
0924
0925 drm_crtc_helper_add(crtc, &vmw_sou_crtc_helper_funcs);
0926
0927 drm_mode_crtc_set_gamma_size(crtc, 256);
0928
0929 drm_object_attach_property(&connector->base,
0930 dev_priv->hotplug_mode_update_property, 1);
0931 drm_object_attach_property(&connector->base,
0932 dev->mode_config.suggested_x_property, 0);
0933 drm_object_attach_property(&connector->base,
0934 dev->mode_config.suggested_y_property, 0);
0935 return 0;
0936
0937 err_free_unregister:
0938 drm_connector_unregister(connector);
0939 err_free_encoder:
0940 drm_encoder_cleanup(encoder);
0941 err_free_connector:
0942 drm_connector_cleanup(connector);
0943 err_free:
0944 kfree(sou);
0945 return ret;
0946 }
0947
0948 int vmw_kms_sou_init_display(struct vmw_private *dev_priv)
0949 {
0950 struct drm_device *dev = &dev_priv->drm;
0951 int i, ret;
0952
0953 if (!(dev_priv->capabilities & SVGA_CAP_SCREEN_OBJECT_2)) {
0954 return -ENOSYS;
0955 }
0956
0957 ret = -ENOMEM;
0958
0959 ret = drm_vblank_init(dev, VMWGFX_NUM_DISPLAY_UNITS);
0960 if (unlikely(ret != 0))
0961 return ret;
0962
0963 for (i = 0; i < VMWGFX_NUM_DISPLAY_UNITS; ++i)
0964 vmw_sou_init(dev_priv, i);
0965
0966 dev_priv->active_display_unit = vmw_du_screen_object;
0967
0968 drm_mode_config_reset(dev);
0969
0970 return 0;
0971 }
0972
0973 static int do_bo_define_gmrfb(struct vmw_private *dev_priv,
0974 struct vmw_framebuffer *framebuffer)
0975 {
0976 struct vmw_buffer_object *buf =
0977 container_of(framebuffer, struct vmw_framebuffer_bo,
0978 base)->buffer;
0979 int depth = framebuffer->base.format->depth;
0980 struct {
0981 uint32_t header;
0982 SVGAFifoCmdDefineGMRFB body;
0983 } *cmd;
0984
0985
0986
0987
0988
0989 if (depth == 32)
0990 depth = 24;
0991
0992 cmd = VMW_CMD_RESERVE(dev_priv, sizeof(*cmd));
0993 if (!cmd)
0994 return -ENOMEM;
0995
0996 cmd->header = SVGA_CMD_DEFINE_GMRFB;
0997 cmd->body.format.bitsPerPixel = framebuffer->base.format->cpp[0] * 8;
0998 cmd->body.format.colorDepth = depth;
0999 cmd->body.format.reserved = 0;
1000 cmd->body.bytesPerLine = framebuffer->base.pitches[0];
1001
1002 vmw_bo_get_guest_ptr(&buf->base, &cmd->body.ptr);
1003 vmw_cmd_commit(dev_priv, sizeof(*cmd));
1004
1005 return 0;
1006 }
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017 static void vmw_sou_surface_fifo_commit(struct vmw_kms_dirty *dirty)
1018 {
1019 struct vmw_kms_sou_surface_dirty *sdirty =
1020 container_of(dirty, typeof(*sdirty), base);
1021 struct vmw_kms_sou_dirty_cmd *cmd = dirty->cmd;
1022 s32 trans_x = dirty->unit->crtc.x - sdirty->dst_x;
1023 s32 trans_y = dirty->unit->crtc.y - sdirty->dst_y;
1024 size_t region_size = dirty->num_hits * sizeof(SVGASignedRect);
1025 SVGASignedRect *blit = (SVGASignedRect *) &cmd[1];
1026 int i;
1027
1028 if (!dirty->num_hits) {
1029 vmw_cmd_commit(dirty->dev_priv, 0);
1030 return;
1031 }
1032
1033 cmd->header.id = SVGA_3D_CMD_BLIT_SURFACE_TO_SCREEN;
1034 cmd->header.size = sizeof(cmd->body) + region_size;
1035
1036
1037
1038
1039
1040 cmd->body.destRect.left = sdirty->left;
1041 cmd->body.destRect.right = sdirty->right;
1042 cmd->body.destRect.top = sdirty->top;
1043 cmd->body.destRect.bottom = sdirty->bottom;
1044
1045 cmd->body.srcRect.left = sdirty->left + trans_x;
1046 cmd->body.srcRect.right = sdirty->right + trans_x;
1047 cmd->body.srcRect.top = sdirty->top + trans_y;
1048 cmd->body.srcRect.bottom = sdirty->bottom + trans_y;
1049
1050 cmd->body.srcImage.sid = sdirty->sid;
1051 cmd->body.destScreenId = dirty->unit->unit;
1052
1053
1054 for (i = 0; i < dirty->num_hits; ++i, ++blit) {
1055 blit->left -= sdirty->left;
1056 blit->right -= sdirty->left;
1057 blit->top -= sdirty->top;
1058 blit->bottom -= sdirty->top;
1059 }
1060
1061 vmw_cmd_commit(dirty->dev_priv, region_size + sizeof(*cmd));
1062
1063 sdirty->left = sdirty->top = S32_MAX;
1064 sdirty->right = sdirty->bottom = S32_MIN;
1065 }
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075 static void vmw_sou_surface_clip(struct vmw_kms_dirty *dirty)
1076 {
1077 struct vmw_kms_sou_surface_dirty *sdirty =
1078 container_of(dirty, typeof(*sdirty), base);
1079 struct vmw_kms_sou_dirty_cmd *cmd = dirty->cmd;
1080 SVGASignedRect *blit = (SVGASignedRect *) &cmd[1];
1081
1082
1083 blit += dirty->num_hits;
1084 blit->left = dirty->unit_x1;
1085 blit->top = dirty->unit_y1;
1086 blit->right = dirty->unit_x2;
1087 blit->bottom = dirty->unit_y2;
1088
1089
1090 sdirty->left = min_t(s32, sdirty->left, dirty->unit_x1);
1091 sdirty->top = min_t(s32, sdirty->top, dirty->unit_y1);
1092 sdirty->right = max_t(s32, sdirty->right, dirty->unit_x2);
1093 sdirty->bottom = max_t(s32, sdirty->bottom, dirty->unit_y2);
1094
1095 dirty->num_hits++;
1096 }
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120 int vmw_kms_sou_do_surface_dirty(struct vmw_private *dev_priv,
1121 struct vmw_framebuffer *framebuffer,
1122 struct drm_clip_rect *clips,
1123 struct drm_vmw_rect *vclips,
1124 struct vmw_resource *srf,
1125 s32 dest_x,
1126 s32 dest_y,
1127 unsigned num_clips, int inc,
1128 struct vmw_fence_obj **out_fence,
1129 struct drm_crtc *crtc)
1130 {
1131 struct vmw_framebuffer_surface *vfbs =
1132 container_of(framebuffer, typeof(*vfbs), base);
1133 struct vmw_kms_sou_surface_dirty sdirty;
1134 DECLARE_VAL_CONTEXT(val_ctx, NULL, 0);
1135 int ret;
1136
1137 if (!srf)
1138 srf = &vfbs->surface->res;
1139
1140 ret = vmw_validation_add_resource(&val_ctx, srf, 0, VMW_RES_DIRTY_NONE,
1141 NULL, NULL);
1142 if (ret)
1143 return ret;
1144
1145 ret = vmw_validation_prepare(&val_ctx, &dev_priv->cmdbuf_mutex, true);
1146 if (ret)
1147 goto out_unref;
1148
1149 sdirty.base.fifo_commit = vmw_sou_surface_fifo_commit;
1150 sdirty.base.clip = vmw_sou_surface_clip;
1151 sdirty.base.dev_priv = dev_priv;
1152 sdirty.base.fifo_reserve_size = sizeof(struct vmw_kms_sou_dirty_cmd) +
1153 sizeof(SVGASignedRect) * num_clips;
1154 sdirty.base.crtc = crtc;
1155
1156 sdirty.sid = srf->id;
1157 sdirty.left = sdirty.top = S32_MAX;
1158 sdirty.right = sdirty.bottom = S32_MIN;
1159 sdirty.dst_x = dest_x;
1160 sdirty.dst_y = dest_y;
1161
1162 ret = vmw_kms_helper_dirty(dev_priv, framebuffer, clips, vclips,
1163 dest_x, dest_y, num_clips, inc,
1164 &sdirty.base);
1165 vmw_kms_helper_validation_finish(dev_priv, NULL, &val_ctx, out_fence,
1166 NULL);
1167
1168 return ret;
1169
1170 out_unref:
1171 vmw_validation_unref_lists(&val_ctx);
1172 return ret;
1173 }
1174
1175
1176
1177
1178
1179
1180
1181
1182 static void vmw_sou_bo_fifo_commit(struct vmw_kms_dirty *dirty)
1183 {
1184 if (!dirty->num_hits) {
1185 vmw_cmd_commit(dirty->dev_priv, 0);
1186 return;
1187 }
1188
1189 vmw_cmd_commit(dirty->dev_priv,
1190 sizeof(struct vmw_kms_sou_bo_blit) *
1191 dirty->num_hits);
1192 }
1193
1194
1195
1196
1197
1198
1199
1200
1201 static void vmw_sou_bo_clip(struct vmw_kms_dirty *dirty)
1202 {
1203 struct vmw_kms_sou_bo_blit *blit = dirty->cmd;
1204
1205 blit += dirty->num_hits;
1206 blit->header = SVGA_CMD_BLIT_GMRFB_TO_SCREEN;
1207 blit->body.destScreenId = dirty->unit->unit;
1208 blit->body.srcOrigin.x = dirty->fb_x;
1209 blit->body.srcOrigin.y = dirty->fb_y;
1210 blit->body.destRect.left = dirty->unit_x1;
1211 blit->body.destRect.top = dirty->unit_y1;
1212 blit->body.destRect.right = dirty->unit_x2;
1213 blit->body.destRect.bottom = dirty->unit_y2;
1214 dirty->num_hits++;
1215 }
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236 int vmw_kms_sou_do_bo_dirty(struct vmw_private *dev_priv,
1237 struct vmw_framebuffer *framebuffer,
1238 struct drm_clip_rect *clips,
1239 struct drm_vmw_rect *vclips,
1240 unsigned num_clips, int increment,
1241 bool interruptible,
1242 struct vmw_fence_obj **out_fence,
1243 struct drm_crtc *crtc)
1244 {
1245 struct vmw_buffer_object *buf =
1246 container_of(framebuffer, struct vmw_framebuffer_bo,
1247 base)->buffer;
1248 struct vmw_kms_dirty dirty;
1249 DECLARE_VAL_CONTEXT(val_ctx, NULL, 0);
1250 int ret;
1251
1252 ret = vmw_validation_add_bo(&val_ctx, buf, false, false);
1253 if (ret)
1254 return ret;
1255
1256 ret = vmw_validation_prepare(&val_ctx, NULL, interruptible);
1257 if (ret)
1258 goto out_unref;
1259
1260 ret = do_bo_define_gmrfb(dev_priv, framebuffer);
1261 if (unlikely(ret != 0))
1262 goto out_revert;
1263
1264 dirty.crtc = crtc;
1265 dirty.fifo_commit = vmw_sou_bo_fifo_commit;
1266 dirty.clip = vmw_sou_bo_clip;
1267 dirty.fifo_reserve_size = sizeof(struct vmw_kms_sou_bo_blit) *
1268 num_clips;
1269 ret = vmw_kms_helper_dirty(dev_priv, framebuffer, clips, vclips,
1270 0, 0, num_clips, increment, &dirty);
1271 vmw_kms_helper_validation_finish(dev_priv, NULL, &val_ctx, out_fence,
1272 NULL);
1273
1274 return ret;
1275
1276 out_revert:
1277 vmw_validation_revert(&val_ctx);
1278 out_unref:
1279 vmw_validation_unref_lists(&val_ctx);
1280
1281 return ret;
1282 }
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292 static void vmw_sou_readback_fifo_commit(struct vmw_kms_dirty *dirty)
1293 {
1294 if (!dirty->num_hits) {
1295 vmw_cmd_commit(dirty->dev_priv, 0);
1296 return;
1297 }
1298
1299 vmw_cmd_commit(dirty->dev_priv,
1300 sizeof(struct vmw_kms_sou_readback_blit) *
1301 dirty->num_hits);
1302 }
1303
1304
1305
1306
1307
1308
1309
1310
1311 static void vmw_sou_readback_clip(struct vmw_kms_dirty *dirty)
1312 {
1313 struct vmw_kms_sou_readback_blit *blit = dirty->cmd;
1314
1315 blit += dirty->num_hits;
1316 blit->header = SVGA_CMD_BLIT_SCREEN_TO_GMRFB;
1317 blit->body.srcScreenId = dirty->unit->unit;
1318 blit->body.destOrigin.x = dirty->fb_x;
1319 blit->body.destOrigin.y = dirty->fb_y;
1320 blit->body.srcRect.left = dirty->unit_x1;
1321 blit->body.srcRect.top = dirty->unit_y1;
1322 blit->body.srcRect.right = dirty->unit_x2;
1323 blit->body.srcRect.bottom = dirty->unit_y2;
1324 dirty->num_hits++;
1325 }
1326
1327
1328
1329
1330
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344 int vmw_kms_sou_readback(struct vmw_private *dev_priv,
1345 struct drm_file *file_priv,
1346 struct vmw_framebuffer *vfb,
1347 struct drm_vmw_fence_rep __user *user_fence_rep,
1348 struct drm_vmw_rect *vclips,
1349 uint32_t num_clips,
1350 struct drm_crtc *crtc)
1351 {
1352 struct vmw_buffer_object *buf =
1353 container_of(vfb, struct vmw_framebuffer_bo, base)->buffer;
1354 struct vmw_kms_dirty dirty;
1355 DECLARE_VAL_CONTEXT(val_ctx, NULL, 0);
1356 int ret;
1357
1358 ret = vmw_validation_add_bo(&val_ctx, buf, false, false);
1359 if (ret)
1360 return ret;
1361
1362 ret = vmw_validation_prepare(&val_ctx, NULL, true);
1363 if (ret)
1364 goto out_unref;
1365
1366 ret = do_bo_define_gmrfb(dev_priv, vfb);
1367 if (unlikely(ret != 0))
1368 goto out_revert;
1369
1370 dirty.crtc = crtc;
1371 dirty.fifo_commit = vmw_sou_readback_fifo_commit;
1372 dirty.clip = vmw_sou_readback_clip;
1373 dirty.fifo_reserve_size = sizeof(struct vmw_kms_sou_readback_blit) *
1374 num_clips;
1375 ret = vmw_kms_helper_dirty(dev_priv, vfb, NULL, vclips,
1376 0, 0, num_clips, 1, &dirty);
1377 vmw_kms_helper_validation_finish(dev_priv, file_priv, &val_ctx, NULL,
1378 user_fence_rep);
1379
1380 return ret;
1381
1382 out_revert:
1383 vmw_validation_revert(&val_ctx);
1384 out_unref:
1385 vmw_validation_unref_lists(&val_ctx);
1386
1387 return ret;
1388 }