drm/via/via_dmablit.h

0001 /* via_dmablit.h -- PCI DMA BitBlt support for the VIA Unichrome/Pro
0002  *
0003  * Copyright 2005 Thomas Hellstrom.
0004  * All Rights Reserved.
0005  *
0006  * Permission is hereby granted, free of charge, to any person obtaining a
0007  * copy of this software and associated documentation files (the "Software"),
0008  * to deal in the Software without restriction, including without limitation
0009  * the rights to use, copy, modify, merge, publish, distribute, sub license,
0010  * and/or sell copies of the Software, and to permit persons to whom the
0011  * Software is furnished to do so, subject to the following conditions:
0012  *
0013  * The above copyright notice and this permission notice (including the
0014  * next paragraph) shall be included in all copies or substantial portions
0015  * of the Software.
0016  *
0017  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0018  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0019  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
0020  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
0021  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
0022  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
0023  * USE OR OTHER DEALINGS IN THE SOFTWARE.
0024  *
0025  * Authors:
0026  *    Thomas Hellstrom.
0027  *    Register info from Digeo Inc.
0028  */
0029
0030 #ifndef _VIA_DMABLIT_H
0031 #define _VIA_DMABLIT_H
0032
0033 #include <linux/dma-mapping.h>
0034
0035 #define VIA_NUM_BLIT_ENGINES 2
0036 #define VIA_NUM_BLIT_SLOTS 8
0037
0038 struct _drm_via_descriptor;
0039
0040 typedef struct _drm_via_sg_info {
0041     struct page **pages;
0042     unsigned long num_pages;
0043     struct _drm_via_descriptor **desc_pages;
0044     int num_desc_pages;
0045     int num_desc;
0046     enum dma_data_direction direction;
0047     unsigned char *bounce_buffer;
0048     dma_addr_t chain_start;
0049     uint32_t free_on_sequence;
0050     unsigned int descriptors_per_page;
0051     int aborted;
0052     enum {
0053         dr_via_device_mapped,
0054         dr_via_desc_pages_alloc,
0055         dr_via_pages_locked,
0056         dr_via_pages_alloc,
0057         dr_via_sg_init
0058     } state;
0059 } drm_via_sg_info_t;
0060
0061 typedef struct _drm_via_blitq {
0062     struct drm_device *dev;
0063     uint32_t cur_blit_handle;
0064     uint32_t done_blit_handle;
0065     unsigned serviced;
0066     unsigned head;
0067     unsigned cur;
0068     unsigned num_free;
0069     unsigned num_outstanding;
0070     unsigned long end;
0071     int aborting;
0072     int is_active;
0073     drm_via_sg_info_t *blits[VIA_NUM_BLIT_SLOTS];
0074     spinlock_t blit_lock;
0075     wait_queue_head_t blit_queue[VIA_NUM_BLIT_SLOTS];
0076     wait_queue_head_t busy_queue;
0077     struct work_struct wq;
0078     struct timer_list poll_timer;
0079 } drm_via_blitq_t;
0080
0081
0082 /*
0083  *  PCI DMA Registers
0084  *  Channels 2 & 3 don't seem to be implemented in hardware.
0085  */
0086
0087 #define VIA_PCI_DMA_MAR0            0xE40   /* Memory Address Register of Channel 0 */
0088 #define VIA_PCI_DMA_DAR0            0xE44   /* Device Address Register of Channel 0 */
0089 #define VIA_PCI_DMA_BCR0            0xE48   /* Byte Count Register of Channel 0 */
0090 #define VIA_PCI_DMA_DPR0            0xE4C   /* Descriptor Pointer Register of Channel 0 */
0091
0092 #define VIA_PCI_DMA_MAR1            0xE50   /* Memory Address Register of Channel 1 */
0093 #define VIA_PCI_DMA_DAR1            0xE54   /* Device Address Register of Channel 1 */
0094 #define VIA_PCI_DMA_BCR1            0xE58   /* Byte Count Register of Channel 1 */
0095 #define VIA_PCI_DMA_DPR1            0xE5C   /* Descriptor Pointer Register of Channel 1 */
0096
0097 #define VIA_PCI_DMA_MAR2            0xE60   /* Memory Address Register of Channel 2 */
0098 #define VIA_PCI_DMA_DAR2            0xE64   /* Device Address Register of Channel 2 */
0099 #define VIA_PCI_DMA_BCR2            0xE68   /* Byte Count Register of Channel 2 */
0100 #define VIA_PCI_DMA_DPR2            0xE6C   /* Descriptor Pointer Register of Channel 2 */
0101
0102 #define VIA_PCI_DMA_MAR3            0xE70   /* Memory Address Register of Channel 3 */
0103 #define VIA_PCI_DMA_DAR3            0xE74   /* Device Address Register of Channel 3 */
0104 #define VIA_PCI_DMA_BCR3            0xE78   /* Byte Count Register of Channel 3 */
0105 #define VIA_PCI_DMA_DPR3            0xE7C   /* Descriptor Pointer Register of Channel 3 */
0106
0107 #define VIA_PCI_DMA_MR0             0xE80   /* Mode Register of Channel 0 */
0108 #define VIA_PCI_DMA_MR1             0xE84   /* Mode Register of Channel 1 */
0109 #define VIA_PCI_DMA_MR2             0xE88   /* Mode Register of Channel 2 */
0110 #define VIA_PCI_DMA_MR3             0xE8C   /* Mode Register of Channel 3 */
0111
0112 #define VIA_PCI_DMA_CSR0            0xE90   /* Command/Status Register of Channel 0 */
0113 #define VIA_PCI_DMA_CSR1            0xE94   /* Command/Status Register of Channel 1 */
0114 #define VIA_PCI_DMA_CSR2            0xE98   /* Command/Status Register of Channel 2 */
0115 #define VIA_PCI_DMA_CSR3            0xE9C   /* Command/Status Register of Channel 3 */
0116
0117 #define VIA_PCI_DMA_PTR             0xEA0   /* Priority Type Register */
0118
0119 /* Define for DMA engine */
0120 /* DPR */
0121 #define VIA_DMA_DPR_EC      (1<<1)  /* end of chain */
0122 #define VIA_DMA_DPR_DDIE    (1<<2)  /* descriptor done interrupt enable */
0123 #define VIA_DMA_DPR_DT      (1<<3)  /* direction of transfer (RO) */
0124
0125 /* MR */
0126 #define VIA_DMA_MR_CM       (1<<0)  /* chaining mode */
0127 #define VIA_DMA_MR_TDIE     (1<<1)  /* transfer done interrupt enable */
0128 #define VIA_DMA_MR_HENDMACMD        (1<<7) /* ? */
0129
0130 /* CSR */
0131 #define VIA_DMA_CSR_DE      (1<<0)  /* DMA enable */
0132 #define VIA_DMA_CSR_TS      (1<<1)  /* transfer start */
0133 #define VIA_DMA_CSR_TA      (1<<2)  /* transfer abort */
0134 #define VIA_DMA_CSR_TD      (1<<3)  /* transfer done */
0135 #define VIA_DMA_CSR_DD      (1<<4)  /* descriptor done */
0136 #define VIA_DMA_DPR_EC          (1<<1)  /* end of chain */
0137
0138
0139
0140 #endif