drm/vc4/vc4_qpu_defines.h

0001 /*
0002  * Copyright © 2014 Broadcom
0003  *
0004  * Permission is hereby granted, free of charge, to any person obtaining a
0005  * copy of this software and associated documentation files (the "Software"),
0006  * to deal in the Software without restriction, including without limitation
0007  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
0008  * and/or sell copies of the Software, and to permit persons to whom the
0009  * Software is furnished to do so, subject to the following conditions:
0010  *
0011  * The above copyright notice and this permission notice (including the next
0012  * paragraph) shall be included in all copies or substantial portions of the
0013  * Software.
0014  *
0015  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
0016  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
0017  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
0018  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
0019  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
0020  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
0021  * IN THE SOFTWARE.
0022  */
0023
0024 #ifndef VC4_QPU_DEFINES_H
0025 #define VC4_QPU_DEFINES_H
0026
0027 enum qpu_op_add {
0028     QPU_A_NOP,
0029     QPU_A_FADD,
0030     QPU_A_FSUB,
0031     QPU_A_FMIN,
0032     QPU_A_FMAX,
0033     QPU_A_FMINABS,
0034     QPU_A_FMAXABS,
0035     QPU_A_FTOI,
0036     QPU_A_ITOF,
0037     QPU_A_ADD = 12,
0038     QPU_A_SUB,
0039     QPU_A_SHR,
0040     QPU_A_ASR,
0041     QPU_A_ROR,
0042     QPU_A_SHL,
0043     QPU_A_MIN,
0044     QPU_A_MAX,
0045     QPU_A_AND,
0046     QPU_A_OR,
0047     QPU_A_XOR,
0048     QPU_A_NOT,
0049     QPU_A_CLZ,
0050     QPU_A_V8ADDS = 30,
0051     QPU_A_V8SUBS = 31,
0052 };
0053
0054 enum qpu_op_mul {
0055     QPU_M_NOP,
0056     QPU_M_FMUL,
0057     QPU_M_MUL24,
0058     QPU_M_V8MULD,
0059     QPU_M_V8MIN,
0060     QPU_M_V8MAX,
0061     QPU_M_V8ADDS,
0062     QPU_M_V8SUBS,
0063 };
0064
0065 enum qpu_raddr {
0066     QPU_R_FRAG_PAYLOAD_ZW = 15, /* W for A file, Z for B file */
0067     /* 0-31 are the plain regfile a or b fields */
0068     QPU_R_UNIF = 32,
0069     QPU_R_VARY = 35,
0070     QPU_R_ELEM_QPU = 38,
0071     QPU_R_NOP,
0072     QPU_R_XY_PIXEL_COORD = 41,
0073     QPU_R_MS_REV_FLAGS = 42,
0074     QPU_R_VPM = 48,
0075     QPU_R_VPM_LD_BUSY,
0076     QPU_R_VPM_LD_WAIT,
0077     QPU_R_MUTEX_ACQUIRE,
0078 };
0079
0080 enum qpu_waddr {
0081     /* 0-31 are the plain regfile a or b fields */
0082     QPU_W_ACC0 = 32, /* aka r0 */
0083     QPU_W_ACC1,
0084     QPU_W_ACC2,
0085     QPU_W_ACC3,
0086     QPU_W_TMU_NOSWAP,
0087     QPU_W_ACC5,
0088     QPU_W_HOST_INT,
0089     QPU_W_NOP,
0090     QPU_W_UNIFORMS_ADDRESS,
0091     QPU_W_QUAD_XY, /* X for regfile a, Y for regfile b */
0092     QPU_W_MS_FLAGS = 42,
0093     QPU_W_REV_FLAG = 42,
0094     QPU_W_TLB_STENCIL_SETUP = 43,
0095     QPU_W_TLB_Z,
0096     QPU_W_TLB_COLOR_MS,
0097     QPU_W_TLB_COLOR_ALL,
0098     QPU_W_TLB_ALPHA_MASK,
0099     QPU_W_VPM,
0100     QPU_W_VPMVCD_SETUP, /* LD for regfile a, ST for regfile b */
0101     QPU_W_VPM_ADDR, /* LD for regfile a, ST for regfile b */
0102     QPU_W_MUTEX_RELEASE,
0103     QPU_W_SFU_RECIP,
0104     QPU_W_SFU_RECIPSQRT,
0105     QPU_W_SFU_EXP,
0106     QPU_W_SFU_LOG,
0107     QPU_W_TMU0_S,
0108     QPU_W_TMU0_T,
0109     QPU_W_TMU0_R,
0110     QPU_W_TMU0_B,
0111     QPU_W_TMU1_S,
0112     QPU_W_TMU1_T,
0113     QPU_W_TMU1_R,
0114     QPU_W_TMU1_B,
0115 };
0116
0117 enum qpu_sig_bits {
0118     QPU_SIG_SW_BREAKPOINT,
0119     QPU_SIG_NONE,
0120     QPU_SIG_THREAD_SWITCH,
0121     QPU_SIG_PROG_END,
0122     QPU_SIG_WAIT_FOR_SCOREBOARD,
0123     QPU_SIG_SCOREBOARD_UNLOCK,
0124     QPU_SIG_LAST_THREAD_SWITCH,
0125     QPU_SIG_COVERAGE_LOAD,
0126     QPU_SIG_COLOR_LOAD,
0127     QPU_SIG_COLOR_LOAD_END,
0128     QPU_SIG_LOAD_TMU0,
0129     QPU_SIG_LOAD_TMU1,
0130     QPU_SIG_ALPHA_MASK_LOAD,
0131     QPU_SIG_SMALL_IMM,
0132     QPU_SIG_LOAD_IMM,
0133     QPU_SIG_BRANCH
0134 };
0135
0136 enum qpu_mux {
0137     /* hardware mux values */
0138     QPU_MUX_R0,
0139     QPU_MUX_R1,
0140     QPU_MUX_R2,
0141     QPU_MUX_R3,
0142     QPU_MUX_R4,
0143     QPU_MUX_R5,
0144     QPU_MUX_A,
0145     QPU_MUX_B,
0146
0147     /* non-hardware mux values */
0148     QPU_MUX_IMM,
0149 };
0150
0151 enum qpu_cond {
0152     QPU_COND_NEVER,
0153     QPU_COND_ALWAYS,
0154     QPU_COND_ZS,
0155     QPU_COND_ZC,
0156     QPU_COND_NS,
0157     QPU_COND_NC,
0158     QPU_COND_CS,
0159     QPU_COND_CC,
0160 };
0161
0162 enum qpu_pack_mul {
0163     QPU_PACK_MUL_NOP,
0164     /* replicated to each 8 bits of the 32-bit dst. */
0165     QPU_PACK_MUL_8888 = 3,
0166     QPU_PACK_MUL_8A,
0167     QPU_PACK_MUL_8B,
0168     QPU_PACK_MUL_8C,
0169     QPU_PACK_MUL_8D,
0170 };
0171
0172 enum qpu_pack_a {
0173     QPU_PACK_A_NOP,
0174     /* convert to 16 bit float if float input, or to int16. */
0175     QPU_PACK_A_16A,
0176     QPU_PACK_A_16B,
0177     /* replicated to each 8 bits of the 32-bit dst. */
0178     QPU_PACK_A_8888,
0179     /* Convert to 8-bit unsigned int. */
0180     QPU_PACK_A_8A,
0181     QPU_PACK_A_8B,
0182     QPU_PACK_A_8C,
0183     QPU_PACK_A_8D,
0184
0185     /* Saturating variants of the previous instructions. */
0186     QPU_PACK_A_32_SAT, /* int-only */
0187     QPU_PACK_A_16A_SAT, /* int or float */
0188     QPU_PACK_A_16B_SAT,
0189     QPU_PACK_A_8888_SAT,
0190     QPU_PACK_A_8A_SAT,
0191     QPU_PACK_A_8B_SAT,
0192     QPU_PACK_A_8C_SAT,
0193     QPU_PACK_A_8D_SAT,
0194 };
0195
0196 enum qpu_unpack_r4 {
0197     QPU_UNPACK_R4_NOP,
0198     QPU_UNPACK_R4_F16A_TO_F32,
0199     QPU_UNPACK_R4_F16B_TO_F32,
0200     QPU_UNPACK_R4_8D_REP,
0201     QPU_UNPACK_R4_8A,
0202     QPU_UNPACK_R4_8B,
0203     QPU_UNPACK_R4_8C,
0204     QPU_UNPACK_R4_8D,
0205 };
0206
0207 #define QPU_MASK(high, low) \
0208     ((((uint64_t)1 << ((high) - (low) + 1)) - 1) << (low))
0209
0210 #define QPU_GET_FIELD(word, field) \
0211     ((uint32_t)(((word)  & field ## _MASK) >> field ## _SHIFT))
0212
0213 #define QPU_SIG_SHIFT                   60
0214 #define QPU_SIG_MASK                    QPU_MASK(63, 60)
0215
0216 #define QPU_UNPACK_SHIFT                57
0217 #define QPU_UNPACK_MASK                 QPU_MASK(59, 57)
0218
0219 /**
0220  * If set, the pack field means PACK_MUL or R4 packing, instead of normal
0221  * regfile a packing.
0222  */
0223 #define QPU_PM                          ((uint64_t)1 << 56)
0224
0225 #define QPU_PACK_SHIFT                  52
0226 #define QPU_PACK_MASK                   QPU_MASK(55, 52)
0227
0228 #define QPU_COND_ADD_SHIFT              49
0229 #define QPU_COND_ADD_MASK               QPU_MASK(51, 49)
0230 #define QPU_COND_MUL_SHIFT              46
0231 #define QPU_COND_MUL_MASK               QPU_MASK(48, 46)
0232
0233 #define QPU_BRANCH_COND_SHIFT           52
0234 #define QPU_BRANCH_COND_MASK            QPU_MASK(55, 52)
0235
0236 #define QPU_BRANCH_REL                  ((uint64_t)1 << 51)
0237 #define QPU_BRANCH_REG                  ((uint64_t)1 << 50)
0238
0239 #define QPU_BRANCH_RADDR_A_SHIFT        45
0240 #define QPU_BRANCH_RADDR_A_MASK         QPU_MASK(49, 45)
0241
0242 #define QPU_SF                          ((uint64_t)1 << 45)
0243
0244 #define QPU_WADDR_ADD_SHIFT             38
0245 #define QPU_WADDR_ADD_MASK              QPU_MASK(43, 38)
0246 #define QPU_WADDR_MUL_SHIFT             32
0247 #define QPU_WADDR_MUL_MASK              QPU_MASK(37, 32)
0248
0249 #define QPU_OP_MUL_SHIFT                29
0250 #define QPU_OP_MUL_MASK                 QPU_MASK(31, 29)
0251
0252 #define QPU_RADDR_A_SHIFT               18
0253 #define QPU_RADDR_A_MASK                QPU_MASK(23, 18)
0254 #define QPU_RADDR_B_SHIFT               12
0255 #define QPU_RADDR_B_MASK                QPU_MASK(17, 12)
0256 #define QPU_SMALL_IMM_SHIFT             12
0257 #define QPU_SMALL_IMM_MASK              QPU_MASK(17, 12)
0258
0259 #define QPU_ADD_A_SHIFT                 9
0260 #define QPU_ADD_A_MASK                  QPU_MASK(11, 9)
0261 #define QPU_ADD_B_SHIFT                 6
0262 #define QPU_ADD_B_MASK                  QPU_MASK(8, 6)
0263 #define QPU_MUL_A_SHIFT                 3
0264 #define QPU_MUL_A_MASK                  QPU_MASK(5, 3)
0265 #define QPU_MUL_B_SHIFT                 0
0266 #define QPU_MUL_B_MASK                  QPU_MASK(2, 0)
0267
0268 #define QPU_WS                          ((uint64_t)1 << 44)
0269
0270 #define QPU_OP_ADD_SHIFT                24
0271 #define QPU_OP_ADD_MASK                 QPU_MASK(28, 24)
0272
0273 #define QPU_LOAD_IMM_SHIFT              0
0274 #define QPU_LOAD_IMM_MASK               QPU_MASK(31, 0)
0275
0276 #define QPU_BRANCH_TARGET_SHIFT         0
0277 #define QPU_BRANCH_TARGET_MASK          QPU_MASK(31, 0)
0278
0279 #endif /* VC4_QPU_DEFINES_H */