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0001 #ifndef _VC4_HDMI_REGS_H_
0002 #define _VC4_HDMI_REGS_H_
0003 
0004 #include <linux/pm_runtime.h>
0005 
0006 #include "vc4_hdmi.h"
0007 
0008 #define VC4_HDMI_PACKET_STRIDE          0x24
0009 
0010 enum vc4_hdmi_regs {
0011     VC4_INVALID = 0,
0012     VC4_HDMI,
0013     VC4_HD,
0014     VC5_CEC,
0015     VC5_CSC,
0016     VC5_DVP,
0017     VC5_PHY,
0018     VC5_RAM,
0019     VC5_RM,
0020 };
0021 
0022 enum vc4_hdmi_field {
0023     HDMI_AUDIO_PACKET_CONFIG,
0024     HDMI_CEC_CNTRL_1,
0025     HDMI_CEC_CNTRL_2,
0026     HDMI_CEC_CNTRL_3,
0027     HDMI_CEC_CNTRL_4,
0028     HDMI_CEC_CNTRL_5,
0029     HDMI_CEC_CPU_CLEAR,
0030     HDMI_CEC_CPU_MASK_CLEAR,
0031     HDMI_CEC_CPU_MASK_SET,
0032     HDMI_CEC_CPU_MASK_STATUS,
0033     HDMI_CEC_CPU_STATUS,
0034     HDMI_CEC_CPU_SET,
0035 
0036     /*
0037      * Transmit data, first byte is low byte of the 32-bit reg.
0038      * MSB of each byte transmitted first.
0039      */
0040     HDMI_CEC_RX_DATA_1,
0041     HDMI_CEC_RX_DATA_2,
0042     HDMI_CEC_RX_DATA_3,
0043     HDMI_CEC_RX_DATA_4,
0044     HDMI_CEC_TX_DATA_1,
0045     HDMI_CEC_TX_DATA_2,
0046     HDMI_CEC_TX_DATA_3,
0047     HDMI_CEC_TX_DATA_4,
0048     HDMI_CLOCK_STOP,
0049     HDMI_CORE_REV,
0050     HDMI_CRP_CFG,
0051     HDMI_CSC_12_11,
0052     HDMI_CSC_14_13,
0053     HDMI_CSC_22_21,
0054     HDMI_CSC_24_23,
0055     HDMI_CSC_32_31,
0056     HDMI_CSC_34_33,
0057     HDMI_CSC_CHANNEL_CTL,
0058     HDMI_CSC_CTL,
0059 
0060     /*
0061      * 20-bit fields containing CTS values to be transmitted if
0062      * !EXTERNAL_CTS_EN
0063      */
0064     HDMI_CTS_0,
0065     HDMI_CTS_1,
0066     HDMI_DEEP_COLOR_CONFIG_1,
0067     HDMI_DVP_CTL,
0068     HDMI_FIFO_CTL,
0069     HDMI_FRAME_COUNT,
0070     HDMI_GCP_CONFIG,
0071     HDMI_GCP_WORD_1,
0072     HDMI_HORZA,
0073     HDMI_HORZB,
0074     HDMI_HOTPLUG,
0075     HDMI_HOTPLUG_INT,
0076 
0077     /*
0078      * 3 bits per field, where each field maps from that
0079      * corresponding MAI bus channel to the given HDMI channel.
0080      */
0081     HDMI_MAI_CHANNEL_MAP,
0082     HDMI_MAI_CONFIG,
0083     HDMI_MAI_CTL,
0084 
0085     /*
0086      * Register for DMAing in audio data to be transported over
0087      * the MAI bus to the Falcon core.
0088      */
0089     HDMI_MAI_DATA,
0090 
0091     /* Format header to be placed on the MAI data. Unused. */
0092     HDMI_MAI_FMT,
0093 
0094     /* Last received format word on the MAI bus. */
0095     HDMI_MAI_FORMAT,
0096     HDMI_MAI_SMP,
0097     HDMI_MAI_THR,
0098     HDMI_M_CTL,
0099     HDMI_RAM_PACKET_CONFIG,
0100     HDMI_RAM_PACKET_START,
0101     HDMI_RAM_PACKET_STATUS,
0102     HDMI_RM_CONTROL,
0103     HDMI_RM_FORMAT,
0104     HDMI_RM_OFFSET,
0105     HDMI_SCHEDULER_CONTROL,
0106     HDMI_SCRAMBLER_CTL,
0107     HDMI_SW_RESET_CONTROL,
0108     HDMI_TX_PHY_CHANNEL_SWAP,
0109     HDMI_TX_PHY_CLK_DIV,
0110     HDMI_TX_PHY_CTL_0,
0111     HDMI_TX_PHY_CTL_1,
0112     HDMI_TX_PHY_CTL_2,
0113     HDMI_TX_PHY_CTL_3,
0114     HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1,
0115     HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2,
0116     HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4,
0117     HDMI_TX_PHY_PLL_CFG,
0118     HDMI_TX_PHY_PLL_CTL_0,
0119     HDMI_TX_PHY_PLL_CTL_1,
0120     HDMI_TX_PHY_POWERDOWN_CTL,
0121     HDMI_TX_PHY_RESET_CTL,
0122     HDMI_TX_PHY_TMDS_CLK_WORD_SEL,
0123     HDMI_VEC_INTERFACE_CFG,
0124     HDMI_VEC_INTERFACE_XBAR,
0125     HDMI_VERTA0,
0126     HDMI_VERTA1,
0127     HDMI_VERTB0,
0128     HDMI_VERTB1,
0129     HDMI_VID_CTL,
0130     HDMI_MISC_CONTROL,
0131     HDMI_FORMAT_DET_1,
0132     HDMI_FORMAT_DET_2,
0133     HDMI_FORMAT_DET_3,
0134     HDMI_FORMAT_DET_4,
0135     HDMI_FORMAT_DET_5,
0136     HDMI_FORMAT_DET_6,
0137     HDMI_FORMAT_DET_7,
0138     HDMI_FORMAT_DET_8,
0139     HDMI_FORMAT_DET_9,
0140     HDMI_FORMAT_DET_10,
0141 };
0142 
0143 struct vc4_hdmi_register {
0144     char *name;
0145     enum vc4_hdmi_regs reg;
0146     unsigned int offset;
0147 };
0148 
0149 #define _VC4_REG(_base, _reg, _offset)  \
0150     [_reg] = {              \
0151         .name = #_reg,          \
0152         .reg = _base,           \
0153         .offset = _offset,      \
0154     }
0155 
0156 #define VC4_HD_REG(reg, offset)     _VC4_REG(VC4_HD, reg, offset)
0157 #define VC4_HDMI_REG(reg, offset)   _VC4_REG(VC4_HDMI, reg, offset)
0158 #define VC5_CEC_REG(reg, offset)    _VC4_REG(VC5_CEC, reg, offset)
0159 #define VC5_CSC_REG(reg, offset)    _VC4_REG(VC5_CSC, reg, offset)
0160 #define VC5_DVP_REG(reg, offset)    _VC4_REG(VC5_DVP, reg, offset)
0161 #define VC5_PHY_REG(reg, offset)    _VC4_REG(VC5_PHY, reg, offset)
0162 #define VC5_RAM_REG(reg, offset)    _VC4_REG(VC5_RAM, reg, offset)
0163 #define VC5_RM_REG(reg, offset)     _VC4_REG(VC5_RM, reg, offset)
0164 
0165 static const struct vc4_hdmi_register __maybe_unused vc4_hdmi_fields[] = {
0166     VC4_HD_REG(HDMI_M_CTL, 0x000c),
0167     VC4_HD_REG(HDMI_MAI_CTL, 0x0014),
0168     VC4_HD_REG(HDMI_MAI_THR, 0x0018),
0169     VC4_HD_REG(HDMI_MAI_FMT, 0x001c),
0170     VC4_HD_REG(HDMI_MAI_DATA, 0x0020),
0171     VC4_HD_REG(HDMI_MAI_SMP, 0x002c),
0172     VC4_HD_REG(HDMI_VID_CTL, 0x0038),
0173     VC4_HD_REG(HDMI_CSC_CTL, 0x0040),
0174     VC4_HD_REG(HDMI_CSC_12_11, 0x0044),
0175     VC4_HD_REG(HDMI_CSC_14_13, 0x0048),
0176     VC4_HD_REG(HDMI_CSC_22_21, 0x004c),
0177     VC4_HD_REG(HDMI_CSC_24_23, 0x0050),
0178     VC4_HD_REG(HDMI_CSC_32_31, 0x0054),
0179     VC4_HD_REG(HDMI_CSC_34_33, 0x0058),
0180     VC4_HD_REG(HDMI_FRAME_COUNT, 0x0068),
0181 
0182     VC4_HDMI_REG(HDMI_CORE_REV, 0x0000),
0183     VC4_HDMI_REG(HDMI_SW_RESET_CONTROL, 0x0004),
0184     VC4_HDMI_REG(HDMI_HOTPLUG_INT, 0x0008),
0185     VC4_HDMI_REG(HDMI_HOTPLUG, 0x000c),
0186     VC4_HDMI_REG(HDMI_FIFO_CTL, 0x005c),
0187     VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x0090),
0188     VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0094),
0189     VC4_HDMI_REG(HDMI_MAI_FORMAT, 0x0098),
0190     VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x009c),
0191     VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x00a0),
0192     VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x00a4),
0193     VC4_HDMI_REG(HDMI_CRP_CFG, 0x00a8),
0194     VC4_HDMI_REG(HDMI_CTS_0, 0x00ac),
0195     VC4_HDMI_REG(HDMI_CTS_1, 0x00b0),
0196     VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x00c0),
0197     VC4_HDMI_REG(HDMI_HORZA, 0x00c4),
0198     VC4_HDMI_REG(HDMI_HORZB, 0x00c8),
0199     VC4_HDMI_REG(HDMI_VERTA0, 0x00cc),
0200     VC4_HDMI_REG(HDMI_VERTB0, 0x00d0),
0201     VC4_HDMI_REG(HDMI_VERTA1, 0x00d4),
0202     VC4_HDMI_REG(HDMI_VERTB1, 0x00d8),
0203     VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x00e4),
0204     VC4_HDMI_REG(HDMI_CEC_CNTRL_1, 0x00e8),
0205     VC4_HDMI_REG(HDMI_CEC_CNTRL_2, 0x00ec),
0206     VC4_HDMI_REG(HDMI_CEC_CNTRL_3, 0x00f0),
0207     VC4_HDMI_REG(HDMI_CEC_CNTRL_4, 0x00f4),
0208     VC4_HDMI_REG(HDMI_CEC_CNTRL_5, 0x00f8),
0209     VC4_HDMI_REG(HDMI_CEC_TX_DATA_1, 0x00fc),
0210     VC4_HDMI_REG(HDMI_CEC_TX_DATA_2, 0x0100),
0211     VC4_HDMI_REG(HDMI_CEC_TX_DATA_3, 0x0104),
0212     VC4_HDMI_REG(HDMI_CEC_TX_DATA_4, 0x0108),
0213     VC4_HDMI_REG(HDMI_CEC_RX_DATA_1, 0x010c),
0214     VC4_HDMI_REG(HDMI_CEC_RX_DATA_2, 0x0110),
0215     VC4_HDMI_REG(HDMI_CEC_RX_DATA_3, 0x0114),
0216     VC4_HDMI_REG(HDMI_CEC_RX_DATA_4, 0x0118),
0217     VC4_HDMI_REG(HDMI_TX_PHY_RESET_CTL, 0x02c0),
0218     VC4_HDMI_REG(HDMI_TX_PHY_CTL_0, 0x02c4),
0219     VC4_HDMI_REG(HDMI_CEC_CPU_STATUS, 0x0340),
0220     VC4_HDMI_REG(HDMI_CEC_CPU_SET, 0x0344),
0221     VC4_HDMI_REG(HDMI_CEC_CPU_CLEAR, 0x0348),
0222     VC4_HDMI_REG(HDMI_CEC_CPU_MASK_STATUS, 0x034c),
0223     VC4_HDMI_REG(HDMI_CEC_CPU_MASK_SET, 0x0350),
0224     VC4_HDMI_REG(HDMI_CEC_CPU_MASK_CLEAR, 0x0354),
0225     VC4_HDMI_REG(HDMI_RAM_PACKET_START, 0x0400),
0226 };
0227 
0228 static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi0_fields[] = {
0229     VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
0230     VC4_HD_REG(HDMI_MAI_CTL, 0x0010),
0231     VC4_HD_REG(HDMI_MAI_THR, 0x0014),
0232     VC4_HD_REG(HDMI_MAI_FMT, 0x0018),
0233     VC4_HD_REG(HDMI_MAI_DATA, 0x001c),
0234     VC4_HD_REG(HDMI_MAI_SMP, 0x0020),
0235     VC4_HD_REG(HDMI_VID_CTL, 0x0044),
0236     VC4_HD_REG(HDMI_FRAME_COUNT, 0x0060),
0237 
0238     VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074),
0239     VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8),
0240     VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc),
0241     VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4),
0242     VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8),
0243     VC4_HDMI_REG(HDMI_CTS_0, 0x0cc),
0244     VC4_HDMI_REG(HDMI_CTS_1, 0x0d0),
0245     VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0),
0246     VC4_HDMI_REG(HDMI_HORZA, 0x0e4),
0247     VC4_HDMI_REG(HDMI_HORZB, 0x0e8),
0248     VC4_HDMI_REG(HDMI_VERTA0, 0x0ec),
0249     VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
0250     VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
0251     VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
0252     VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x100),
0253     VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
0254     VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
0255     VC4_HDMI_REG(HDMI_FORMAT_DET_1, 0x134),
0256     VC4_HDMI_REG(HDMI_FORMAT_DET_2, 0x138),
0257     VC4_HDMI_REG(HDMI_FORMAT_DET_3, 0x13c),
0258     VC4_HDMI_REG(HDMI_FORMAT_DET_4, 0x140),
0259     VC4_HDMI_REG(HDMI_FORMAT_DET_5, 0x144),
0260     VC4_HDMI_REG(HDMI_FORMAT_DET_6, 0x148),
0261     VC4_HDMI_REG(HDMI_FORMAT_DET_7, 0x14c),
0262     VC4_HDMI_REG(HDMI_FORMAT_DET_8, 0x150),
0263     VC4_HDMI_REG(HDMI_FORMAT_DET_9, 0x154),
0264     VC4_HDMI_REG(HDMI_FORMAT_DET_10, 0x158),
0265     VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),
0266     VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),
0267     VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),
0268     VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
0269     VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
0270 
0271     VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
0272     VC5_DVP_REG(HDMI_VEC_INTERFACE_CFG, 0x0ec),
0273     VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
0274 
0275     VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
0276     VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
0277     VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
0278     VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
0279     VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
0280     VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
0281     VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
0282     VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
0283     VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
0284     VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
0285     VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
0286     VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
0287     VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
0288     VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
0289     VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
0290 
0291     VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
0292     VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
0293     VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
0294 
0295     VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
0296 
0297     VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
0298     VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
0299     VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
0300     VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
0301     VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
0302     VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
0303     VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
0304     VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
0305     VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
0306     VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
0307     VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
0308     VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
0309     VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
0310 
0311     VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
0312     VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
0313     VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
0314     VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
0315     VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
0316     VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
0317     VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
0318     VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
0319 };
0320 
0321 static const struct vc4_hdmi_register __maybe_unused vc5_hdmi_hdmi1_fields[] = {
0322     VC4_HD_REG(HDMI_DVP_CTL, 0x0000),
0323     VC4_HD_REG(HDMI_MAI_CTL, 0x0030),
0324     VC4_HD_REG(HDMI_MAI_THR, 0x0034),
0325     VC4_HD_REG(HDMI_MAI_FMT, 0x0038),
0326     VC4_HD_REG(HDMI_MAI_DATA, 0x003c),
0327     VC4_HD_REG(HDMI_MAI_SMP, 0x0040),
0328     VC4_HD_REG(HDMI_VID_CTL, 0x0048),
0329     VC4_HD_REG(HDMI_FRAME_COUNT, 0x0064),
0330 
0331     VC4_HDMI_REG(HDMI_FIFO_CTL, 0x074),
0332     VC4_HDMI_REG(HDMI_AUDIO_PACKET_CONFIG, 0x0b8),
0333     VC4_HDMI_REG(HDMI_RAM_PACKET_CONFIG, 0x0bc),
0334     VC4_HDMI_REG(HDMI_RAM_PACKET_STATUS, 0x0c4),
0335     VC4_HDMI_REG(HDMI_CRP_CFG, 0x0c8),
0336     VC4_HDMI_REG(HDMI_CTS_0, 0x0cc),
0337     VC4_HDMI_REG(HDMI_CTS_1, 0x0d0),
0338     VC4_HDMI_REG(HDMI_SCHEDULER_CONTROL, 0x0e0),
0339     VC4_HDMI_REG(HDMI_HORZA, 0x0e4),
0340     VC4_HDMI_REG(HDMI_HORZB, 0x0e8),
0341     VC4_HDMI_REG(HDMI_VERTA0, 0x0ec),
0342     VC4_HDMI_REG(HDMI_VERTB0, 0x0f0),
0343     VC4_HDMI_REG(HDMI_VERTA1, 0x0f4),
0344     VC4_HDMI_REG(HDMI_VERTB1, 0x0f8),
0345     VC4_HDMI_REG(HDMI_MISC_CONTROL, 0x100),
0346     VC4_HDMI_REG(HDMI_MAI_CHANNEL_MAP, 0x09c),
0347     VC4_HDMI_REG(HDMI_MAI_CONFIG, 0x0a0),
0348     VC4_HDMI_REG(HDMI_FORMAT_DET_1, 0x134),
0349     VC4_HDMI_REG(HDMI_FORMAT_DET_2, 0x138),
0350     VC4_HDMI_REG(HDMI_FORMAT_DET_3, 0x13c),
0351     VC4_HDMI_REG(HDMI_FORMAT_DET_4, 0x140),
0352     VC4_HDMI_REG(HDMI_FORMAT_DET_5, 0x144),
0353     VC4_HDMI_REG(HDMI_FORMAT_DET_6, 0x148),
0354     VC4_HDMI_REG(HDMI_FORMAT_DET_7, 0x14c),
0355     VC4_HDMI_REG(HDMI_FORMAT_DET_8, 0x150),
0356     VC4_HDMI_REG(HDMI_FORMAT_DET_9, 0x154),
0357     VC4_HDMI_REG(HDMI_FORMAT_DET_10, 0x158),
0358     VC4_HDMI_REG(HDMI_DEEP_COLOR_CONFIG_1, 0x170),
0359     VC4_HDMI_REG(HDMI_GCP_CONFIG, 0x178),
0360     VC4_HDMI_REG(HDMI_GCP_WORD_1, 0x17c),
0361     VC4_HDMI_REG(HDMI_HOTPLUG, 0x1a8),
0362     VC4_HDMI_REG(HDMI_SCRAMBLER_CTL, 0x1c4),
0363 
0364     VC5_DVP_REG(HDMI_CLOCK_STOP, 0x0bc),
0365     VC5_DVP_REG(HDMI_VEC_INTERFACE_CFG, 0x0ec),
0366     VC5_DVP_REG(HDMI_VEC_INTERFACE_XBAR, 0x0f0),
0367 
0368     VC5_PHY_REG(HDMI_TX_PHY_RESET_CTL, 0x000),
0369     VC5_PHY_REG(HDMI_TX_PHY_POWERDOWN_CTL, 0x004),
0370     VC5_PHY_REG(HDMI_TX_PHY_CTL_0, 0x008),
0371     VC5_PHY_REG(HDMI_TX_PHY_CTL_1, 0x00c),
0372     VC5_PHY_REG(HDMI_TX_PHY_CTL_2, 0x010),
0373     VC5_PHY_REG(HDMI_TX_PHY_CTL_3, 0x014),
0374     VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_0, 0x01c),
0375     VC5_PHY_REG(HDMI_TX_PHY_PLL_CTL_1, 0x020),
0376     VC5_PHY_REG(HDMI_TX_PHY_CLK_DIV, 0x028),
0377     VC5_PHY_REG(HDMI_TX_PHY_PLL_CFG, 0x034),
0378     VC5_PHY_REG(HDMI_TX_PHY_CHANNEL_SWAP, 0x04c),
0379     VC5_PHY_REG(HDMI_TX_PHY_TMDS_CLK_WORD_SEL, 0x044),
0380     VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_1, 0x050),
0381     VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_2, 0x054),
0382     VC5_PHY_REG(HDMI_TX_PHY_PLL_CALIBRATION_CONFIG_4, 0x05c),
0383 
0384     VC5_RM_REG(HDMI_RM_CONTROL, 0x000),
0385     VC5_RM_REG(HDMI_RM_OFFSET, 0x018),
0386     VC5_RM_REG(HDMI_RM_FORMAT, 0x01c),
0387 
0388     VC5_RAM_REG(HDMI_RAM_PACKET_START, 0x000),
0389 
0390     VC5_CEC_REG(HDMI_CEC_CNTRL_1, 0x010),
0391     VC5_CEC_REG(HDMI_CEC_CNTRL_2, 0x014),
0392     VC5_CEC_REG(HDMI_CEC_CNTRL_3, 0x018),
0393     VC5_CEC_REG(HDMI_CEC_CNTRL_4, 0x01c),
0394     VC5_CEC_REG(HDMI_CEC_CNTRL_5, 0x020),
0395     VC5_CEC_REG(HDMI_CEC_TX_DATA_1, 0x028),
0396     VC5_CEC_REG(HDMI_CEC_TX_DATA_2, 0x02c),
0397     VC5_CEC_REG(HDMI_CEC_TX_DATA_3, 0x030),
0398     VC5_CEC_REG(HDMI_CEC_TX_DATA_4, 0x034),
0399     VC5_CEC_REG(HDMI_CEC_RX_DATA_1, 0x038),
0400     VC5_CEC_REG(HDMI_CEC_RX_DATA_2, 0x03c),
0401     VC5_CEC_REG(HDMI_CEC_RX_DATA_3, 0x040),
0402     VC5_CEC_REG(HDMI_CEC_RX_DATA_4, 0x044),
0403 
0404     VC5_CSC_REG(HDMI_CSC_CTL, 0x000),
0405     VC5_CSC_REG(HDMI_CSC_12_11, 0x004),
0406     VC5_CSC_REG(HDMI_CSC_14_13, 0x008),
0407     VC5_CSC_REG(HDMI_CSC_22_21, 0x00c),
0408     VC5_CSC_REG(HDMI_CSC_24_23, 0x010),
0409     VC5_CSC_REG(HDMI_CSC_32_31, 0x014),
0410     VC5_CSC_REG(HDMI_CSC_34_33, 0x018),
0411     VC5_CSC_REG(HDMI_CSC_CHANNEL_CTL, 0x02c),
0412 };
0413 
0414 static inline
0415 void __iomem *__vc4_hdmi_get_field_base(struct vc4_hdmi *hdmi,
0416                     enum vc4_hdmi_regs reg)
0417 {
0418     switch (reg) {
0419     case VC4_HD:
0420         return hdmi->hd_regs;
0421 
0422     case VC4_HDMI:
0423         return hdmi->hdmicore_regs;
0424 
0425     case VC5_CSC:
0426         return hdmi->csc_regs;
0427 
0428     case VC5_CEC:
0429         return hdmi->cec_regs;
0430 
0431     case VC5_DVP:
0432         return hdmi->dvp_regs;
0433 
0434     case VC5_PHY:
0435         return hdmi->phy_regs;
0436 
0437     case VC5_RAM:
0438         return hdmi->ram_regs;
0439 
0440     case VC5_RM:
0441         return hdmi->rm_regs;
0442 
0443     default:
0444         return NULL;
0445     }
0446 
0447     return NULL;
0448 }
0449 
0450 static inline u32 vc4_hdmi_read(struct vc4_hdmi *hdmi,
0451                 enum vc4_hdmi_field reg)
0452 {
0453     const struct vc4_hdmi_register *field;
0454     const struct vc4_hdmi_variant *variant = hdmi->variant;
0455     void __iomem *base;
0456 
0457     WARN_ON(pm_runtime_status_suspended(&hdmi->pdev->dev));
0458 
0459     if (reg >= variant->num_registers) {
0460         dev_warn(&hdmi->pdev->dev,
0461              "Invalid register ID %u\n", reg);
0462         return 0;
0463     }
0464 
0465     field = &variant->registers[reg];
0466     base = __vc4_hdmi_get_field_base(hdmi, field->reg);
0467     if (!base) {
0468         dev_warn(&hdmi->pdev->dev,
0469              "Unknown register ID %u\n", reg);
0470         return 0;
0471     }
0472 
0473     return readl(base + field->offset);
0474 }
0475 #define HDMI_READ(reg)      vc4_hdmi_read(vc4_hdmi, reg)
0476 
0477 static inline void vc4_hdmi_write(struct vc4_hdmi *hdmi,
0478                   enum vc4_hdmi_field reg,
0479                   u32 value)
0480 {
0481     const struct vc4_hdmi_register *field;
0482     const struct vc4_hdmi_variant *variant = hdmi->variant;
0483     void __iomem *base;
0484 
0485     lockdep_assert_held(&hdmi->hw_lock);
0486 
0487     WARN_ON(pm_runtime_status_suspended(&hdmi->pdev->dev));
0488 
0489     if (reg >= variant->num_registers) {
0490         dev_warn(&hdmi->pdev->dev,
0491              "Invalid register ID %u\n", reg);
0492         return;
0493     }
0494 
0495     field = &variant->registers[reg];
0496     base = __vc4_hdmi_get_field_base(hdmi, field->reg);
0497     if (!base)
0498         return;
0499 
0500     writel(value, base + field->offset);
0501 }
0502 #define HDMI_WRITE(reg, val)    vc4_hdmi_write(vc4_hdmi, reg, val)
0503 
0504 #endif /* _VC4_HDMI_REGS_H_ */
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