OSCL-LXR

DOC: VC4 GEM BO management support The VC4 GPU architecture (both scanout and rendering) has direct access to system memory with no MMU in between.

DOC: VC4 CRTC module In VC4, the Pixel Valve is what most closely corresponds to the DRM's concept of a CRTC.

DOC: VC4 DPI module The VC4 DPI hardware supports MIPI DPI type 4 and Nokia ViSSI signals. On BCM2835, these can be routed out to GPIO0-27 with the ALT2 function.

DOC: VC4 DSI0/DSI1 module BCM2835 contains two DSI modules, DSI0 and DSI1.

DOC: VC4 Falcon HDMI module The HDMI core has a state machine and a PHY.

DOC: VC4 HVS module.

DOC: Interrupt management for the V3D engine We have an interrupt status register (V3D_INTCTL) which reports interrupts, and where writing 1 bits clears those interrupts.

DOC: VC4 KMS This is the general code for implementing KMS mode setting that doesn't clearly associate with any of the other objects (plane, crtc, HDMI encoder).

DOC: VC4 V3D performance monitor module The V3D block provides 16 hardware counters which can count various events.

DOC: VC4 plane module Each DRM plane is a layer of pixels being scanned out by the HVS.

DOC: Command list validator for VC4.

DOC: Shader validator for VC4.

DOC: VC4 SDTV module The VEC encoder generates PAL or NTSC composite video output.