drm/v3d/v3d_drv.h

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /* Copyright (C) 2015-2018 Broadcom */
0003
0004 #include <linux/delay.h>
0005 #include <linux/mutex.h>
0006 #include <linux/spinlock_types.h>
0007 #include <linux/workqueue.h>
0008
0009 #include <drm/drm_encoder.h>
0010 #include <drm/drm_gem.h>
0011 #include <drm/drm_gem_shmem_helper.h>
0012 #include <drm/gpu_scheduler.h>
0013
0014 #include "uapi/drm/v3d_drm.h"
0015
0016 struct clk;
0017 struct platform_device;
0018 struct reset_control;
0019
0020 #define GMP_GRANULARITY (128 * 1024)
0021
0022 #define V3D_MAX_QUEUES (V3D_CACHE_CLEAN + 1)
0023
0024 struct v3d_queue_state {
0025     struct drm_gpu_scheduler sched;
0026
0027     u64 fence_context;
0028     u64 emit_seqno;
0029 };
0030
0031 /* Performance monitor object. The perform lifetime is controlled by userspace
0032  * using perfmon related ioctls. A perfmon can be attached to a submit_cl
0033  * request, and when this is the case, HW perf counters will be activated just
0034  * before the submit_cl is submitted to the GPU and disabled when the job is
0035  * done. This way, only events related to a specific job will be counted.
0036  */
0037 struct v3d_perfmon {
0038     /* Tracks the number of users of the perfmon, when this counter reaches
0039      * zero the perfmon is destroyed.
0040      */
0041     refcount_t refcnt;
0042
0043     /* Protects perfmon stop, as it can be invoked from multiple places. */
0044     struct mutex lock;
0045
0046     /* Number of counters activated in this perfmon instance
0047      * (should be less than DRM_V3D_MAX_PERF_COUNTERS).
0048      */
0049     u8 ncounters;
0050
0051     /* Events counted by the HW perf counters. */
0052     u8 counters[DRM_V3D_MAX_PERF_COUNTERS];
0053
0054     /* Storage for counter values. Counters are incremented by the
0055      * HW perf counter values every time the perfmon is attached
0056      * to a GPU job.  This way, perfmon users don't have to
0057      * retrieve the results after each job if they want to track
0058      * events covering several submissions.  Note that counter
0059      * values can't be reset, but you can fake a reset by
0060      * destroying the perfmon and creating a new one.
0061      */
0062     u64 values[];
0063 };
0064
0065 struct v3d_dev {
0066     struct drm_device drm;
0067
0068     /* Short representation (e.g. 33, 41) of the V3D tech version
0069      * and revision.
0070      */
0071     int ver;
0072     bool single_irq_line;
0073
0074     void __iomem *hub_regs;
0075     void __iomem *core_regs[3];
0076     void __iomem *bridge_regs;
0077     void __iomem *gca_regs;
0078     struct clk *clk;
0079     struct reset_control *reset;
0080
0081     /* Virtual and DMA addresses of the single shared page table. */
0082     volatile u32 *pt;
0083     dma_addr_t pt_paddr;
0084
0085     /* Virtual and DMA addresses of the MMU's scratch page.  When
0086      * a read or write is invalid in the MMU, it will be
0087      * redirected here.
0088      */
0089     void *mmu_scratch;
0090     dma_addr_t mmu_scratch_paddr;
0091     /* virtual address bits from V3D to the MMU. */
0092     int va_width;
0093
0094     /* Number of V3D cores. */
0095     u32 cores;
0096
0097     /* Allocator managing the address space.  All units are in
0098      * number of pages.
0099      */
0100     struct drm_mm mm;
0101     spinlock_t mm_lock;
0102
0103     struct work_struct overflow_mem_work;
0104
0105     struct v3d_bin_job *bin_job;
0106     struct v3d_render_job *render_job;
0107     struct v3d_tfu_job *tfu_job;
0108     struct v3d_csd_job *csd_job;
0109
0110     struct v3d_queue_state queue[V3D_MAX_QUEUES];
0111
0112     /* Spinlock used to synchronize the overflow memory
0113      * management against bin job submission.
0114      */
0115     spinlock_t job_lock;
0116
0117     /* Used to track the active perfmon if any. */
0118     struct v3d_perfmon *active_perfmon;
0119
0120     /* Protects bo_stats */
0121     struct mutex bo_lock;
0122
0123     /* Lock taken when resetting the GPU, to keep multiple
0124      * processes from trying to park the scheduler threads and
0125      * reset at once.
0126      */
0127     struct mutex reset_lock;
0128
0129     /* Lock taken when creating and pushing the GPU scheduler
0130      * jobs, to keep the sched-fence seqnos in order.
0131      */
0132     struct mutex sched_lock;
0133
0134     /* Lock taken during a cache clean and when initiating an L2
0135      * flush, to keep L2 flushes from interfering with the
0136      * synchronous L2 cleans.
0137      */
0138     struct mutex cache_clean_lock;
0139
0140     struct {
0141         u32 num_allocated;
0142         u32 pages_allocated;
0143     } bo_stats;
0144 };
0145
0146 static inline struct v3d_dev *
0147 to_v3d_dev(struct drm_device *dev)
0148 {
0149     return container_of(dev, struct v3d_dev, drm);
0150 }
0151
0152 static inline bool
0153 v3d_has_csd(struct v3d_dev *v3d)
0154 {
0155     return v3d->ver >= 41;
0156 }
0157
0158 #define v3d_to_pdev(v3d) to_platform_device((v3d)->drm.dev)
0159
0160 /* The per-fd struct, which tracks the MMU mappings. */
0161 struct v3d_file_priv {
0162     struct v3d_dev *v3d;
0163
0164     struct {
0165         struct idr idr;
0166         struct mutex lock;
0167     } perfmon;
0168
0169     struct drm_sched_entity sched_entity[V3D_MAX_QUEUES];
0170 };
0171
0172 struct v3d_bo {
0173     struct drm_gem_shmem_object base;
0174
0175     struct drm_mm_node node;
0176
0177     /* List entry for the BO's position in
0178      * v3d_render_job->unref_list
0179      */
0180     struct list_head unref_head;
0181 };
0182
0183 static inline struct v3d_bo *
0184 to_v3d_bo(struct drm_gem_object *bo)
0185 {
0186     return (struct v3d_bo *)bo;
0187 }
0188
0189 struct v3d_fence {
0190     struct dma_fence base;
0191     struct drm_device *dev;
0192     /* v3d seqno for signaled() test */
0193     u64 seqno;
0194     enum v3d_queue queue;
0195 };
0196
0197 static inline struct v3d_fence *
0198 to_v3d_fence(struct dma_fence *fence)
0199 {
0200     return (struct v3d_fence *)fence;
0201 }
0202
0203 #define V3D_READ(offset) readl(v3d->hub_regs + offset)
0204 #define V3D_WRITE(offset, val) writel(val, v3d->hub_regs + offset)
0205
0206 #define V3D_BRIDGE_READ(offset) readl(v3d->bridge_regs + offset)
0207 #define V3D_BRIDGE_WRITE(offset, val) writel(val, v3d->bridge_regs + offset)
0208
0209 #define V3D_GCA_READ(offset) readl(v3d->gca_regs + offset)
0210 #define V3D_GCA_WRITE(offset, val) writel(val, v3d->gca_regs + offset)
0211
0212 #define V3D_CORE_READ(core, offset) readl(v3d->core_regs[core] + offset)
0213 #define V3D_CORE_WRITE(core, offset, val) writel(val, v3d->core_regs[core] + offset)
0214
0215 struct v3d_job {
0216     struct drm_sched_job base;
0217
0218     struct kref refcount;
0219
0220     struct v3d_dev *v3d;
0221
0222     /* This is the array of BOs that were looked up at the start
0223      * of submission.
0224      */
0225     struct drm_gem_object **bo;
0226     u32 bo_count;
0227
0228     /* v3d fence to be signaled by IRQ handler when the job is complete. */
0229     struct dma_fence *irq_fence;
0230
0231     /* scheduler fence for when the job is considered complete and
0232      * the BO reservations can be released.
0233      */
0234     struct dma_fence *done_fence;
0235
0236     /* Pointer to a performance monitor object if the user requested it,
0237      * NULL otherwise.
0238      */
0239     struct v3d_perfmon *perfmon;
0240
0241     /* Callback for the freeing of the job on refcount going to 0. */
0242     void (*free)(struct kref *ref);
0243 };
0244
0245 struct v3d_bin_job {
0246     struct v3d_job base;
0247
0248     /* GPU virtual addresses of the start/end of the CL job. */
0249     u32 start, end;
0250
0251     u32 timedout_ctca, timedout_ctra;
0252
0253     /* Corresponding render job, for attaching our overflow memory. */
0254     struct v3d_render_job *render;
0255
0256     /* Submitted tile memory allocation start/size, tile state. */
0257     u32 qma, qms, qts;
0258 };
0259
0260 struct v3d_render_job {
0261     struct v3d_job base;
0262
0263     /* GPU virtual addresses of the start/end of the CL job. */
0264     u32 start, end;
0265
0266     u32 timedout_ctca, timedout_ctra;
0267
0268     /* List of overflow BOs used in the job that need to be
0269      * released once the job is complete.
0270      */
0271     struct list_head unref_list;
0272 };
0273
0274 struct v3d_tfu_job {
0275     struct v3d_job base;
0276
0277     struct drm_v3d_submit_tfu args;
0278 };
0279
0280 struct v3d_csd_job {
0281     struct v3d_job base;
0282
0283     u32 timedout_batches;
0284
0285     struct drm_v3d_submit_csd args;
0286 };
0287
0288 struct v3d_submit_outsync {
0289     struct drm_syncobj *syncobj;
0290 };
0291
0292 struct v3d_submit_ext {
0293     u32 flags;
0294     u32 wait_stage;
0295
0296     u32 in_sync_count;
0297     u64 in_syncs;
0298
0299     u32 out_sync_count;
0300     struct v3d_submit_outsync *out_syncs;
0301 };
0302
0303 /**
0304  * __wait_for - magic wait macro
0305  *
0306  * Macro to help avoid open coding check/wait/timeout patterns. Note that it's
0307  * important that we check the condition again after having timed out, since the
0308  * timeout could be due to preemption or similar and we've never had a chance to
0309  * check the condition before the timeout.
0310  */
0311 #define __wait_for(OP, COND, US, Wmin, Wmax) ({ \
0312     const ktime_t end__ = ktime_add_ns(ktime_get_raw(), 1000ll * (US)); \
0313     long wait__ = (Wmin); /* recommended min for usleep is 10 us */ \
0314     int ret__;                          \
0315     might_sleep();                          \
0316     for (;;) {                          \
0317         const bool expired__ = ktime_after(ktime_get_raw(), end__); \
0318         OP;                         \
0319         /* Guarantee COND check prior to timeout */     \
0320         barrier();                      \
0321         if (COND) {                     \
0322             ret__ = 0;                  \
0323             break;                      \
0324         }                           \
0325         if (expired__) {                    \
0326             ret__ = -ETIMEDOUT;             \
0327             break;                      \
0328         }                           \
0329         usleep_range(wait__, wait__ * 2);           \
0330         if (wait__ < (Wmax))                    \
0331             wait__ <<= 1;                   \
0332     }                               \
0333     ret__;                              \
0334 })
0335
0336 #define _wait_for(COND, US, Wmin, Wmax) __wait_for(, (COND), (US), (Wmin), \
0337                            (Wmax))
0338 #define wait_for(COND, MS)      _wait_for((COND), (MS) * 1000, 10, 1000)
0339
0340 static inline unsigned long nsecs_to_jiffies_timeout(const u64 n)
0341 {
0342     /* nsecs_to_jiffies64() does not guard against overflow */
0343     if (NSEC_PER_SEC % HZ &&
0344         div_u64(n, NSEC_PER_SEC) >= MAX_JIFFY_OFFSET / HZ)
0345         return MAX_JIFFY_OFFSET;
0346
0347     return min_t(u64, MAX_JIFFY_OFFSET, nsecs_to_jiffies64(n) + 1);
0348 }
0349
0350 /* v3d_bo.c */
0351 struct drm_gem_object *v3d_create_object(struct drm_device *dev, size_t size);
0352 void v3d_free_object(struct drm_gem_object *gem_obj);
0353 struct v3d_bo *v3d_bo_create(struct drm_device *dev, struct drm_file *file_priv,
0354                  size_t size);
0355 int v3d_create_bo_ioctl(struct drm_device *dev, void *data,
0356             struct drm_file *file_priv);
0357 int v3d_mmap_bo_ioctl(struct drm_device *dev, void *data,
0358               struct drm_file *file_priv);
0359 int v3d_get_bo_offset_ioctl(struct drm_device *dev, void *data,
0360                 struct drm_file *file_priv);
0361 struct drm_gem_object *v3d_prime_import_sg_table(struct drm_device *dev,
0362                          struct dma_buf_attachment *attach,
0363                          struct sg_table *sgt);
0364
0365 /* v3d_debugfs.c */
0366 void v3d_debugfs_init(struct drm_minor *minor);
0367
0368 /* v3d_fence.c */
0369 extern const struct dma_fence_ops v3d_fence_ops;
0370 struct dma_fence *v3d_fence_create(struct v3d_dev *v3d, enum v3d_queue queue);
0371
0372 /* v3d_gem.c */
0373 int v3d_gem_init(struct drm_device *dev);
0374 void v3d_gem_destroy(struct drm_device *dev);
0375 int v3d_submit_cl_ioctl(struct drm_device *dev, void *data,
0376             struct drm_file *file_priv);
0377 int v3d_submit_tfu_ioctl(struct drm_device *dev, void *data,
0378              struct drm_file *file_priv);
0379 int v3d_submit_csd_ioctl(struct drm_device *dev, void *data,
0380              struct drm_file *file_priv);
0381 int v3d_wait_bo_ioctl(struct drm_device *dev, void *data,
0382               struct drm_file *file_priv);
0383 void v3d_job_cleanup(struct v3d_job *job);
0384 void v3d_job_put(struct v3d_job *job);
0385 void v3d_reset(struct v3d_dev *v3d);
0386 void v3d_invalidate_caches(struct v3d_dev *v3d);
0387 void v3d_clean_caches(struct v3d_dev *v3d);
0388
0389 /* v3d_irq.c */
0390 int v3d_irq_init(struct v3d_dev *v3d);
0391 void v3d_irq_enable(struct v3d_dev *v3d);
0392 void v3d_irq_disable(struct v3d_dev *v3d);
0393 void v3d_irq_reset(struct v3d_dev *v3d);
0394
0395 /* v3d_mmu.c */
0396 int v3d_mmu_get_offset(struct drm_file *file_priv, struct v3d_bo *bo,
0397                u32 *offset);
0398 int v3d_mmu_set_page_table(struct v3d_dev *v3d);
0399 void v3d_mmu_insert_ptes(struct v3d_bo *bo);
0400 void v3d_mmu_remove_ptes(struct v3d_bo *bo);
0401
0402 /* v3d_sched.c */
0403 int v3d_sched_init(struct v3d_dev *v3d);
0404 void v3d_sched_fini(struct v3d_dev *v3d);
0405
0406 /* v3d_perfmon.c */
0407 void v3d_perfmon_get(struct v3d_perfmon *perfmon);
0408 void v3d_perfmon_put(struct v3d_perfmon *perfmon);
0409 void v3d_perfmon_start(struct v3d_dev *v3d, struct v3d_perfmon *perfmon);
0410 void v3d_perfmon_stop(struct v3d_dev *v3d, struct v3d_perfmon *perfmon,
0411               bool capture);
0412 struct v3d_perfmon *v3d_perfmon_find(struct v3d_file_priv *v3d_priv, int id);
0413 void v3d_perfmon_open_file(struct v3d_file_priv *v3d_priv);
0414 void v3d_perfmon_close_file(struct v3d_file_priv *v3d_priv);
0415 int v3d_perfmon_create_ioctl(struct drm_device *dev, void *data,
0416                  struct drm_file *file_priv);
0417 int v3d_perfmon_destroy_ioctl(struct drm_device *dev, void *data,
0418                   struct drm_file *file_priv);
0419 int v3d_perfmon_get_values_ioctl(struct drm_device *dev, void *data,
0420                  struct drm_file *file_priv);