drm/v3d/v3d_drv.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /* Copyright (C) 2014-2018 Broadcom */
0003
0004 /**
0005  * DOC: Broadcom V3D Graphics Driver
0006  *
0007  * This driver supports the Broadcom V3D 3.3 and 4.1 OpenGL ES GPUs.
0008  * For V3D 2.x support, see the VC4 driver.
0009  *
0010  * The V3D GPU includes a tiled render (composed of a bin and render
0011  * pipelines), the TFU (texture formatting unit), and the CSD (compute
0012  * shader dispatch).
0013  */
0014
0015 #include <linux/clk.h>
0016 #include <linux/device.h>
0017 #include <linux/dma-mapping.h>
0018 #include <linux/io.h>
0019 #include <linux/module.h>
0020 #include <linux/of_platform.h>
0021 #include <linux/platform_device.h>
0022 #include <linux/reset.h>
0023
0024 #include <drm/drm_drv.h>
0025 #include <drm/drm_fb_cma_helper.h>
0026 #include <drm/drm_fb_helper.h>
0027 #include <drm/drm_managed.h>
0028 #include <uapi/drm/v3d_drm.h>
0029
0030 #include "v3d_drv.h"
0031 #include "v3d_regs.h"
0032
0033 #define DRIVER_NAME "v3d"
0034 #define DRIVER_DESC "Broadcom V3D graphics"
0035 #define DRIVER_DATE "20180419"
0036 #define DRIVER_MAJOR 1
0037 #define DRIVER_MINOR 0
0038 #define DRIVER_PATCHLEVEL 0
0039
0040 static int v3d_get_param_ioctl(struct drm_device *dev, void *data,
0041                    struct drm_file *file_priv)
0042 {
0043     struct v3d_dev *v3d = to_v3d_dev(dev);
0044     struct drm_v3d_get_param *args = data;
0045     static const u32 reg_map[] = {
0046         [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_UIFCFG,
0047         [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_IDENT1,
0048         [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_IDENT2,
0049         [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_IDENT3,
0050         [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_IDENT0,
0051         [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_IDENT1,
0052         [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_IDENT2,
0053     };
0054
0055     if (args->pad != 0)
0056         return -EINVAL;
0057
0058     /* Note that DRM_V3D_PARAM_V3D_CORE0_IDENT0 is 0, so we need
0059      * to explicitly allow it in the "the register in our
0060      * parameter map" check.
0061      */
0062     if (args->param < ARRAY_SIZE(reg_map) &&
0063         (reg_map[args->param] ||
0064          args->param == DRM_V3D_PARAM_V3D_CORE0_IDENT0)) {
0065         u32 offset = reg_map[args->param];
0066
0067         if (args->value != 0)
0068             return -EINVAL;
0069
0070         if (args->param >= DRM_V3D_PARAM_V3D_CORE0_IDENT0 &&
0071             args->param <= DRM_V3D_PARAM_V3D_CORE0_IDENT2) {
0072             args->value = V3D_CORE_READ(0, offset);
0073         } else {
0074             args->value = V3D_READ(offset);
0075         }
0076         return 0;
0077     }
0078
0079     switch (args->param) {
0080     case DRM_V3D_PARAM_SUPPORTS_TFU:
0081         args->value = 1;
0082         return 0;
0083     case DRM_V3D_PARAM_SUPPORTS_CSD:
0084         args->value = v3d_has_csd(v3d);
0085         return 0;
0086     case DRM_V3D_PARAM_SUPPORTS_CACHE_FLUSH:
0087         args->value = 1;
0088         return 0;
0089     case DRM_V3D_PARAM_SUPPORTS_PERFMON:
0090         args->value = (v3d->ver >= 40);
0091         return 0;
0092     case DRM_V3D_PARAM_SUPPORTS_MULTISYNC_EXT:
0093         args->value = 1;
0094         return 0;
0095     default:
0096         DRM_DEBUG("Unknown parameter %d\n", args->param);
0097         return -EINVAL;
0098     }
0099 }
0100
0101 static int
0102 v3d_open(struct drm_device *dev, struct drm_file *file)
0103 {
0104     struct v3d_dev *v3d = to_v3d_dev(dev);
0105     struct v3d_file_priv *v3d_priv;
0106     struct drm_gpu_scheduler *sched;
0107     int i;
0108
0109     v3d_priv = kzalloc(sizeof(*v3d_priv), GFP_KERNEL);
0110     if (!v3d_priv)
0111         return -ENOMEM;
0112
0113     v3d_priv->v3d = v3d;
0114
0115     for (i = 0; i < V3D_MAX_QUEUES; i++) {
0116         sched = &v3d->queue[i].sched;
0117         drm_sched_entity_init(&v3d_priv->sched_entity[i],
0118                       DRM_SCHED_PRIORITY_NORMAL, &sched,
0119                       1, NULL);
0120     }
0121
0122     v3d_perfmon_open_file(v3d_priv);
0123     file->driver_priv = v3d_priv;
0124
0125     return 0;
0126 }
0127
0128 static void
0129 v3d_postclose(struct drm_device *dev, struct drm_file *file)
0130 {
0131     struct v3d_file_priv *v3d_priv = file->driver_priv;
0132     enum v3d_queue q;
0133
0134     for (q = 0; q < V3D_MAX_QUEUES; q++)
0135         drm_sched_entity_destroy(&v3d_priv->sched_entity[q]);
0136
0137     v3d_perfmon_close_file(v3d_priv);
0138     kfree(v3d_priv);
0139 }
0140
0141 DEFINE_DRM_GEM_FOPS(v3d_drm_fops);
0142
0143 /* DRM_AUTH is required on SUBMIT_CL for now, while we don't have GMP
0144  * protection between clients.  Note that render nodes would be
0145  * able to submit CLs that could access BOs from clients authenticated
0146  * with the master node.  The TFU doesn't use the GMP, so it would
0147  * need to stay DRM_AUTH until we do buffer size/offset validation.
0148  */
0149 static const struct drm_ioctl_desc v3d_drm_ioctls[] = {
0150     DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CL, v3d_submit_cl_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
0151     DRM_IOCTL_DEF_DRV(V3D_WAIT_BO, v3d_wait_bo_ioctl, DRM_RENDER_ALLOW),
0152     DRM_IOCTL_DEF_DRV(V3D_CREATE_BO, v3d_create_bo_ioctl, DRM_RENDER_ALLOW),
0153     DRM_IOCTL_DEF_DRV(V3D_MMAP_BO, v3d_mmap_bo_ioctl, DRM_RENDER_ALLOW),
0154     DRM_IOCTL_DEF_DRV(V3D_GET_PARAM, v3d_get_param_ioctl, DRM_RENDER_ALLOW),
0155     DRM_IOCTL_DEF_DRV(V3D_GET_BO_OFFSET, v3d_get_bo_offset_ioctl, DRM_RENDER_ALLOW),
0156     DRM_IOCTL_DEF_DRV(V3D_SUBMIT_TFU, v3d_submit_tfu_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
0157     DRM_IOCTL_DEF_DRV(V3D_SUBMIT_CSD, v3d_submit_csd_ioctl, DRM_RENDER_ALLOW | DRM_AUTH),
0158     DRM_IOCTL_DEF_DRV(V3D_PERFMON_CREATE, v3d_perfmon_create_ioctl, DRM_RENDER_ALLOW),
0159     DRM_IOCTL_DEF_DRV(V3D_PERFMON_DESTROY, v3d_perfmon_destroy_ioctl, DRM_RENDER_ALLOW),
0160     DRM_IOCTL_DEF_DRV(V3D_PERFMON_GET_VALUES, v3d_perfmon_get_values_ioctl, DRM_RENDER_ALLOW),
0161 };
0162
0163 static const struct drm_driver v3d_drm_driver = {
0164     .driver_features = (DRIVER_GEM |
0165                 DRIVER_RENDER |
0166                 DRIVER_SYNCOBJ),
0167
0168     .open = v3d_open,
0169     .postclose = v3d_postclose,
0170
0171 #if defined(CONFIG_DEBUG_FS)
0172     .debugfs_init = v3d_debugfs_init,
0173 #endif
0174
0175     .gem_create_object = v3d_create_object,
0176     .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
0177     .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
0178     .gem_prime_import_sg_table = v3d_prime_import_sg_table,
0179     .gem_prime_mmap = drm_gem_prime_mmap,
0180
0181     .ioctls = v3d_drm_ioctls,
0182     .num_ioctls = ARRAY_SIZE(v3d_drm_ioctls),
0183     .fops = &v3d_drm_fops,
0184
0185     .name = DRIVER_NAME,
0186     .desc = DRIVER_DESC,
0187     .date = DRIVER_DATE,
0188     .major = DRIVER_MAJOR,
0189     .minor = DRIVER_MINOR,
0190     .patchlevel = DRIVER_PATCHLEVEL,
0191 };
0192
0193 static const struct of_device_id v3d_of_match[] = {
0194     { .compatible = "brcm,2711-v3d" },
0195     { .compatible = "brcm,7268-v3d" },
0196     { .compatible = "brcm,7278-v3d" },
0197     {},
0198 };
0199 MODULE_DEVICE_TABLE(of, v3d_of_match);
0200
0201 static int
0202 map_regs(struct v3d_dev *v3d, void __iomem **regs, const char *name)
0203 {
0204     *regs = devm_platform_ioremap_resource_byname(v3d_to_pdev(v3d), name);
0205     return PTR_ERR_OR_ZERO(*regs);
0206 }
0207
0208 static int v3d_platform_drm_probe(struct platform_device *pdev)
0209 {
0210     struct device *dev = &pdev->dev;
0211     struct drm_device *drm;
0212     struct v3d_dev *v3d;
0213     int ret;
0214     u32 mmu_debug;
0215     u32 ident1;
0216     u64 mask;
0217
0218     v3d = devm_drm_dev_alloc(dev, &v3d_drm_driver, struct v3d_dev, drm);
0219     if (IS_ERR(v3d))
0220         return PTR_ERR(v3d);
0221
0222     drm = &v3d->drm;
0223
0224     platform_set_drvdata(pdev, drm);
0225
0226     ret = map_regs(v3d, &v3d->hub_regs, "hub");
0227     if (ret)
0228         return ret;
0229
0230     ret = map_regs(v3d, &v3d->core_regs[0], "core0");
0231     if (ret)
0232         return ret;
0233
0234     mmu_debug = V3D_READ(V3D_MMU_DEBUG_INFO);
0235     mask = DMA_BIT_MASK(30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_PA_WIDTH));
0236     ret = dma_set_mask_and_coherent(dev, mask);
0237     if (ret)
0238         return ret;
0239
0240     v3d->va_width = 30 + V3D_GET_FIELD(mmu_debug, V3D_MMU_VA_WIDTH);
0241
0242     ident1 = V3D_READ(V3D_HUB_IDENT1);
0243     v3d->ver = (V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER) * 10 +
0244             V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV));
0245     v3d->cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
0246     WARN_ON(v3d->cores > 1); /* multicore not yet implemented */
0247
0248     v3d->reset = devm_reset_control_get_exclusive(dev, NULL);
0249     if (IS_ERR(v3d->reset)) {
0250         ret = PTR_ERR(v3d->reset);
0251
0252         if (ret == -EPROBE_DEFER)
0253             return ret;
0254
0255         v3d->reset = NULL;
0256         ret = map_regs(v3d, &v3d->bridge_regs, "bridge");
0257         if (ret) {
0258             dev_err(dev,
0259                 "Failed to get reset control or bridge regs\n");
0260             return ret;
0261         }
0262     }
0263
0264     if (v3d->ver < 41) {
0265         ret = map_regs(v3d, &v3d->gca_regs, "gca");
0266         if (ret)
0267             return ret;
0268     }
0269
0270     v3d->mmu_scratch = dma_alloc_wc(dev, 4096, &v3d->mmu_scratch_paddr,
0271                     GFP_KERNEL | __GFP_NOWARN | __GFP_ZERO);
0272     if (!v3d->mmu_scratch) {
0273         dev_err(dev, "Failed to allocate MMU scratch page\n");
0274         return -ENOMEM;
0275     }
0276
0277     ret = v3d_gem_init(drm);
0278     if (ret)
0279         goto dma_free;
0280
0281     ret = v3d_irq_init(v3d);
0282     if (ret)
0283         goto gem_destroy;
0284
0285     ret = drm_dev_register(drm, 0);
0286     if (ret)
0287         goto irq_disable;
0288
0289     return 0;
0290
0291 irq_disable:
0292     v3d_irq_disable(v3d);
0293 gem_destroy:
0294     v3d_gem_destroy(drm);
0295 dma_free:
0296     dma_free_wc(dev, 4096, v3d->mmu_scratch, v3d->mmu_scratch_paddr);
0297     return ret;
0298 }
0299
0300 static int v3d_platform_drm_remove(struct platform_device *pdev)
0301 {
0302     struct drm_device *drm = platform_get_drvdata(pdev);
0303     struct v3d_dev *v3d = to_v3d_dev(drm);
0304
0305     drm_dev_unregister(drm);
0306
0307     v3d_gem_destroy(drm);
0308
0309     dma_free_wc(v3d->drm.dev, 4096, v3d->mmu_scratch,
0310             v3d->mmu_scratch_paddr);
0311
0312     return 0;
0313 }
0314
0315 static struct platform_driver v3d_platform_driver = {
0316     .probe      = v3d_platform_drm_probe,
0317     .remove     = v3d_platform_drm_remove,
0318     .driver     = {
0319         .name   = "v3d",
0320         .of_match_table = v3d_of_match,
0321     },
0322 };
0323
0324 module_platform_driver(v3d_platform_driver);
0325
0326 MODULE_ALIAS("platform:v3d-drm");
0327 MODULE_DESCRIPTION("Broadcom V3D DRM Driver");
0328 MODULE_AUTHOR("Eric Anholt <eric@anholt.net>");
0329 MODULE_LICENSE("GPL v2");