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0002
0003
0004 #include <linux/circ_buf.h>
0005 #include <linux/ctype.h>
0006 #include <linux/debugfs.h>
0007 #include <linux/seq_file.h>
0008 #include <linux/string_helpers.h>
0009
0010 #include <drm/drm_debugfs.h>
0011
0012 #include "v3d_drv.h"
0013 #include "v3d_regs.h"
0014
0015 #define REGDEF(reg) { reg, #reg }
0016 struct v3d_reg_def {
0017 u32 reg;
0018 const char *name;
0019 };
0020
0021 static const struct v3d_reg_def v3d_hub_reg_defs[] = {
0022 REGDEF(V3D_HUB_AXICFG),
0023 REGDEF(V3D_HUB_UIFCFG),
0024 REGDEF(V3D_HUB_IDENT0),
0025 REGDEF(V3D_HUB_IDENT1),
0026 REGDEF(V3D_HUB_IDENT2),
0027 REGDEF(V3D_HUB_IDENT3),
0028 REGDEF(V3D_HUB_INT_STS),
0029 REGDEF(V3D_HUB_INT_MSK_STS),
0030
0031 REGDEF(V3D_MMU_CTL),
0032 REGDEF(V3D_MMU_VIO_ADDR),
0033 REGDEF(V3D_MMU_VIO_ID),
0034 REGDEF(V3D_MMU_DEBUG_INFO),
0035 };
0036
0037 static const struct v3d_reg_def v3d_gca_reg_defs[] = {
0038 REGDEF(V3D_GCA_SAFE_SHUTDOWN),
0039 REGDEF(V3D_GCA_SAFE_SHUTDOWN_ACK),
0040 };
0041
0042 static const struct v3d_reg_def v3d_core_reg_defs[] = {
0043 REGDEF(V3D_CTL_IDENT0),
0044 REGDEF(V3D_CTL_IDENT1),
0045 REGDEF(V3D_CTL_IDENT2),
0046 REGDEF(V3D_CTL_MISCCFG),
0047 REGDEF(V3D_CTL_INT_STS),
0048 REGDEF(V3D_CTL_INT_MSK_STS),
0049 REGDEF(V3D_CLE_CT0CS),
0050 REGDEF(V3D_CLE_CT0CA),
0051 REGDEF(V3D_CLE_CT0EA),
0052 REGDEF(V3D_CLE_CT1CS),
0053 REGDEF(V3D_CLE_CT1CA),
0054 REGDEF(V3D_CLE_CT1EA),
0055
0056 REGDEF(V3D_PTB_BPCA),
0057 REGDEF(V3D_PTB_BPCS),
0058
0059 REGDEF(V3D_GMP_STATUS),
0060 REGDEF(V3D_GMP_CFG),
0061 REGDEF(V3D_GMP_VIO_ADDR),
0062
0063 REGDEF(V3D_ERR_FDBGO),
0064 REGDEF(V3D_ERR_FDBGB),
0065 REGDEF(V3D_ERR_FDBGS),
0066 REGDEF(V3D_ERR_STAT),
0067 };
0068
0069 static const struct v3d_reg_def v3d_csd_reg_defs[] = {
0070 REGDEF(V3D_CSD_STATUS),
0071 REGDEF(V3D_CSD_CURRENT_CFG0),
0072 REGDEF(V3D_CSD_CURRENT_CFG1),
0073 REGDEF(V3D_CSD_CURRENT_CFG2),
0074 REGDEF(V3D_CSD_CURRENT_CFG3),
0075 REGDEF(V3D_CSD_CURRENT_CFG4),
0076 REGDEF(V3D_CSD_CURRENT_CFG5),
0077 REGDEF(V3D_CSD_CURRENT_CFG6),
0078 };
0079
0080 static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused)
0081 {
0082 struct drm_info_node *node = (struct drm_info_node *)m->private;
0083 struct drm_device *dev = node->minor->dev;
0084 struct v3d_dev *v3d = to_v3d_dev(dev);
0085 int i, core;
0086
0087 for (i = 0; i < ARRAY_SIZE(v3d_hub_reg_defs); i++) {
0088 seq_printf(m, "%s (0x%04x): 0x%08x\n",
0089 v3d_hub_reg_defs[i].name, v3d_hub_reg_defs[i].reg,
0090 V3D_READ(v3d_hub_reg_defs[i].reg));
0091 }
0092
0093 if (v3d->ver < 41) {
0094 for (i = 0; i < ARRAY_SIZE(v3d_gca_reg_defs); i++) {
0095 seq_printf(m, "%s (0x%04x): 0x%08x\n",
0096 v3d_gca_reg_defs[i].name,
0097 v3d_gca_reg_defs[i].reg,
0098 V3D_GCA_READ(v3d_gca_reg_defs[i].reg));
0099 }
0100 }
0101
0102 for (core = 0; core < v3d->cores; core++) {
0103 for (i = 0; i < ARRAY_SIZE(v3d_core_reg_defs); i++) {
0104 seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
0105 core,
0106 v3d_core_reg_defs[i].name,
0107 v3d_core_reg_defs[i].reg,
0108 V3D_CORE_READ(core,
0109 v3d_core_reg_defs[i].reg));
0110 }
0111
0112 if (v3d_has_csd(v3d)) {
0113 for (i = 0; i < ARRAY_SIZE(v3d_csd_reg_defs); i++) {
0114 seq_printf(m, "core %d %s (0x%04x): 0x%08x\n",
0115 core,
0116 v3d_csd_reg_defs[i].name,
0117 v3d_csd_reg_defs[i].reg,
0118 V3D_CORE_READ(core,
0119 v3d_csd_reg_defs[i].reg));
0120 }
0121 }
0122 }
0123
0124 return 0;
0125 }
0126
0127 static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused)
0128 {
0129 struct drm_info_node *node = (struct drm_info_node *)m->private;
0130 struct drm_device *dev = node->minor->dev;
0131 struct v3d_dev *v3d = to_v3d_dev(dev);
0132 u32 ident0, ident1, ident2, ident3, cores;
0133 int core;
0134
0135 ident0 = V3D_READ(V3D_HUB_IDENT0);
0136 ident1 = V3D_READ(V3D_HUB_IDENT1);
0137 ident2 = V3D_READ(V3D_HUB_IDENT2);
0138 ident3 = V3D_READ(V3D_HUB_IDENT3);
0139 cores = V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_NCORES);
0140
0141 seq_printf(m, "Revision: %d.%d.%d.%d\n",
0142 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_TVER),
0143 V3D_GET_FIELD(ident1, V3D_HUB_IDENT1_REV),
0144 V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPREV),
0145 V3D_GET_FIELD(ident3, V3D_HUB_IDENT3_IPIDX));
0146 seq_printf(m, "MMU: %s\n",
0147 str_yes_no(ident2 & V3D_HUB_IDENT2_WITH_MMU));
0148 seq_printf(m, "TFU: %s\n",
0149 str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TFU));
0150 seq_printf(m, "TSY: %s\n",
0151 str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TSY));
0152 seq_printf(m, "MSO: %s\n",
0153 str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_MSO));
0154 seq_printf(m, "L3C: %s (%dkb)\n",
0155 str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_L3C),
0156 V3D_GET_FIELD(ident2, V3D_HUB_IDENT2_L3C_NKB));
0157
0158 for (core = 0; core < cores; core++) {
0159 u32 misccfg;
0160 u32 nslc, ntmu, qups;
0161
0162 ident0 = V3D_CORE_READ(core, V3D_CTL_IDENT0);
0163 ident1 = V3D_CORE_READ(core, V3D_CTL_IDENT1);
0164 ident2 = V3D_CORE_READ(core, V3D_CTL_IDENT2);
0165 misccfg = V3D_CORE_READ(core, V3D_CTL_MISCCFG);
0166
0167 nslc = V3D_GET_FIELD(ident1, V3D_IDENT1_NSLC);
0168 ntmu = V3D_GET_FIELD(ident1, V3D_IDENT1_NTMU);
0169 qups = V3D_GET_FIELD(ident1, V3D_IDENT1_QUPS);
0170
0171 seq_printf(m, "Core %d:\n", core);
0172 seq_printf(m, " Revision: %d.%d\n",
0173 V3D_GET_FIELD(ident0, V3D_IDENT0_VER),
0174 V3D_GET_FIELD(ident1, V3D_IDENT1_REV));
0175 seq_printf(m, " Slices: %d\n", nslc);
0176 seq_printf(m, " TMUs: %d\n", nslc * ntmu);
0177 seq_printf(m, " QPUs: %d\n", nslc * qups);
0178 seq_printf(m, " Semaphores: %d\n",
0179 V3D_GET_FIELD(ident1, V3D_IDENT1_NSEM));
0180 seq_printf(m, " BCG int: %d\n",
0181 (ident2 & V3D_IDENT2_BCG_INT) != 0);
0182 seq_printf(m, " Override TMU: %d\n",
0183 (misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);
0184 }
0185
0186 return 0;
0187 }
0188
0189 static int v3d_debugfs_bo_stats(struct seq_file *m, void *unused)
0190 {
0191 struct drm_info_node *node = (struct drm_info_node *)m->private;
0192 struct drm_device *dev = node->minor->dev;
0193 struct v3d_dev *v3d = to_v3d_dev(dev);
0194
0195 mutex_lock(&v3d->bo_lock);
0196 seq_printf(m, "allocated bos: %d\n",
0197 v3d->bo_stats.num_allocated);
0198 seq_printf(m, "allocated bo size (kb): %ld\n",
0199 (long)v3d->bo_stats.pages_allocated << (PAGE_SHIFT - 10));
0200 mutex_unlock(&v3d->bo_lock);
0201
0202 return 0;
0203 }
0204
0205 static int v3d_measure_clock(struct seq_file *m, void *unused)
0206 {
0207 struct drm_info_node *node = (struct drm_info_node *)m->private;
0208 struct drm_device *dev = node->minor->dev;
0209 struct v3d_dev *v3d = to_v3d_dev(dev);
0210 uint32_t cycles;
0211 int core = 0;
0212 int measure_ms = 1000;
0213
0214 if (v3d->ver >= 40) {
0215 V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3,
0216 V3D_SET_FIELD(V3D_PCTR_CYCLE_COUNT,
0217 V3D_PCTR_S0));
0218 V3D_CORE_WRITE(core, V3D_V4_PCTR_0_CLR, 1);
0219 V3D_CORE_WRITE(core, V3D_V4_PCTR_0_EN, 1);
0220 } else {
0221 V3D_CORE_WRITE(core, V3D_V3_PCTR_0_PCTRS0,
0222 V3D_PCTR_CYCLE_COUNT);
0223 V3D_CORE_WRITE(core, V3D_V3_PCTR_0_CLR, 1);
0224 V3D_CORE_WRITE(core, V3D_V3_PCTR_0_EN,
0225 V3D_V3_PCTR_0_EN_ENABLE |
0226 1);
0227 }
0228 msleep(measure_ms);
0229 cycles = V3D_CORE_READ(core, V3D_PCTR_0_PCTR0);
0230
0231 seq_printf(m, "cycles: %d (%d.%d Mhz)\n",
0232 cycles,
0233 cycles / (measure_ms * 1000),
0234 (cycles / (measure_ms * 100)) % 10);
0235
0236 return 0;
0237 }
0238
0239 static const struct drm_info_list v3d_debugfs_list[] = {
0240 {"v3d_ident", v3d_v3d_debugfs_ident, 0},
0241 {"v3d_regs", v3d_v3d_debugfs_regs, 0},
0242 {"measure_clock", v3d_measure_clock, 0},
0243 {"bo_stats", v3d_debugfs_bo_stats, 0},
0244 };
0245
0246 void
0247 v3d_debugfs_init(struct drm_minor *minor)
0248 {
0249 drm_debugfs_create_files(v3d_debugfs_list,
0250 ARRAY_SIZE(v3d_debugfs_list),
0251 minor->debugfs_root, minor);
0252 }
