drm/tve200/tve200_drm.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2017 Linus Walleij <linus.walleij@linaro.org>
0004  * Parts of this file were based on sources as follows:
0005  *
0006  * Copyright (C) 2006-2008 Intel Corporation
0007  * Copyright (C) 2007 Amos Lee <amos_lee@storlinksemi.com>
0008  * Copyright (C) 2007 Dave Airlie <airlied@linux.ie>
0009  * Copyright (C) 2011 Texas Instruments
0010  * Copyright (C) 2017 Eric Anholt
0011  */
0012
0013 #ifndef _TVE200_DRM_H_
0014 #define _TVE200_DRM_H_
0015
0016 #include <linux/irqreturn.h>
0017
0018 #include <drm/drm_simple_kms_helper.h>
0019
0020 struct clk;
0021 struct drm_bridge;
0022 struct drm_connector;
0023 struct drm_device;
0024 struct drm_file;
0025 struct drm_mode_create_dumb;
0026 struct drm_panel;
0027
0028 /* Bits 2-31 are valid physical base addresses */
0029 #define TVE200_Y_FRAME_BASE_ADDR    0x00
0030 #define TVE200_U_FRAME_BASE_ADDR    0x04
0031 #define TVE200_V_FRAME_BASE_ADDR    0x08
0032
0033 #define TVE200_INT_EN           0x0C
0034 #define TVE200_INT_CLR          0x10
0035 #define TVE200_INT_STAT         0x14
0036 #define TVE200_INT_BUS_ERR      BIT(7)
0037 #define TVE200_INT_V_STATUS     BIT(6) /* vertical blank */
0038 #define TVE200_INT_V_NEXT_FRAME     BIT(5)
0039 #define TVE200_INT_U_NEXT_FRAME     BIT(4)
0040 #define TVE200_INT_Y_NEXT_FRAME     BIT(3)
0041 #define TVE200_INT_V_FIFO_UNDERRUN  BIT(2)
0042 #define TVE200_INT_U_FIFO_UNDERRUN  BIT(1)
0043 #define TVE200_INT_Y_FIFO_UNDERRUN  BIT(0)
0044 #define TVE200_FIFO_UNDERRUNS       (TVE200_INT_V_FIFO_UNDERRUN | \
0045                      TVE200_INT_U_FIFO_UNDERRUN | \
0046                      TVE200_INT_Y_FIFO_UNDERRUN)
0047
0048 #define TVE200_CTRL         0x18
0049 #define TVE200_CTRL_YUV420      BIT(31)
0050 #define TVE200_CTRL_CSMODE      BIT(30)
0051 #define TVE200_CTRL_NONINTERLACE    BIT(28) /* 0 = non-interlace CCIR656 */
0052 #define TVE200_CTRL_TVCLKP      BIT(27) /* Inverted clock phase */
0053 /* Bits 24..26 define the burst size after arbitration on the bus */
0054 #define TVE200_CTRL_BURST_4_WORDS   (0 << 24)
0055 #define TVE200_CTRL_BURST_8_WORDS   (1 << 24)
0056 #define TVE200_CTRL_BURST_16_WORDS  (2 << 24)
0057 #define TVE200_CTRL_BURST_32_WORDS  (3 << 24)
0058 #define TVE200_CTRL_BURST_64_WORDS  (4 << 24)
0059 #define TVE200_CTRL_BURST_128_WORDS (5 << 24)
0060 #define TVE200_CTRL_BURST_256_WORDS (6 << 24)
0061 #define TVE200_CTRL_BURST_0_WORDS   (7 << 24) /* ? */
0062 /*
0063  * Bits 16..23 is the retry count*16 before issueing a new AHB transfer
0064  * on the AHB bus.
0065  */
0066 #define TVE200_CTRL_RETRYCNT_MASK   GENMASK(23, 16)
0067 #define TVE200_CTRL_RETRYCNT_16     (1 << 16)
0068 #define TVE200_CTRL_BBBP        BIT(15) /* 0 = little-endian */
0069 /* Bits 12..14 define the YCbCr ordering */
0070 #define TVE200_CTRL_YCBCRODR_CB0Y0CR0Y1 (0 << 12)
0071 #define TVE200_CTRL_YCBCRODR_Y0CB0Y1CR0 (1 << 12)
0072 #define TVE200_CTRL_YCBCRODR_CR0Y0CB0Y1 (2 << 12)
0073 #define TVE200_CTRL_YCBCRODR_Y1CB0Y0CR0 (3 << 12)
0074 #define TVE200_CTRL_YCBCRODR_CR0Y1CB0Y0 (4 << 12)
0075 #define TVE200_CTRL_YCBCRODR_Y1CR0Y0CB0 (5 << 12)
0076 #define TVE200_CTRL_YCBCRODR_CB0Y1CR0Y0 (6 << 12)
0077 #define TVE200_CTRL_YCBCRODR_Y0CR0Y1CB0 (7 << 12)
0078 /* Bits 10..11 define the input resolution (framebuffer size) */
0079 #define TVE200_CTRL_IPRESOL_CIF     (0 << 10)
0080 #define TVE200_CTRL_IPRESOL_VGA     (1 << 10)
0081 #define TVE200_CTRL_IPRESOL_D1      (2 << 10)
0082 #define TVE200_CTRL_NTSC        BIT(9) /* 0 = PAL, 1 = NTSC */
0083 #define TVE200_CTRL_INTERLACE       BIT(8) /* 1 = interlace, only for D1 */
0084 #define TVE200_IPDMOD_RGB555        (0 << 6) /* TVE200_CTRL_YUV420 = 0 */
0085 #define TVE200_IPDMOD_RGB565        (1 << 6)
0086 #define TVE200_IPDMOD_RGB888        (2 << 6)
0087 #define TVE200_IPDMOD_YUV420        (2 << 6) /* TVE200_CTRL_YUV420 = 1 */
0088 #define TVE200_IPDMOD_YUV422        (3 << 6)
0089 /* Bits 4 & 5 define when to fire the vblank IRQ */
0090 #define TVE200_VSTSTYPE_VSYNC       (0 << 4) /* start of vsync */
0091 #define TVE200_VSTSTYPE_VBP     (1 << 4) /* start of v back porch */
0092 #define TVE200_VSTSTYPE_VAI     (2 << 4) /* start of v active image */
0093 #define TVE200_VSTSTYPE_VFP     (3 << 4) /* start of v front porch */
0094 #define TVE200_VSTSTYPE_BITS        (BIT(4) | BIT(5))
0095 #define TVE200_BGR          BIT(1) /* 0 = RGB, 1 = BGR */
0096 #define TVE200_TVEEN            BIT(0) /* Enable TVE block */
0097
0098 #define TVE200_CTRL_2           0x1c
0099 #define TVE200_CTRL_3           0x20
0100
0101 #define TVE200_CTRL_4           0x24
0102 #define TVE200_CTRL_4_RESET     BIT(0) /* triggers reset of TVE200 */
0103
0104 struct tve200_drm_dev_private {
0105     struct drm_device *drm;
0106
0107     struct drm_connector *connector;
0108     struct drm_panel *panel;
0109     struct drm_bridge *bridge;
0110     struct drm_simple_display_pipe pipe;
0111
0112     void *regs;
0113     struct clk *pclk;
0114     struct clk *clk;
0115 };
0116
0117 #define to_tve200_connector(x) \
0118     container_of(x, struct tve200_drm_connector, connector)
0119
0120 int tve200_display_init(struct drm_device *dev);
0121 irqreturn_t tve200_irq(int irq, void *data);
0122 int tve200_connector_init(struct drm_device *dev);
0123 int tve200_encoder_init(struct drm_device *dev);
0124 int tve200_dumb_create(struct drm_file *file_priv,
0125               struct drm_device *dev,
0126               struct drm_mode_create_dumb *args);
0127
0128 #endif /* _TVE200_DRM_H_ */