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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 
0003 #include <linux/module.h>
0004 #include <linux/pci.h>
0005 
0006 #include <drm/drm_aperture.h>
0007 #include <drm/drm_atomic_helper.h>
0008 #include <drm/drm_drv.h>
0009 #include <drm/drm_edid.h>
0010 #include <drm/drm_fb_helper.h>
0011 #include <drm/drm_fourcc.h>
0012 #include <drm/drm_framebuffer.h>
0013 #include <drm/drm_gem_framebuffer_helper.h>
0014 #include <drm/drm_gem_vram_helper.h>
0015 #include <drm/drm_managed.h>
0016 #include <drm/drm_module.h>
0017 #include <drm/drm_probe_helper.h>
0018 #include <drm/drm_simple_kms_helper.h>
0019 
0020 #include <video/vga.h>
0021 
0022 /* ---------------------------------------------------------------------- */
0023 
0024 #define VBE_DISPI_IOPORT_INDEX           0x01CE
0025 #define VBE_DISPI_IOPORT_DATA            0x01CF
0026 
0027 #define VBE_DISPI_INDEX_ID               0x0
0028 #define VBE_DISPI_INDEX_XRES             0x1
0029 #define VBE_DISPI_INDEX_YRES             0x2
0030 #define VBE_DISPI_INDEX_BPP              0x3
0031 #define VBE_DISPI_INDEX_ENABLE           0x4
0032 #define VBE_DISPI_INDEX_BANK             0x5
0033 #define VBE_DISPI_INDEX_VIRT_WIDTH       0x6
0034 #define VBE_DISPI_INDEX_VIRT_HEIGHT      0x7
0035 #define VBE_DISPI_INDEX_X_OFFSET         0x8
0036 #define VBE_DISPI_INDEX_Y_OFFSET         0x9
0037 #define VBE_DISPI_INDEX_VIDEO_MEMORY_64K 0xa
0038 
0039 #define VBE_DISPI_ID0                    0xB0C0
0040 #define VBE_DISPI_ID1                    0xB0C1
0041 #define VBE_DISPI_ID2                    0xB0C2
0042 #define VBE_DISPI_ID3                    0xB0C3
0043 #define VBE_DISPI_ID4                    0xB0C4
0044 #define VBE_DISPI_ID5                    0xB0C5
0045 
0046 #define VBE_DISPI_DISABLED               0x00
0047 #define VBE_DISPI_ENABLED                0x01
0048 #define VBE_DISPI_GETCAPS                0x02
0049 #define VBE_DISPI_8BIT_DAC               0x20
0050 #define VBE_DISPI_LFB_ENABLED            0x40
0051 #define VBE_DISPI_NOCLEARMEM             0x80
0052 
0053 static int bochs_modeset = -1;
0054 static int defx = 1024;
0055 static int defy = 768;
0056 
0057 module_param_named(modeset, bochs_modeset, int, 0444);
0058 MODULE_PARM_DESC(modeset, "enable/disable kernel modesetting");
0059 
0060 module_param(defx, int, 0444);
0061 module_param(defy, int, 0444);
0062 MODULE_PARM_DESC(defx, "default x resolution");
0063 MODULE_PARM_DESC(defy, "default y resolution");
0064 
0065 /* ---------------------------------------------------------------------- */
0066 
0067 enum bochs_types {
0068     BOCHS_QEMU_STDVGA,
0069     BOCHS_SIMICS,
0070     BOCHS_UNKNOWN,
0071 };
0072 
0073 struct bochs_device {
0074     /* hw */
0075     void __iomem   *mmio;
0076     int            ioports;
0077     void __iomem   *fb_map;
0078     unsigned long  fb_base;
0079     unsigned long  fb_size;
0080     unsigned long  qext_size;
0081 
0082     /* mode */
0083     u16 xres;
0084     u16 yres;
0085     u16 yres_virtual;
0086     u32 stride;
0087     u32 bpp;
0088     struct edid *edid;
0089 
0090     /* drm */
0091     struct drm_device *dev;
0092     struct drm_simple_display_pipe pipe;
0093     struct drm_connector connector;
0094 };
0095 
0096 /* ---------------------------------------------------------------------- */
0097 
0098 static void bochs_vga_writeb(struct bochs_device *bochs, u16 ioport, u8 val)
0099 {
0100     if (WARN_ON(ioport < 0x3c0 || ioport > 0x3df))
0101         return;
0102 
0103     if (bochs->mmio) {
0104         int offset = ioport - 0x3c0 + 0x400;
0105 
0106         writeb(val, bochs->mmio + offset);
0107     } else {
0108         outb(val, ioport);
0109     }
0110 }
0111 
0112 static u8 bochs_vga_readb(struct bochs_device *bochs, u16 ioport)
0113 {
0114     if (WARN_ON(ioport < 0x3c0 || ioport > 0x3df))
0115         return 0xff;
0116 
0117     if (bochs->mmio) {
0118         int offset = ioport - 0x3c0 + 0x400;
0119 
0120         return readb(bochs->mmio + offset);
0121     } else {
0122         return inb(ioport);
0123     }
0124 }
0125 
0126 static u16 bochs_dispi_read(struct bochs_device *bochs, u16 reg)
0127 {
0128     u16 ret = 0;
0129 
0130     if (bochs->mmio) {
0131         int offset = 0x500 + (reg << 1);
0132 
0133         ret = readw(bochs->mmio + offset);
0134     } else {
0135         outw(reg, VBE_DISPI_IOPORT_INDEX);
0136         ret = inw(VBE_DISPI_IOPORT_DATA);
0137     }
0138     return ret;
0139 }
0140 
0141 static void bochs_dispi_write(struct bochs_device *bochs, u16 reg, u16 val)
0142 {
0143     if (bochs->mmio) {
0144         int offset = 0x500 + (reg << 1);
0145 
0146         writew(val, bochs->mmio + offset);
0147     } else {
0148         outw(reg, VBE_DISPI_IOPORT_INDEX);
0149         outw(val, VBE_DISPI_IOPORT_DATA);
0150     }
0151 }
0152 
0153 static void bochs_hw_set_big_endian(struct bochs_device *bochs)
0154 {
0155     if (bochs->qext_size < 8)
0156         return;
0157 
0158     writel(0xbebebebe, bochs->mmio + 0x604);
0159 }
0160 
0161 static void bochs_hw_set_little_endian(struct bochs_device *bochs)
0162 {
0163     if (bochs->qext_size < 8)
0164         return;
0165 
0166     writel(0x1e1e1e1e, bochs->mmio + 0x604);
0167 }
0168 
0169 #ifdef __BIG_ENDIAN
0170 #define bochs_hw_set_native_endian(_b) bochs_hw_set_big_endian(_b)
0171 #else
0172 #define bochs_hw_set_native_endian(_b) bochs_hw_set_little_endian(_b)
0173 #endif
0174 
0175 static int bochs_get_edid_block(void *data, u8 *buf,
0176                 unsigned int block, size_t len)
0177 {
0178     struct bochs_device *bochs = data;
0179     size_t i, start = block * EDID_LENGTH;
0180 
0181     if (start + len > 0x400 /* vga register offset */)
0182         return -1;
0183 
0184     for (i = 0; i < len; i++)
0185         buf[i] = readb(bochs->mmio + start + i);
0186 
0187     return 0;
0188 }
0189 
0190 static int bochs_hw_load_edid(struct bochs_device *bochs)
0191 {
0192     u8 header[8];
0193 
0194     if (!bochs->mmio)
0195         return -1;
0196 
0197     /* check header to detect whenever edid support is enabled in qemu */
0198     bochs_get_edid_block(bochs, header, 0, ARRAY_SIZE(header));
0199     if (drm_edid_header_is_valid(header) != 8)
0200         return -1;
0201 
0202     kfree(bochs->edid);
0203     bochs->edid = drm_do_get_edid(&bochs->connector,
0204                       bochs_get_edid_block, bochs);
0205     if (bochs->edid == NULL)
0206         return -1;
0207 
0208     return 0;
0209 }
0210 
0211 static int bochs_hw_init(struct drm_device *dev)
0212 {
0213     struct bochs_device *bochs = dev->dev_private;
0214     struct pci_dev *pdev = to_pci_dev(dev->dev);
0215     unsigned long addr, size, mem, ioaddr, iosize;
0216     u16 id;
0217 
0218     if (pdev->resource[2].flags & IORESOURCE_MEM) {
0219         /* mmio bar with vga and bochs registers present */
0220         if (pci_request_region(pdev, 2, "bochs-drm") != 0) {
0221             DRM_ERROR("Cannot request mmio region\n");
0222             return -EBUSY;
0223         }
0224         ioaddr = pci_resource_start(pdev, 2);
0225         iosize = pci_resource_len(pdev, 2);
0226         bochs->mmio = ioremap(ioaddr, iosize);
0227         if (bochs->mmio == NULL) {
0228             DRM_ERROR("Cannot map mmio region\n");
0229             return -ENOMEM;
0230         }
0231     } else {
0232         ioaddr = VBE_DISPI_IOPORT_INDEX;
0233         iosize = 2;
0234         if (!request_region(ioaddr, iosize, "bochs-drm")) {
0235             DRM_ERROR("Cannot request ioports\n");
0236             return -EBUSY;
0237         }
0238         bochs->ioports = 1;
0239     }
0240 
0241     id = bochs_dispi_read(bochs, VBE_DISPI_INDEX_ID);
0242     mem = bochs_dispi_read(bochs, VBE_DISPI_INDEX_VIDEO_MEMORY_64K)
0243         * 64 * 1024;
0244     if ((id & 0xfff0) != VBE_DISPI_ID0) {
0245         DRM_ERROR("ID mismatch\n");
0246         return -ENODEV;
0247     }
0248 
0249     if ((pdev->resource[0].flags & IORESOURCE_MEM) == 0)
0250         return -ENODEV;
0251     addr = pci_resource_start(pdev, 0);
0252     size = pci_resource_len(pdev, 0);
0253     if (addr == 0)
0254         return -ENODEV;
0255     if (size != mem) {
0256         DRM_ERROR("Size mismatch: pci=%ld, bochs=%ld\n",
0257             size, mem);
0258         size = min(size, mem);
0259     }
0260 
0261     if (pci_request_region(pdev, 0, "bochs-drm") != 0)
0262         DRM_WARN("Cannot request framebuffer, boot fb still active?\n");
0263 
0264     bochs->fb_map = ioremap(addr, size);
0265     if (bochs->fb_map == NULL) {
0266         DRM_ERROR("Cannot map framebuffer\n");
0267         return -ENOMEM;
0268     }
0269     bochs->fb_base = addr;
0270     bochs->fb_size = size;
0271 
0272     DRM_INFO("Found bochs VGA, ID 0x%x.\n", id);
0273     DRM_INFO("Framebuffer size %ld kB @ 0x%lx, %s @ 0x%lx.\n",
0274          size / 1024, addr,
0275          bochs->ioports ? "ioports" : "mmio",
0276          ioaddr);
0277 
0278     if (bochs->mmio && pdev->revision >= 2) {
0279         bochs->qext_size = readl(bochs->mmio + 0x600);
0280         if (bochs->qext_size < 4 || bochs->qext_size > iosize) {
0281             bochs->qext_size = 0;
0282             goto noext;
0283         }
0284         DRM_DEBUG("Found qemu ext regs, size %ld\n",
0285               bochs->qext_size);
0286         bochs_hw_set_native_endian(bochs);
0287     }
0288 
0289 noext:
0290     return 0;
0291 }
0292 
0293 static void bochs_hw_fini(struct drm_device *dev)
0294 {
0295     struct bochs_device *bochs = dev->dev_private;
0296 
0297     /* TODO: shot down existing vram mappings */
0298 
0299     if (bochs->mmio)
0300         iounmap(bochs->mmio);
0301     if (bochs->ioports)
0302         release_region(VBE_DISPI_IOPORT_INDEX, 2);
0303     if (bochs->fb_map)
0304         iounmap(bochs->fb_map);
0305     pci_release_regions(to_pci_dev(dev->dev));
0306     kfree(bochs->edid);
0307 }
0308 
0309 static void bochs_hw_blank(struct bochs_device *bochs, bool blank)
0310 {
0311     DRM_DEBUG_DRIVER("hw_blank %d\n", blank);
0312     /* discard ar_flip_flop */
0313     (void)bochs_vga_readb(bochs, VGA_IS1_RC);
0314     /* blank or unblank; we need only update index and set 0x20 */
0315     bochs_vga_writeb(bochs, VGA_ATT_W, blank ? 0 : 0x20);
0316 }
0317 
0318 static void bochs_hw_setmode(struct bochs_device *bochs, struct drm_display_mode *mode)
0319 {
0320     int idx;
0321 
0322     if (!drm_dev_enter(bochs->dev, &idx))
0323         return;
0324 
0325     bochs->xres = mode->hdisplay;
0326     bochs->yres = mode->vdisplay;
0327     bochs->bpp = 32;
0328     bochs->stride = mode->hdisplay * (bochs->bpp / 8);
0329     bochs->yres_virtual = bochs->fb_size / bochs->stride;
0330 
0331     DRM_DEBUG_DRIVER("%dx%d @ %d bpp, vy %d\n",
0332              bochs->xres, bochs->yres, bochs->bpp,
0333              bochs->yres_virtual);
0334 
0335     bochs_hw_blank(bochs, false);
0336 
0337     bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE,      0);
0338     bochs_dispi_write(bochs, VBE_DISPI_INDEX_BPP,         bochs->bpp);
0339     bochs_dispi_write(bochs, VBE_DISPI_INDEX_XRES,        bochs->xres);
0340     bochs_dispi_write(bochs, VBE_DISPI_INDEX_YRES,        bochs->yres);
0341     bochs_dispi_write(bochs, VBE_DISPI_INDEX_BANK,        0);
0342     bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH,  bochs->xres);
0343     bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_HEIGHT,
0344               bochs->yres_virtual);
0345     bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET,    0);
0346     bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET,    0);
0347 
0348     bochs_dispi_write(bochs, VBE_DISPI_INDEX_ENABLE,
0349               VBE_DISPI_ENABLED | VBE_DISPI_LFB_ENABLED);
0350 
0351     drm_dev_exit(idx);
0352 }
0353 
0354 static void bochs_hw_setformat(struct bochs_device *bochs, const struct drm_format_info *format)
0355 {
0356     int idx;
0357 
0358     if (!drm_dev_enter(bochs->dev, &idx))
0359         return;
0360 
0361     DRM_DEBUG_DRIVER("format %c%c%c%c\n",
0362              (format->format >>  0) & 0xff,
0363              (format->format >>  8) & 0xff,
0364              (format->format >> 16) & 0xff,
0365              (format->format >> 24) & 0xff);
0366 
0367     switch (format->format) {
0368     case DRM_FORMAT_XRGB8888:
0369         bochs_hw_set_little_endian(bochs);
0370         break;
0371     case DRM_FORMAT_BGRX8888:
0372         bochs_hw_set_big_endian(bochs);
0373         break;
0374     default:
0375         /* should not happen */
0376         DRM_ERROR("%s: Huh? Got framebuffer format 0x%x",
0377               __func__, format->format);
0378         break;
0379     }
0380 
0381     drm_dev_exit(idx);
0382 }
0383 
0384 static void bochs_hw_setbase(struct bochs_device *bochs, int x, int y, int stride, u64 addr)
0385 {
0386     unsigned long offset;
0387     unsigned int vx, vy, vwidth, idx;
0388 
0389     if (!drm_dev_enter(bochs->dev, &idx))
0390         return;
0391 
0392     bochs->stride = stride;
0393     offset = (unsigned long)addr +
0394         y * bochs->stride +
0395         x * (bochs->bpp / 8);
0396     vy = offset / bochs->stride;
0397     vx = (offset % bochs->stride) * 8 / bochs->bpp;
0398     vwidth = stride * 8 / bochs->bpp;
0399 
0400     DRM_DEBUG_DRIVER("x %d, y %d, addr %llx -> offset %lx, vx %d, vy %d\n",
0401              x, y, addr, offset, vx, vy);
0402     bochs_dispi_write(bochs, VBE_DISPI_INDEX_VIRT_WIDTH, vwidth);
0403     bochs_dispi_write(bochs, VBE_DISPI_INDEX_X_OFFSET, vx);
0404     bochs_dispi_write(bochs, VBE_DISPI_INDEX_Y_OFFSET, vy);
0405 
0406     drm_dev_exit(idx);
0407 }
0408 
0409 /* ---------------------------------------------------------------------- */
0410 
0411 static const uint32_t bochs_formats[] = {
0412     DRM_FORMAT_XRGB8888,
0413     DRM_FORMAT_BGRX8888,
0414 };
0415 
0416 static void bochs_plane_update(struct bochs_device *bochs, struct drm_plane_state *state)
0417 {
0418     struct drm_gem_vram_object *gbo;
0419     s64 gpu_addr;
0420 
0421     if (!state->fb || !bochs->stride)
0422         return;
0423 
0424     gbo = drm_gem_vram_of_gem(state->fb->obj[0]);
0425     gpu_addr = drm_gem_vram_offset(gbo);
0426     if (WARN_ON_ONCE(gpu_addr < 0))
0427         return; /* Bug: we didn't pin the BO to VRAM in prepare_fb. */
0428 
0429     bochs_hw_setbase(bochs,
0430              state->crtc_x,
0431              state->crtc_y,
0432              state->fb->pitches[0],
0433              state->fb->offsets[0] + gpu_addr);
0434     bochs_hw_setformat(bochs, state->fb->format);
0435 }
0436 
0437 static void bochs_pipe_enable(struct drm_simple_display_pipe *pipe,
0438                   struct drm_crtc_state *crtc_state,
0439                   struct drm_plane_state *plane_state)
0440 {
0441     struct bochs_device *bochs = pipe->crtc.dev->dev_private;
0442 
0443     bochs_hw_setmode(bochs, &crtc_state->mode);
0444     bochs_plane_update(bochs, plane_state);
0445 }
0446 
0447 static void bochs_pipe_disable(struct drm_simple_display_pipe *pipe)
0448 {
0449     struct bochs_device *bochs = pipe->crtc.dev->dev_private;
0450 
0451     bochs_hw_blank(bochs, true);
0452 }
0453 
0454 static void bochs_pipe_update(struct drm_simple_display_pipe *pipe,
0455                   struct drm_plane_state *old_state)
0456 {
0457     struct bochs_device *bochs = pipe->crtc.dev->dev_private;
0458 
0459     bochs_plane_update(bochs, pipe->plane.state);
0460 }
0461 
0462 static const struct drm_simple_display_pipe_funcs bochs_pipe_funcs = {
0463     .enable     = bochs_pipe_enable,
0464     .disable    = bochs_pipe_disable,
0465     .update     = bochs_pipe_update,
0466     .prepare_fb = drm_gem_vram_simple_display_pipe_prepare_fb,
0467     .cleanup_fb = drm_gem_vram_simple_display_pipe_cleanup_fb,
0468 };
0469 
0470 static int bochs_connector_get_modes(struct drm_connector *connector)
0471 {
0472     struct bochs_device *bochs =
0473         container_of(connector, struct bochs_device, connector);
0474     int count = 0;
0475 
0476     if (bochs->edid)
0477         count = drm_add_edid_modes(connector, bochs->edid);
0478 
0479     if (!count) {
0480         count = drm_add_modes_noedid(connector, 8192, 8192);
0481         drm_set_preferred_mode(connector, defx, defy);
0482     }
0483     return count;
0484 }
0485 
0486 static const struct drm_connector_helper_funcs bochs_connector_connector_helper_funcs = {
0487     .get_modes = bochs_connector_get_modes,
0488 };
0489 
0490 static const struct drm_connector_funcs bochs_connector_connector_funcs = {
0491     .fill_modes = drm_helper_probe_single_connector_modes,
0492     .destroy = drm_connector_cleanup,
0493     .reset = drm_atomic_helper_connector_reset,
0494     .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
0495     .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
0496 };
0497 
0498 static void bochs_connector_init(struct drm_device *dev)
0499 {
0500     struct bochs_device *bochs = dev->dev_private;
0501     struct drm_connector *connector = &bochs->connector;
0502 
0503     drm_connector_init(dev, connector, &bochs_connector_connector_funcs,
0504                DRM_MODE_CONNECTOR_VIRTUAL);
0505     drm_connector_helper_add(connector, &bochs_connector_connector_helper_funcs);
0506 
0507     bochs_hw_load_edid(bochs);
0508     if (bochs->edid) {
0509         DRM_INFO("Found EDID data blob.\n");
0510         drm_connector_attach_edid_property(connector);
0511         drm_connector_update_edid_property(connector, bochs->edid);
0512     }
0513 }
0514 
0515 static struct drm_framebuffer *
0516 bochs_gem_fb_create(struct drm_device *dev, struct drm_file *file,
0517             const struct drm_mode_fb_cmd2 *mode_cmd)
0518 {
0519     if (mode_cmd->pixel_format != DRM_FORMAT_XRGB8888 &&
0520         mode_cmd->pixel_format != DRM_FORMAT_BGRX8888)
0521         return ERR_PTR(-EINVAL);
0522 
0523     return drm_gem_fb_create(dev, file, mode_cmd);
0524 }
0525 
0526 static const struct drm_mode_config_funcs bochs_mode_funcs = {
0527     .fb_create = bochs_gem_fb_create,
0528     .mode_valid = drm_vram_helper_mode_valid,
0529     .atomic_check = drm_atomic_helper_check,
0530     .atomic_commit = drm_atomic_helper_commit,
0531 };
0532 
0533 static int bochs_kms_init(struct bochs_device *bochs)
0534 {
0535     int ret;
0536 
0537     ret = drmm_mode_config_init(bochs->dev);
0538     if (ret)
0539         return ret;
0540 
0541     bochs->dev->mode_config.max_width = 8192;
0542     bochs->dev->mode_config.max_height = 8192;
0543 
0544     bochs->dev->mode_config.fb_base = bochs->fb_base;
0545     bochs->dev->mode_config.preferred_depth = 24;
0546     bochs->dev->mode_config.prefer_shadow = 0;
0547     bochs->dev->mode_config.prefer_shadow_fbdev = 1;
0548     bochs->dev->mode_config.quirk_addfb_prefer_host_byte_order = true;
0549 
0550     bochs->dev->mode_config.funcs = &bochs_mode_funcs;
0551 
0552     bochs_connector_init(bochs->dev);
0553     drm_simple_display_pipe_init(bochs->dev,
0554                      &bochs->pipe,
0555                      &bochs_pipe_funcs,
0556                      bochs_formats,
0557                      ARRAY_SIZE(bochs_formats),
0558                      NULL,
0559                      &bochs->connector);
0560 
0561     drm_mode_config_reset(bochs->dev);
0562 
0563     return 0;
0564 }
0565 
0566 /* ---------------------------------------------------------------------- */
0567 /* drm interface                                                          */
0568 
0569 static int bochs_load(struct drm_device *dev)
0570 {
0571     struct bochs_device *bochs;
0572     int ret;
0573 
0574     bochs = drmm_kzalloc(dev, sizeof(*bochs), GFP_KERNEL);
0575     if (bochs == NULL)
0576         return -ENOMEM;
0577     dev->dev_private = bochs;
0578     bochs->dev = dev;
0579 
0580     ret = bochs_hw_init(dev);
0581     if (ret)
0582         return ret;
0583 
0584     ret = drmm_vram_helper_init(dev, bochs->fb_base, bochs->fb_size);
0585     if (ret)
0586         return ret;
0587 
0588     ret = bochs_kms_init(bochs);
0589     if (ret)
0590         return ret;
0591 
0592     return 0;
0593 }
0594 
0595 DEFINE_DRM_GEM_FOPS(bochs_fops);
0596 
0597 static const struct drm_driver bochs_driver = {
0598     .driver_features    = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
0599     .fops           = &bochs_fops,
0600     .name           = "bochs-drm",
0601     .desc           = "bochs dispi vga interface (qemu stdvga)",
0602     .date           = "20130925",
0603     .major          = 1,
0604     .minor          = 0,
0605     DRM_GEM_VRAM_DRIVER,
0606 };
0607 
0608 /* ---------------------------------------------------------------------- */
0609 /* pm interface                                                           */
0610 
0611 #ifdef CONFIG_PM_SLEEP
0612 static int bochs_pm_suspend(struct device *dev)
0613 {
0614     struct drm_device *drm_dev = dev_get_drvdata(dev);
0615 
0616     return drm_mode_config_helper_suspend(drm_dev);
0617 }
0618 
0619 static int bochs_pm_resume(struct device *dev)
0620 {
0621     struct drm_device *drm_dev = dev_get_drvdata(dev);
0622 
0623     return drm_mode_config_helper_resume(drm_dev);
0624 }
0625 #endif
0626 
0627 static const struct dev_pm_ops bochs_pm_ops = {
0628     SET_SYSTEM_SLEEP_PM_OPS(bochs_pm_suspend,
0629                 bochs_pm_resume)
0630 };
0631 
0632 /* ---------------------------------------------------------------------- */
0633 /* pci interface                                                          */
0634 
0635 static int bochs_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
0636 {
0637     struct drm_device *dev;
0638     unsigned long fbsize;
0639     int ret;
0640 
0641     fbsize = pci_resource_len(pdev, 0);
0642     if (fbsize < 4 * 1024 * 1024) {
0643         DRM_ERROR("less than 4 MB video memory, ignoring device\n");
0644         return -ENOMEM;
0645     }
0646 
0647     ret = drm_aperture_remove_conflicting_pci_framebuffers(pdev, &bochs_driver);
0648     if (ret)
0649         return ret;
0650 
0651     dev = drm_dev_alloc(&bochs_driver, &pdev->dev);
0652     if (IS_ERR(dev))
0653         return PTR_ERR(dev);
0654 
0655     ret = pcim_enable_device(pdev);
0656     if (ret)
0657         goto err_free_dev;
0658 
0659     pci_set_drvdata(pdev, dev);
0660 
0661     ret = bochs_load(dev);
0662     if (ret)
0663         goto err_free_dev;
0664 
0665     ret = drm_dev_register(dev, 0);
0666     if (ret)
0667         goto err_free_dev;
0668 
0669     drm_fbdev_generic_setup(dev, 32);
0670     return ret;
0671 
0672 err_free_dev:
0673     drm_dev_put(dev);
0674     return ret;
0675 }
0676 
0677 static void bochs_pci_remove(struct pci_dev *pdev)
0678 {
0679     struct drm_device *dev = pci_get_drvdata(pdev);
0680 
0681     drm_dev_unplug(dev);
0682     drm_atomic_helper_shutdown(dev);
0683     bochs_hw_fini(dev);
0684     drm_dev_put(dev);
0685 }
0686 
0687 static const struct pci_device_id bochs_pci_tbl[] = {
0688     {
0689         .vendor      = 0x1234,
0690         .device      = 0x1111,
0691         .subvendor   = PCI_SUBVENDOR_ID_REDHAT_QUMRANET,
0692         .subdevice   = PCI_SUBDEVICE_ID_QEMU,
0693         .driver_data = BOCHS_QEMU_STDVGA,
0694     },
0695     {
0696         .vendor      = 0x1234,
0697         .device      = 0x1111,
0698         .subvendor   = PCI_ANY_ID,
0699         .subdevice   = PCI_ANY_ID,
0700         .driver_data = BOCHS_UNKNOWN,
0701     },
0702     {
0703         .vendor      = 0x4321,
0704         .device      = 0x1111,
0705         .subvendor   = PCI_ANY_ID,
0706         .subdevice   = PCI_ANY_ID,
0707         .driver_data = BOCHS_SIMICS,
0708     },
0709     { /* end of list */ }
0710 };
0711 
0712 static struct pci_driver bochs_pci_driver = {
0713     .name =     "bochs-drm",
0714     .id_table = bochs_pci_tbl,
0715     .probe =    bochs_pci_probe,
0716     .remove =   bochs_pci_remove,
0717     .driver.pm =    &bochs_pm_ops,
0718 };
0719 
0720 /* ---------------------------------------------------------------------- */
0721 /* module init/exit                                                       */
0722 
0723 drm_module_pci_driver_if_modeset(bochs_pci_driver, bochs_modeset);
0724 
0725 MODULE_DEVICE_TABLE(pci, bochs_pci_tbl);
0726 MODULE_AUTHOR("Gerd Hoffmann <kraxel@redhat.com>");
0727 MODULE_LICENSE("GPL");
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