drm/tilcdc/tilcdc_regs.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2012 Texas Instruments
0004  * Author: Rob Clark <robdclark@gmail.com>
0005  */
0006
0007 #ifndef __TILCDC_REGS_H__
0008 #define __TILCDC_REGS_H__
0009
0010 /* LCDC register definitions, based on da8xx-fb */
0011
0012 #include <linux/bitops.h>
0013
0014 #include "tilcdc_drv.h"
0015
0016 /* LCDC Status Register */
0017 #define LCDC_END_OF_FRAME1                       BIT(9)
0018 #define LCDC_END_OF_FRAME0                       BIT(8)
0019 #define LCDC_PL_LOAD_DONE                        BIT(6)
0020 #define LCDC_FIFO_UNDERFLOW                      BIT(5)
0021 #define LCDC_SYNC_LOST                           BIT(2)
0022 #define LCDC_FRAME_DONE                          BIT(0)
0023
0024 /* LCDC DMA Control Register */
0025 #define LCDC_DMA_BURST_SIZE(x)                   ((x) << 4)
0026 #define LCDC_DMA_BURST_SIZE_MASK                 ((0x7) << 4)
0027 #define LCDC_DMA_BURST_1                         0x0
0028 #define LCDC_DMA_BURST_2                         0x1
0029 #define LCDC_DMA_BURST_4                         0x2
0030 #define LCDC_DMA_BURST_8                         0x3
0031 #define LCDC_DMA_BURST_16                        0x4
0032 #define LCDC_DMA_FIFO_THRESHOLD(x)               ((x) << 8)
0033 #define LCDC_DMA_FIFO_THRESHOLD_MASK             ((0x3) << 8)
0034 #define LCDC_V1_END_OF_FRAME_INT_ENA             BIT(2)
0035 #define LCDC_V2_END_OF_FRAME0_INT_ENA            BIT(8)
0036 #define LCDC_V2_END_OF_FRAME1_INT_ENA            BIT(9)
0037 #define LCDC_DUAL_FRAME_BUFFER_ENABLE            BIT(0)
0038
0039 /* LCDC Control Register */
0040 #define LCDC_CLK_DIVISOR(x)                      ((x) << 8)
0041 #define LCDC_CLK_DIVISOR_MASK                    ((0xFF) << 8)
0042 #define LCDC_RASTER_MODE                         0x01
0043
0044 /* LCDC Raster Control Register */
0045 #define LCDC_PALETTE_LOAD_MODE(x)                ((x) << 20)
0046 #define LCDC_PALETTE_LOAD_MODE_MASK              ((0x3) << 20)
0047 #define PALETTE_AND_DATA                         0x00
0048 #define PALETTE_ONLY                             0x01
0049 #define DATA_ONLY                                0x02
0050
0051 #define LCDC_MONO_8BIT_MODE                      BIT(9)
0052 #define LCDC_RASTER_ORDER                        BIT(8)
0053 #define LCDC_TFT_MODE                            BIT(7)
0054 #define LCDC_V1_UNDERFLOW_INT_ENA                BIT(6)
0055 #define LCDC_V2_UNDERFLOW_INT_ENA                BIT(5)
0056 #define LCDC_V1_PL_INT_ENA                       BIT(4)
0057 #define LCDC_V2_PL_INT_ENA                       BIT(6)
0058 #define LCDC_V1_SYNC_LOST_INT_ENA                BIT(5)
0059 #define LCDC_V1_FRAME_DONE_INT_ENA               BIT(3)
0060 #define LCDC_MONOCHROME_MODE                     BIT(1)
0061 #define LCDC_RASTER_ENABLE                       BIT(0)
0062 #define LCDC_TFT_ALT_ENABLE                      BIT(23)
0063 #define LCDC_STN_565_ENABLE                      BIT(24)
0064 #define LCDC_V2_DMA_CLK_EN                       BIT(2)
0065 #define LCDC_V2_LIDD_CLK_EN                      BIT(1)
0066 #define LCDC_V2_CORE_CLK_EN                      BIT(0)
0067 #define LCDC_V2_LPP_B10                          26
0068 #define LCDC_V2_TFT_24BPP_MODE                   BIT(25)
0069 #define LCDC_V2_TFT_24BPP_UNPACK                 BIT(26)
0070
0071 /* LCDC Raster Timing 2 Register */
0072 #define LCDC_AC_BIAS_TRANSITIONS_PER_INT(x)      ((x) << 16)
0073 #define LCDC_AC_BIAS_TRANSITIONS_PER_INT_MASK    ((0xF) << 16)
0074 #define LCDC_AC_BIAS_FREQUENCY(x)                ((x) << 8)
0075 #define LCDC_AC_BIAS_FREQUENCY_MASK              ((0xFF) << 8)
0076 #define LCDC_SYNC_CTRL                           BIT(25)
0077 #define LCDC_SYNC_EDGE                           BIT(24)
0078 #define LCDC_INVERT_PIXEL_CLOCK                  BIT(22)
0079 #define LCDC_INVERT_HSYNC                        BIT(21)
0080 #define LCDC_INVERT_VSYNC                        BIT(20)
0081 #define LCDC_LPP_B10                             BIT(26)
0082
0083 /* LCDC Block */
0084 #define LCDC_PID_REG                             0x0
0085 #define LCDC_CTRL_REG                            0x4
0086 #define LCDC_STAT_REG                            0x8
0087 #define LCDC_RASTER_CTRL_REG                     0x28
0088 #define LCDC_RASTER_TIMING_0_REG                 0x2c
0089 #define LCDC_RASTER_TIMING_1_REG                 0x30
0090 #define LCDC_RASTER_TIMING_2_REG                 0x34
0091 #define LCDC_DMA_CTRL_REG                        0x40
0092 #define LCDC_DMA_FB_BASE_ADDR_0_REG              0x44
0093 #define LCDC_DMA_FB_CEILING_ADDR_0_REG           0x48
0094 #define LCDC_DMA_FB_BASE_ADDR_1_REG              0x4c
0095 #define LCDC_DMA_FB_CEILING_ADDR_1_REG           0x50
0096
0097 /* Interrupt Registers available only in Version 2 */
0098 #define LCDC_RAW_STAT_REG                        0x58
0099 #define LCDC_MASKED_STAT_REG                     0x5c
0100 #define LCDC_INT_ENABLE_SET_REG                  0x60
0101 #define LCDC_INT_ENABLE_CLR_REG                  0x64
0102 #define LCDC_END_OF_INT_IND_REG                  0x68
0103
0104 /* Clock registers available only on Version 2 */
0105 #define LCDC_CLK_ENABLE_REG                      0x6c
0106 #define LCDC_CLK_RESET_REG                       0x70
0107 #define LCDC_CLK_MAIN_RESET                      BIT(3)
0108
0109
0110 /*
0111  * Helpers:
0112  */
0113
0114 static inline void tilcdc_write(struct drm_device *dev, u32 reg, u32 data)
0115 {
0116     struct tilcdc_drm_private *priv = dev->dev_private;
0117     iowrite32(data, priv->mmio + reg);
0118 }
0119
0120 static inline void tilcdc_write64(struct drm_device *dev, u32 reg, u64 data)
0121 {
0122     struct tilcdc_drm_private *priv = dev->dev_private;
0123     volatile void __iomem *addr = priv->mmio + reg;
0124
0125 #if defined(iowrite64) && !defined(iowrite64_is_nonatomic)
0126     iowrite64(data, addr);
0127 #else
0128     __iowmb();
0129     /* This compiles to strd (=64-bit write) on ARM7 */
0130     *(volatile u64 __force *)addr = __cpu_to_le64(data);
0131 #endif
0132 }
0133
0134 static inline u32 tilcdc_read(struct drm_device *dev, u32 reg)
0135 {
0136     struct tilcdc_drm_private *priv = dev->dev_private;
0137     return ioread32(priv->mmio + reg);
0138 }
0139
0140 static inline void tilcdc_write_mask(struct drm_device *dev, u32 reg,
0141                      u32 val, u32 mask)
0142 {
0143     tilcdc_write(dev, reg, (tilcdc_read(dev, reg) & ~mask) | (val & mask));
0144 }
0145
0146 static inline void tilcdc_set(struct drm_device *dev, u32 reg, u32 mask)
0147 {
0148     tilcdc_write(dev, reg, tilcdc_read(dev, reg) | mask);
0149 }
0150
0151 static inline void tilcdc_clear(struct drm_device *dev, u32 reg, u32 mask)
0152 {
0153     tilcdc_write(dev, reg, tilcdc_read(dev, reg) & ~mask);
0154 }
0155
0156 /* the register to read/clear irqstatus differs between v1 and v2 of the IP */
0157 static inline u32 tilcdc_irqstatus_reg(struct drm_device *dev)
0158 {
0159     struct tilcdc_drm_private *priv = dev->dev_private;
0160     return (priv->rev == 2) ? LCDC_MASKED_STAT_REG : LCDC_STAT_REG;
0161 }
0162
0163 static inline u32 tilcdc_read_irqstatus(struct drm_device *dev)
0164 {
0165     return tilcdc_read(dev, tilcdc_irqstatus_reg(dev));
0166 }
0167
0168 static inline void tilcdc_clear_irqstatus(struct drm_device *dev, u32 mask)
0169 {
0170     tilcdc_write(dev, tilcdc_irqstatus_reg(dev), mask);
0171 }
0172
0173 #endif /* __TILCDC_REGS_H__ */