drm/tilcdc/tilcdc_drv.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2012 Texas Instruments
0004  * Author: Rob Clark <robdclark@gmail.com>
0005  */
0006
0007 #ifndef __TILCDC_DRV_H__
0008 #define __TILCDC_DRV_H__
0009
0010 #include <linux/cpufreq.h>
0011 #include <linux/irqreturn.h>
0012
0013 #include <drm/drm_print.h>
0014
0015 struct clk;
0016 struct workqueue_struct;
0017
0018 struct drm_connector;
0019 struct drm_connector_helper_funcs;
0020 struct drm_crtc;
0021 struct drm_device;
0022 struct drm_display_mode;
0023 struct drm_encoder;
0024 struct drm_framebuffer;
0025 struct drm_minor;
0026 struct drm_pending_vblank_event;
0027 struct drm_plane;
0028
0029 /* Defaulting to pixel clock defined on AM335x */
0030 #define TILCDC_DEFAULT_MAX_PIXELCLOCK  126000
0031 /* Maximum display width for LCDC V1 */
0032 #define TILCDC_DEFAULT_MAX_WIDTH_V1  1024
0033 /* ... and for LCDC V2 found on AM335x: */
0034 #define TILCDC_DEFAULT_MAX_WIDTH_V2  2048
0035 /*
0036  * This may need some tweaking, but want to allow at least 1280x1024@60
0037  * with optimized DDR & EMIF settings tweaked 1920x1080@24 appears to
0038  * be supportable
0039  */
0040 #define TILCDC_DEFAULT_MAX_BANDWIDTH  (1280*1024*60)
0041
0042
0043 struct tilcdc_drm_private {
0044     void __iomem *mmio;
0045
0046     struct clk *clk;         /* functional clock */
0047     int rev;                 /* IP revision */
0048
0049     unsigned int irq;
0050
0051     /* don't attempt resolutions w/ higher W * H * Hz: */
0052     uint32_t max_bandwidth;
0053     /*
0054      * Pixel Clock will be restricted to some value as
0055      * defined in the device datasheet measured in KHz
0056      */
0057     uint32_t max_pixelclock;
0058     /*
0059      * Max allowable width is limited on a per device basis
0060      * measured in pixels
0061      */
0062     uint32_t max_width;
0063
0064     /* Supported pixel formats */
0065     const uint32_t *pixelformats;
0066     uint32_t num_pixelformats;
0067
0068 #ifdef CONFIG_CPU_FREQ
0069     struct notifier_block freq_transition;
0070 #endif
0071
0072     struct workqueue_struct *wq;
0073
0074     struct drm_crtc *crtc;
0075
0076     unsigned int num_encoders;
0077     struct drm_encoder *encoders[8];
0078
0079     unsigned int num_connectors;
0080     struct drm_connector *connectors[8];
0081
0082     struct drm_encoder *external_encoder;
0083     struct drm_connector *external_connector;
0084
0085     bool is_registered;
0086     bool is_componentized;
0087     bool irq_enabled;
0088 };
0089
0090 /* Sub-module for display.  Since we don't know at compile time what panels
0091  * or display adapter(s) might be present (for ex, off chip dvi/tfp410,
0092  * hdmi encoder, various lcd panels), the connector/encoder(s) are split into
0093  * separate drivers.  If they are probed and found to be present, they
0094  * register themselves with tilcdc_register_module().
0095  */
0096 struct tilcdc_module;
0097
0098 struct tilcdc_module_ops {
0099     /* create appropriate encoders/connectors: */
0100     int (*modeset_init)(struct tilcdc_module *mod, struct drm_device *dev);
0101 #ifdef CONFIG_DEBUG_FS
0102     /* create debugfs nodes (can be NULL): */
0103     int (*debugfs_init)(struct tilcdc_module *mod, struct drm_minor *minor);
0104 #endif
0105 };
0106
0107 struct tilcdc_module {
0108     const char *name;
0109     struct list_head list;
0110     const struct tilcdc_module_ops *funcs;
0111 };
0112
0113 void tilcdc_module_init(struct tilcdc_module *mod, const char *name,
0114         const struct tilcdc_module_ops *funcs);
0115 void tilcdc_module_cleanup(struct tilcdc_module *mod);
0116
0117 /* Panel config that needs to be set in the crtc, but is not coming from
0118  * the mode timings.  The display module is expected to call
0119  * tilcdc_crtc_set_panel_info() to set this during modeset.
0120  */
0121 struct tilcdc_panel_info {
0122
0123     /* AC Bias Pin Frequency */
0124     uint32_t ac_bias;
0125
0126     /* AC Bias Pin Transitions per Interrupt */
0127     uint32_t ac_bias_intrpt;
0128
0129     /* DMA burst size */
0130     uint32_t dma_burst_sz;
0131
0132     /* Bits per pixel */
0133     uint32_t bpp;
0134
0135     /* FIFO DMA Request Delay */
0136     uint32_t fdd;
0137
0138     /* TFT Alternative Signal Mapping (Only for active) */
0139     bool tft_alt_mode;
0140
0141     /* Invert pixel clock */
0142     bool invert_pxl_clk;
0143
0144     /* Horizontal and Vertical Sync Edge: 0=rising 1=falling */
0145     uint32_t sync_edge;
0146
0147     /* Horizontal and Vertical Sync: Control: 0=ignore */
0148     uint32_t sync_ctrl;
0149
0150     /* Raster Data Order Select: 1=Most-to-least 0=Least-to-most */
0151     uint32_t raster_order;
0152
0153     /* DMA FIFO threshold */
0154     uint32_t fifo_th;
0155 };
0156
0157 #define DBG(fmt, ...) DRM_DEBUG(fmt"\n", ##__VA_ARGS__)
0158
0159 int tilcdc_crtc_create(struct drm_device *dev);
0160 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc);
0161 void tilcdc_crtc_update_clk(struct drm_crtc *crtc);
0162 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
0163         const struct tilcdc_panel_info *info);
0164 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
0165                     bool simulate_vesa_sync);
0166 void tilcdc_crtc_shutdown(struct drm_crtc *crtc);
0167 int tilcdc_crtc_update_fb(struct drm_crtc *crtc,
0168         struct drm_framebuffer *fb,
0169         struct drm_pending_vblank_event *event);
0170
0171 int tilcdc_plane_init(struct drm_device *dev, struct drm_plane *plane);
0172
0173 #endif /* __TILCDC_DRV_H__ */