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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2012 Texas Instruments
0004  * Author: Rob Clark <robdclark@gmail.com>
0005  */
0006 
0007 #include <linux/delay.h>
0008 #include <linux/dma-mapping.h>
0009 #include <linux/of_graph.h>
0010 #include <linux/pm_runtime.h>
0011 
0012 #include <drm/drm_atomic.h>
0013 #include <drm/drm_atomic_helper.h>
0014 #include <drm/drm_crtc.h>
0015 #include <drm/drm_fb_cma_helper.h>
0016 #include <drm/drm_fourcc.h>
0017 #include <drm/drm_framebuffer.h>
0018 #include <drm/drm_gem_cma_helper.h>
0019 #include <drm/drm_modeset_helper_vtables.h>
0020 #include <drm/drm_print.h>
0021 #include <drm/drm_vblank.h>
0022 
0023 #include "tilcdc_drv.h"
0024 #include "tilcdc_regs.h"
0025 
0026 #define TILCDC_VBLANK_SAFETY_THRESHOLD_US   1000
0027 #define TILCDC_PALETTE_SIZE         32
0028 #define TILCDC_PALETTE_FIRST_ENTRY      0x4000
0029 
0030 struct tilcdc_crtc {
0031     struct drm_crtc base;
0032 
0033     struct drm_plane primary;
0034     const struct tilcdc_panel_info *info;
0035     struct drm_pending_vblank_event *event;
0036     struct mutex enable_lock;
0037     bool enabled;
0038     bool shutdown;
0039     wait_queue_head_t frame_done_wq;
0040     bool frame_done;
0041     spinlock_t irq_lock;
0042 
0043     unsigned int lcd_fck_rate;
0044 
0045     ktime_t last_vblank;
0046     unsigned int hvtotal_us;
0047 
0048     struct drm_framebuffer *next_fb;
0049 
0050     /* Only set if an external encoder is connected */
0051     bool simulate_vesa_sync;
0052 
0053     int sync_lost_count;
0054     bool frame_intact;
0055     struct work_struct recover_work;
0056 
0057     dma_addr_t palette_dma_handle;
0058     u16 *palette_base;
0059     struct completion palette_loaded;
0060 };
0061 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
0062 
0063 static void set_scanout(struct drm_crtc *crtc, struct drm_framebuffer *fb)
0064 {
0065     struct drm_device *dev = crtc->dev;
0066     struct tilcdc_drm_private *priv = dev->dev_private;
0067     struct drm_gem_cma_object *gem;
0068     dma_addr_t start, end;
0069     u64 dma_base_and_ceiling;
0070 
0071     gem = drm_fb_cma_get_gem_obj(fb, 0);
0072 
0073     start = gem->paddr + fb->offsets[0] +
0074         crtc->y * fb->pitches[0] +
0075         crtc->x * fb->format->cpp[0];
0076 
0077     end = start + (crtc->mode.vdisplay * fb->pitches[0]);
0078 
0079     /* Write LCDC_DMA_FB_BASE_ADDR_0_REG and LCDC_DMA_FB_CEILING_ADDR_0_REG
0080      * with a single insruction, if available. This should make it more
0081      * unlikely that LCDC would fetch the DMA addresses in the middle of
0082      * an update.
0083      */
0084     if (priv->rev == 1)
0085         end -= 1;
0086 
0087     dma_base_and_ceiling = (u64)end << 32 | start;
0088     tilcdc_write64(dev, LCDC_DMA_FB_BASE_ADDR_0_REG, dma_base_and_ceiling);
0089 }
0090 
0091 /*
0092  * The driver currently only supports only true color formats. For
0093  * true color the palette block is bypassed, but a 32 byte palette
0094  * should still be loaded. The first 16-bit entry must be 0x4000 while
0095  * all other entries must be zeroed.
0096  */
0097 static void tilcdc_crtc_load_palette(struct drm_crtc *crtc)
0098 {
0099     struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
0100     struct drm_device *dev = crtc->dev;
0101     struct tilcdc_drm_private *priv = dev->dev_private;
0102     int ret;
0103 
0104     reinit_completion(&tilcdc_crtc->palette_loaded);
0105 
0106     /* Tell the LCDC where the palette is located. */
0107     tilcdc_write(dev, LCDC_DMA_FB_BASE_ADDR_0_REG,
0108              tilcdc_crtc->palette_dma_handle);
0109     tilcdc_write(dev, LCDC_DMA_FB_CEILING_ADDR_0_REG,
0110              (u32) tilcdc_crtc->palette_dma_handle +
0111              TILCDC_PALETTE_SIZE - 1);
0112 
0113     /* Set dma load mode for palette loading only. */
0114     tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
0115               LCDC_PALETTE_LOAD_MODE(PALETTE_ONLY),
0116               LCDC_PALETTE_LOAD_MODE_MASK);
0117 
0118     /* Enable DMA Palette Loaded Interrupt */
0119     if (priv->rev == 1)
0120         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
0121     else
0122         tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, LCDC_V2_PL_INT_ENA);
0123 
0124     /* Enable LCDC DMA and wait for palette to be loaded. */
0125     tilcdc_clear_irqstatus(dev, 0xffffffff);
0126     tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
0127 
0128     ret = wait_for_completion_timeout(&tilcdc_crtc->palette_loaded,
0129                       msecs_to_jiffies(50));
0130     if (ret == 0)
0131         dev_err(dev->dev, "%s: Palette loading timeout", __func__);
0132 
0133     /* Disable LCDC DMA and DMA Palette Loaded Interrupt. */
0134     tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
0135     if (priv->rev == 1)
0136         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_V1_PL_INT_ENA);
0137     else
0138         tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG, LCDC_V2_PL_INT_ENA);
0139 }
0140 
0141 static void tilcdc_crtc_enable_irqs(struct drm_device *dev)
0142 {
0143     struct tilcdc_drm_private *priv = dev->dev_private;
0144 
0145     tilcdc_clear_irqstatus(dev, 0xffffffff);
0146 
0147     if (priv->rev == 1) {
0148         tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
0149             LCDC_V1_SYNC_LOST_INT_ENA | LCDC_V1_FRAME_DONE_INT_ENA |
0150             LCDC_V1_UNDERFLOW_INT_ENA);
0151     } else {
0152         tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG,
0153             LCDC_V2_UNDERFLOW_INT_ENA |
0154             LCDC_FRAME_DONE | LCDC_SYNC_LOST);
0155     }
0156 }
0157 
0158 static void tilcdc_crtc_disable_irqs(struct drm_device *dev)
0159 {
0160     struct tilcdc_drm_private *priv = dev->dev_private;
0161 
0162     /* disable irqs that we might have enabled: */
0163     if (priv->rev == 1) {
0164         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
0165             LCDC_V1_SYNC_LOST_INT_ENA | LCDC_V1_FRAME_DONE_INT_ENA |
0166             LCDC_V1_UNDERFLOW_INT_ENA | LCDC_V1_PL_INT_ENA);
0167         tilcdc_clear(dev, LCDC_DMA_CTRL_REG,
0168             LCDC_V1_END_OF_FRAME_INT_ENA);
0169     } else {
0170         tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
0171             LCDC_V2_UNDERFLOW_INT_ENA | LCDC_V2_PL_INT_ENA |
0172             LCDC_V2_END_OF_FRAME0_INT_ENA |
0173             LCDC_FRAME_DONE | LCDC_SYNC_LOST);
0174     }
0175 }
0176 
0177 static void reset(struct drm_crtc *crtc)
0178 {
0179     struct drm_device *dev = crtc->dev;
0180     struct tilcdc_drm_private *priv = dev->dev_private;
0181 
0182     if (priv->rev != 2)
0183         return;
0184 
0185     tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
0186     usleep_range(250, 1000);
0187     tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
0188 }
0189 
0190 /*
0191  * Calculate the percentage difference between the requested pixel clock rate
0192  * and the effective rate resulting from calculating the clock divider value.
0193  */
0194 static unsigned int tilcdc_pclk_diff(unsigned long rate,
0195                      unsigned long real_rate)
0196 {
0197     int r = rate / 100, rr = real_rate / 100;
0198 
0199     return (unsigned int)(abs(((rr - r) * 100) / r));
0200 }
0201 
0202 static void tilcdc_crtc_set_clk(struct drm_crtc *crtc)
0203 {
0204     struct drm_device *dev = crtc->dev;
0205     struct tilcdc_drm_private *priv = dev->dev_private;
0206     struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
0207     unsigned long clk_rate, real_pclk_rate, pclk_rate;
0208     unsigned int clkdiv;
0209     int ret;
0210 
0211     clkdiv = 2; /* first try using a standard divider of 2 */
0212 
0213     /* mode.clock is in KHz, set_rate wants parameter in Hz */
0214     pclk_rate = crtc->mode.clock * 1000;
0215 
0216     ret = clk_set_rate(priv->clk, pclk_rate * clkdiv);
0217     clk_rate = clk_get_rate(priv->clk);
0218     real_pclk_rate = clk_rate / clkdiv;
0219     if (ret < 0 || tilcdc_pclk_diff(pclk_rate, real_pclk_rate) > 5) {
0220         /*
0221          * If we fail to set the clock rate (some architectures don't
0222          * use the common clock framework yet and may not implement
0223          * all the clk API calls for every clock), try the next best
0224          * thing: adjusting the clock divider, unless clk_get_rate()
0225          * failed as well.
0226          */
0227         if (!clk_rate) {
0228             /* Nothing more we can do. Just bail out. */
0229             dev_err(dev->dev,
0230                 "failed to set the pixel clock - unable to read current lcdc clock rate\n");
0231             return;
0232         }
0233 
0234         clkdiv = DIV_ROUND_CLOSEST(clk_rate, pclk_rate);
0235 
0236         /*
0237          * Emit a warning if the real clock rate resulting from the
0238          * calculated divider differs much from the requested rate.
0239          *
0240          * 5% is an arbitrary value - LCDs are usually quite tolerant
0241          * about pixel clock rates.
0242          */
0243         real_pclk_rate = clk_rate / clkdiv;
0244 
0245         if (tilcdc_pclk_diff(pclk_rate, real_pclk_rate) > 5) {
0246             dev_warn(dev->dev,
0247                  "effective pixel clock rate (%luHz) differs from the requested rate (%luHz)\n",
0248                  real_pclk_rate, pclk_rate);
0249         }
0250     }
0251 
0252     tilcdc_crtc->lcd_fck_rate = clk_rate;
0253 
0254     DBG("lcd_clk=%u, mode clock=%d, div=%u",
0255         tilcdc_crtc->lcd_fck_rate, crtc->mode.clock, clkdiv);
0256 
0257     /* Configure the LCD clock divisor. */
0258     tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(clkdiv) |
0259              LCDC_RASTER_MODE);
0260 
0261     if (priv->rev == 2)
0262         tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
0263                 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
0264                 LCDC_V2_CORE_CLK_EN);
0265 }
0266 
0267 static uint tilcdc_mode_hvtotal(const struct drm_display_mode *mode)
0268 {
0269     return (uint) div_u64(1000llu * mode->htotal * mode->vtotal,
0270                   mode->clock);
0271 }
0272 
0273 static void tilcdc_crtc_set_mode(struct drm_crtc *crtc)
0274 {
0275     struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
0276     struct drm_device *dev = crtc->dev;
0277     struct tilcdc_drm_private *priv = dev->dev_private;
0278     const struct tilcdc_panel_info *info = tilcdc_crtc->info;
0279     uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
0280     struct drm_display_mode *mode = &crtc->state->adjusted_mode;
0281     struct drm_framebuffer *fb = crtc->primary->state->fb;
0282 
0283     if (WARN_ON(!info))
0284         return;
0285 
0286     if (WARN_ON(!fb))
0287         return;
0288 
0289     /* Configure the Burst Size and fifo threshold of DMA: */
0290     reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
0291     switch (info->dma_burst_sz) {
0292     case 1:
0293         reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
0294         break;
0295     case 2:
0296         reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
0297         break;
0298     case 4:
0299         reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
0300         break;
0301     case 8:
0302         reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
0303         break;
0304     case 16:
0305         reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
0306         break;
0307     default:
0308         dev_err(dev->dev, "invalid burst size\n");
0309         return;
0310     }
0311     reg |= (info->fifo_th << 8);
0312     tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
0313 
0314     /* Configure timings: */
0315     hbp = mode->htotal - mode->hsync_end;
0316     hfp = mode->hsync_start - mode->hdisplay;
0317     hsw = mode->hsync_end - mode->hsync_start;
0318     vbp = mode->vtotal - mode->vsync_end;
0319     vfp = mode->vsync_start - mode->vdisplay;
0320     vsw = mode->vsync_end - mode->vsync_start;
0321 
0322     DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
0323         mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
0324 
0325     /* Set AC Bias Period and Number of Transitions per Interrupt: */
0326     reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
0327     reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
0328         LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
0329 
0330     /*
0331      * subtract one from hfp, hbp, hsw because the hardware uses
0332      * a value of 0 as 1
0333      */
0334     if (priv->rev == 2) {
0335         /* clear bits we're going to set */
0336         reg &= ~0x78000033;
0337         reg |= ((hfp-1) & 0x300) >> 8;
0338         reg |= ((hbp-1) & 0x300) >> 4;
0339         reg |= ((hsw-1) & 0x3c0) << 21;
0340     }
0341     tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
0342 
0343     reg = (((mode->hdisplay >> 4) - 1) << 4) |
0344         (((hbp-1) & 0xff) << 24) |
0345         (((hfp-1) & 0xff) << 16) |
0346         (((hsw-1) & 0x3f) << 10);
0347     if (priv->rev == 2)
0348         reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
0349     tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
0350 
0351     reg = ((mode->vdisplay - 1) & 0x3ff) |
0352         ((vbp & 0xff) << 24) |
0353         ((vfp & 0xff) << 16) |
0354         (((vsw-1) & 0x3f) << 10);
0355     tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
0356 
0357     /*
0358      * be sure to set Bit 10 for the V2 LCDC controller,
0359      * otherwise limited to 1024 pixels width, stopping
0360      * 1920x1080 being supported.
0361      */
0362     if (priv->rev == 2) {
0363         if ((mode->vdisplay - 1) & 0x400) {
0364             tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
0365                 LCDC_LPP_B10);
0366         } else {
0367             tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
0368                 LCDC_LPP_B10);
0369         }
0370     }
0371 
0372     /* Configure display type: */
0373     reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
0374         ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
0375           LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK |
0376           0x000ff000 /* Palette Loading Delay bits */);
0377     reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
0378     if (info->tft_alt_mode)
0379         reg |= LCDC_TFT_ALT_ENABLE;
0380     if (priv->rev == 2) {
0381         switch (fb->format->format) {
0382         case DRM_FORMAT_BGR565:
0383         case DRM_FORMAT_RGB565:
0384             break;
0385         case DRM_FORMAT_XBGR8888:
0386         case DRM_FORMAT_XRGB8888:
0387             reg |= LCDC_V2_TFT_24BPP_UNPACK;
0388             fallthrough;
0389         case DRM_FORMAT_BGR888:
0390         case DRM_FORMAT_RGB888:
0391             reg |= LCDC_V2_TFT_24BPP_MODE;
0392             break;
0393         default:
0394             dev_err(dev->dev, "invalid pixel format\n");
0395             return;
0396         }
0397     }
0398     reg |= info->fdd << 12;
0399     tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
0400 
0401     if (info->invert_pxl_clk)
0402         tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
0403     else
0404         tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
0405 
0406     if (info->sync_ctrl)
0407         tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
0408     else
0409         tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
0410 
0411     if (info->sync_edge)
0412         tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
0413     else
0414         tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
0415 
0416     if (mode->flags & DRM_MODE_FLAG_NHSYNC)
0417         tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
0418     else
0419         tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
0420 
0421     if (mode->flags & DRM_MODE_FLAG_NVSYNC)
0422         tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
0423     else
0424         tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
0425 
0426     if (info->raster_order)
0427         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
0428     else
0429         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
0430 
0431     tilcdc_crtc_set_clk(crtc);
0432 
0433     tilcdc_crtc_load_palette(crtc);
0434 
0435     set_scanout(crtc, fb);
0436 
0437     drm_mode_copy(&crtc->hwmode, &crtc->state->adjusted_mode);
0438 
0439     tilcdc_crtc->hvtotal_us =
0440         tilcdc_mode_hvtotal(&crtc->hwmode);
0441 }
0442 
0443 static void tilcdc_crtc_enable(struct drm_crtc *crtc)
0444 {
0445     struct drm_device *dev = crtc->dev;
0446     struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
0447     unsigned long flags;
0448 
0449     mutex_lock(&tilcdc_crtc->enable_lock);
0450     if (tilcdc_crtc->enabled || tilcdc_crtc->shutdown) {
0451         mutex_unlock(&tilcdc_crtc->enable_lock);
0452         return;
0453     }
0454 
0455     pm_runtime_get_sync(dev->dev);
0456 
0457     reset(crtc);
0458 
0459     tilcdc_crtc_set_mode(crtc);
0460 
0461     tilcdc_crtc_enable_irqs(dev);
0462 
0463     tilcdc_clear(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
0464     tilcdc_write_mask(dev, LCDC_RASTER_CTRL_REG,
0465               LCDC_PALETTE_LOAD_MODE(DATA_ONLY),
0466               LCDC_PALETTE_LOAD_MODE_MASK);
0467 
0468     /* There is no real chance for a race here as the time stamp
0469      * is taken before the raster DMA is started. The spin-lock is
0470      * taken to have a memory barrier after taking the time-stamp
0471      * and to avoid a context switch between taking the stamp and
0472      * enabling the raster.
0473      */
0474     spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
0475     tilcdc_crtc->last_vblank = ktime_get();
0476     tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
0477     spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
0478 
0479     drm_crtc_vblank_on(crtc);
0480 
0481     tilcdc_crtc->enabled = true;
0482     mutex_unlock(&tilcdc_crtc->enable_lock);
0483 }
0484 
0485 static void tilcdc_crtc_atomic_enable(struct drm_crtc *crtc,
0486                       struct drm_atomic_state *state)
0487 {
0488     tilcdc_crtc_enable(crtc);
0489 }
0490 
0491 static void tilcdc_crtc_off(struct drm_crtc *crtc, bool shutdown)
0492 {
0493     struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
0494     struct drm_device *dev = crtc->dev;
0495     int ret;
0496 
0497     mutex_lock(&tilcdc_crtc->enable_lock);
0498     if (shutdown)
0499         tilcdc_crtc->shutdown = true;
0500     if (!tilcdc_crtc->enabled) {
0501         mutex_unlock(&tilcdc_crtc->enable_lock);
0502         return;
0503     }
0504     tilcdc_crtc->frame_done = false;
0505     tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
0506 
0507     /*
0508      * Wait for framedone irq which will still come before putting
0509      * things to sleep..
0510      */
0511     ret = wait_event_timeout(tilcdc_crtc->frame_done_wq,
0512                  tilcdc_crtc->frame_done,
0513                  msecs_to_jiffies(500));
0514     if (ret == 0)
0515         dev_err(dev->dev, "%s: timeout waiting for framedone\n",
0516             __func__);
0517 
0518     drm_crtc_vblank_off(crtc);
0519 
0520     spin_lock_irq(&crtc->dev->event_lock);
0521 
0522     if (crtc->state->event) {
0523         drm_crtc_send_vblank_event(crtc, crtc->state->event);
0524         crtc->state->event = NULL;
0525     }
0526 
0527     spin_unlock_irq(&crtc->dev->event_lock);
0528 
0529     tilcdc_crtc_disable_irqs(dev);
0530 
0531     pm_runtime_put_sync(dev->dev);
0532 
0533     tilcdc_crtc->enabled = false;
0534     mutex_unlock(&tilcdc_crtc->enable_lock);
0535 }
0536 
0537 static void tilcdc_crtc_disable(struct drm_crtc *crtc)
0538 {
0539     tilcdc_crtc_off(crtc, false);
0540 }
0541 
0542 static void tilcdc_crtc_atomic_disable(struct drm_crtc *crtc,
0543                        struct drm_atomic_state *state)
0544 {
0545     tilcdc_crtc_disable(crtc);
0546 }
0547 
0548 static void tilcdc_crtc_atomic_flush(struct drm_crtc *crtc,
0549                      struct drm_atomic_state *state)
0550 {
0551     if (!crtc->state->event)
0552         return;
0553 
0554     spin_lock_irq(&crtc->dev->event_lock);
0555     drm_crtc_send_vblank_event(crtc, crtc->state->event);
0556     crtc->state->event = NULL;
0557     spin_unlock_irq(&crtc->dev->event_lock);
0558 }
0559 
0560 void tilcdc_crtc_shutdown(struct drm_crtc *crtc)
0561 {
0562     tilcdc_crtc_off(crtc, true);
0563 }
0564 
0565 static bool tilcdc_crtc_is_on(struct drm_crtc *crtc)
0566 {
0567     return crtc->state && crtc->state->enable && crtc->state->active;
0568 }
0569 
0570 static void tilcdc_crtc_recover_work(struct work_struct *work)
0571 {
0572     struct tilcdc_crtc *tilcdc_crtc =
0573         container_of(work, struct tilcdc_crtc, recover_work);
0574     struct drm_crtc *crtc = &tilcdc_crtc->base;
0575 
0576     dev_info(crtc->dev->dev, "%s: Reset CRTC", __func__);
0577 
0578     drm_modeset_lock(&crtc->mutex, NULL);
0579 
0580     if (!tilcdc_crtc_is_on(crtc))
0581         goto out;
0582 
0583     tilcdc_crtc_disable(crtc);
0584     tilcdc_crtc_enable(crtc);
0585 out:
0586     drm_modeset_unlock(&crtc->mutex);
0587 }
0588 
0589 static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
0590 {
0591     struct tilcdc_drm_private *priv = crtc->dev->dev_private;
0592 
0593     tilcdc_crtc_shutdown(crtc);
0594 
0595     flush_workqueue(priv->wq);
0596 
0597     of_node_put(crtc->port);
0598     drm_crtc_cleanup(crtc);
0599 }
0600 
0601 int tilcdc_crtc_update_fb(struct drm_crtc *crtc,
0602         struct drm_framebuffer *fb,
0603         struct drm_pending_vblank_event *event)
0604 {
0605     struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
0606     struct drm_device *dev = crtc->dev;
0607 
0608     if (tilcdc_crtc->event) {
0609         dev_err(dev->dev, "already pending page flip!\n");
0610         return -EBUSY;
0611     }
0612 
0613     tilcdc_crtc->event = event;
0614 
0615     mutex_lock(&tilcdc_crtc->enable_lock);
0616 
0617     if (tilcdc_crtc->enabled) {
0618         unsigned long flags;
0619         ktime_t next_vblank;
0620         s64 tdiff;
0621 
0622         spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
0623 
0624         next_vblank = ktime_add_us(tilcdc_crtc->last_vblank,
0625                        tilcdc_crtc->hvtotal_us);
0626         tdiff = ktime_to_us(ktime_sub(next_vblank, ktime_get()));
0627 
0628         if (tdiff < TILCDC_VBLANK_SAFETY_THRESHOLD_US)
0629             tilcdc_crtc->next_fb = fb;
0630         else
0631             set_scanout(crtc, fb);
0632 
0633         spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
0634     }
0635 
0636     mutex_unlock(&tilcdc_crtc->enable_lock);
0637 
0638     return 0;
0639 }
0640 
0641 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
0642         const struct drm_display_mode *mode,
0643         struct drm_display_mode *adjusted_mode)
0644 {
0645     struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
0646 
0647     if (!tilcdc_crtc->simulate_vesa_sync)
0648         return true;
0649 
0650     /*
0651      * tilcdc does not generate VESA-compliant sync but aligns
0652      * VS on the second edge of HS instead of first edge.
0653      * We use adjusted_mode, to fixup sync by aligning both rising
0654      * edges and add HSKEW offset to fix the sync.
0655      */
0656     adjusted_mode->hskew = mode->hsync_end - mode->hsync_start;
0657     adjusted_mode->flags |= DRM_MODE_FLAG_HSKEW;
0658 
0659     if (mode->flags & DRM_MODE_FLAG_NHSYNC) {
0660         adjusted_mode->flags |= DRM_MODE_FLAG_PHSYNC;
0661         adjusted_mode->flags &= ~DRM_MODE_FLAG_NHSYNC;
0662     } else {
0663         adjusted_mode->flags |= DRM_MODE_FLAG_NHSYNC;
0664         adjusted_mode->flags &= ~DRM_MODE_FLAG_PHSYNC;
0665     }
0666 
0667     return true;
0668 }
0669 
0670 static int tilcdc_crtc_atomic_check(struct drm_crtc *crtc,
0671                     struct drm_atomic_state *state)
0672 {
0673     struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
0674                                       crtc);
0675     /* If we are not active we don't care */
0676     if (!crtc_state->active)
0677         return 0;
0678 
0679     if (state->planes[0].ptr != crtc->primary ||
0680         state->planes[0].state == NULL ||
0681         state->planes[0].state->crtc != crtc) {
0682         dev_dbg(crtc->dev->dev, "CRTC primary plane must be present");
0683         return -EINVAL;
0684     }
0685 
0686     return 0;
0687 }
0688 
0689 static int tilcdc_crtc_enable_vblank(struct drm_crtc *crtc)
0690 {
0691     struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
0692     struct drm_device *dev = crtc->dev;
0693     struct tilcdc_drm_private *priv = dev->dev_private;
0694     unsigned long flags;
0695 
0696     spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
0697 
0698     tilcdc_clear_irqstatus(dev, LCDC_END_OF_FRAME0);
0699 
0700     if (priv->rev == 1)
0701         tilcdc_set(dev, LCDC_DMA_CTRL_REG,
0702                LCDC_V1_END_OF_FRAME_INT_ENA);
0703     else
0704         tilcdc_set(dev, LCDC_INT_ENABLE_SET_REG,
0705                LCDC_V2_END_OF_FRAME0_INT_ENA);
0706 
0707     spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
0708 
0709     return 0;
0710 }
0711 
0712 static void tilcdc_crtc_disable_vblank(struct drm_crtc *crtc)
0713 {
0714     struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
0715     struct drm_device *dev = crtc->dev;
0716     struct tilcdc_drm_private *priv = dev->dev_private;
0717     unsigned long flags;
0718 
0719     spin_lock_irqsave(&tilcdc_crtc->irq_lock, flags);
0720 
0721     if (priv->rev == 1)
0722         tilcdc_clear(dev, LCDC_DMA_CTRL_REG,
0723                  LCDC_V1_END_OF_FRAME_INT_ENA);
0724     else
0725         tilcdc_clear(dev, LCDC_INT_ENABLE_SET_REG,
0726                  LCDC_V2_END_OF_FRAME0_INT_ENA);
0727 
0728     spin_unlock_irqrestore(&tilcdc_crtc->irq_lock, flags);
0729 }
0730 
0731 static void tilcdc_crtc_reset(struct drm_crtc *crtc)
0732 {
0733     struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
0734     struct drm_device *dev = crtc->dev;
0735     int ret;
0736 
0737     drm_atomic_helper_crtc_reset(crtc);
0738 
0739     /* Turn the raster off if it for some reason is on. */
0740     pm_runtime_get_sync(dev->dev);
0741     if (tilcdc_read(dev, LCDC_RASTER_CTRL_REG) & LCDC_RASTER_ENABLE) {
0742         /* Enable DMA Frame Done Interrupt */
0743         tilcdc_write(dev, LCDC_INT_ENABLE_SET_REG, LCDC_FRAME_DONE);
0744         tilcdc_clear_irqstatus(dev, 0xffffffff);
0745 
0746         tilcdc_crtc->frame_done = false;
0747         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
0748 
0749         ret = wait_event_timeout(tilcdc_crtc->frame_done_wq,
0750                      tilcdc_crtc->frame_done,
0751                      msecs_to_jiffies(500));
0752         if (ret == 0)
0753             dev_err(dev->dev, "%s: timeout waiting for framedone\n",
0754                 __func__);
0755     }
0756     pm_runtime_put_sync(dev->dev);
0757 }
0758 
0759 static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
0760     .destroy        = tilcdc_crtc_destroy,
0761     .set_config     = drm_atomic_helper_set_config,
0762     .page_flip      = drm_atomic_helper_page_flip,
0763     .reset      = tilcdc_crtc_reset,
0764     .atomic_duplicate_state = drm_atomic_helper_crtc_duplicate_state,
0765     .atomic_destroy_state = drm_atomic_helper_crtc_destroy_state,
0766     .enable_vblank  = tilcdc_crtc_enable_vblank,
0767     .disable_vblank = tilcdc_crtc_disable_vblank,
0768 };
0769 
0770 static enum drm_mode_status
0771 tilcdc_crtc_mode_valid(struct drm_crtc *crtc,
0772                const struct drm_display_mode *mode)
0773 {
0774     struct tilcdc_drm_private *priv = crtc->dev->dev_private;
0775     unsigned int bandwidth;
0776     uint32_t hbp, hfp, hsw, vbp, vfp, vsw;
0777 
0778     /*
0779      * check to see if the width is within the range that
0780      * the LCD Controller physically supports
0781      */
0782     if (mode->hdisplay > priv->max_width)
0783         return MODE_VIRTUAL_X;
0784 
0785     /* width must be multiple of 16 */
0786     if (mode->hdisplay & 0xf)
0787         return MODE_VIRTUAL_X;
0788 
0789     if (mode->vdisplay > 2048)
0790         return MODE_VIRTUAL_Y;
0791 
0792     DBG("Processing mode %dx%d@%d with pixel clock %d",
0793         mode->hdisplay, mode->vdisplay,
0794         drm_mode_vrefresh(mode), mode->clock);
0795 
0796     hbp = mode->htotal - mode->hsync_end;
0797     hfp = mode->hsync_start - mode->hdisplay;
0798     hsw = mode->hsync_end - mode->hsync_start;
0799     vbp = mode->vtotal - mode->vsync_end;
0800     vfp = mode->vsync_start - mode->vdisplay;
0801     vsw = mode->vsync_end - mode->vsync_start;
0802 
0803     if ((hbp-1) & ~0x3ff) {
0804         DBG("Pruning mode: Horizontal Back Porch out of range");
0805         return MODE_HBLANK_WIDE;
0806     }
0807 
0808     if ((hfp-1) & ~0x3ff) {
0809         DBG("Pruning mode: Horizontal Front Porch out of range");
0810         return MODE_HBLANK_WIDE;
0811     }
0812 
0813     if ((hsw-1) & ~0x3ff) {
0814         DBG("Pruning mode: Horizontal Sync Width out of range");
0815         return MODE_HSYNC_WIDE;
0816     }
0817 
0818     if (vbp & ~0xff) {
0819         DBG("Pruning mode: Vertical Back Porch out of range");
0820         return MODE_VBLANK_WIDE;
0821     }
0822 
0823     if (vfp & ~0xff) {
0824         DBG("Pruning mode: Vertical Front Porch out of range");
0825         return MODE_VBLANK_WIDE;
0826     }
0827 
0828     if ((vsw-1) & ~0x3f) {
0829         DBG("Pruning mode: Vertical Sync Width out of range");
0830         return MODE_VSYNC_WIDE;
0831     }
0832 
0833     /*
0834      * some devices have a maximum allowed pixel clock
0835      * configured from the DT
0836      */
0837     if (mode->clock > priv->max_pixelclock) {
0838         DBG("Pruning mode: pixel clock too high");
0839         return MODE_CLOCK_HIGH;
0840     }
0841 
0842     /*
0843      * some devices further limit the max horizontal resolution
0844      * configured from the DT
0845      */
0846     if (mode->hdisplay > priv->max_width)
0847         return MODE_BAD_WIDTH;
0848 
0849     /* filter out modes that would require too much memory bandwidth: */
0850     bandwidth = mode->hdisplay * mode->vdisplay *
0851         drm_mode_vrefresh(mode);
0852     if (bandwidth > priv->max_bandwidth) {
0853         DBG("Pruning mode: exceeds defined bandwidth limit");
0854         return MODE_BAD;
0855     }
0856 
0857     return MODE_OK;
0858 }
0859 
0860 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
0861     .mode_valid = tilcdc_crtc_mode_valid,
0862     .mode_fixup = tilcdc_crtc_mode_fixup,
0863     .atomic_check   = tilcdc_crtc_atomic_check,
0864     .atomic_enable  = tilcdc_crtc_atomic_enable,
0865     .atomic_disable = tilcdc_crtc_atomic_disable,
0866     .atomic_flush   = tilcdc_crtc_atomic_flush,
0867 };
0868 
0869 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
0870         const struct tilcdc_panel_info *info)
0871 {
0872     struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
0873     tilcdc_crtc->info = info;
0874 }
0875 
0876 void tilcdc_crtc_set_simulate_vesa_sync(struct drm_crtc *crtc,
0877                     bool simulate_vesa_sync)
0878 {
0879     struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
0880 
0881     tilcdc_crtc->simulate_vesa_sync = simulate_vesa_sync;
0882 }
0883 
0884 void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
0885 {
0886     struct drm_device *dev = crtc->dev;
0887     struct tilcdc_drm_private *priv = dev->dev_private;
0888     struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
0889 
0890     drm_modeset_lock(&crtc->mutex, NULL);
0891     if (tilcdc_crtc->lcd_fck_rate != clk_get_rate(priv->clk)) {
0892         if (tilcdc_crtc_is_on(crtc)) {
0893             pm_runtime_get_sync(dev->dev);
0894             tilcdc_crtc_disable(crtc);
0895 
0896             tilcdc_crtc_set_clk(crtc);
0897 
0898             tilcdc_crtc_enable(crtc);
0899             pm_runtime_put_sync(dev->dev);
0900         }
0901     }
0902     drm_modeset_unlock(&crtc->mutex);
0903 }
0904 
0905 #define SYNC_LOST_COUNT_LIMIT 50
0906 
0907 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
0908 {
0909     struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
0910     struct drm_device *dev = crtc->dev;
0911     struct tilcdc_drm_private *priv = dev->dev_private;
0912     uint32_t stat, reg;
0913 
0914     stat = tilcdc_read_irqstatus(dev);
0915     tilcdc_clear_irqstatus(dev, stat);
0916 
0917     if (stat & LCDC_END_OF_FRAME0) {
0918         bool skip_event = false;
0919         ktime_t now;
0920 
0921         now = ktime_get();
0922 
0923         spin_lock(&tilcdc_crtc->irq_lock);
0924 
0925         tilcdc_crtc->last_vblank = now;
0926 
0927         if (tilcdc_crtc->next_fb) {
0928             set_scanout(crtc, tilcdc_crtc->next_fb);
0929             tilcdc_crtc->next_fb = NULL;
0930             skip_event = true;
0931         }
0932 
0933         spin_unlock(&tilcdc_crtc->irq_lock);
0934 
0935         drm_crtc_handle_vblank(crtc);
0936 
0937         if (!skip_event) {
0938             struct drm_pending_vblank_event *event;
0939 
0940             spin_lock(&dev->event_lock);
0941 
0942             event = tilcdc_crtc->event;
0943             tilcdc_crtc->event = NULL;
0944             if (event)
0945                 drm_crtc_send_vblank_event(crtc, event);
0946 
0947             spin_unlock(&dev->event_lock);
0948         }
0949 
0950         if (tilcdc_crtc->frame_intact)
0951             tilcdc_crtc->sync_lost_count = 0;
0952         else
0953             tilcdc_crtc->frame_intact = true;
0954     }
0955 
0956     if (stat & LCDC_FIFO_UNDERFLOW)
0957         dev_err_ratelimited(dev->dev, "%s(0x%08x): FIFO underflow",
0958                     __func__, stat);
0959 
0960     if (stat & LCDC_PL_LOAD_DONE) {
0961         complete(&tilcdc_crtc->palette_loaded);
0962         if (priv->rev == 1)
0963             tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
0964                      LCDC_V1_PL_INT_ENA);
0965         else
0966             tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
0967                      LCDC_V2_PL_INT_ENA);
0968     }
0969 
0970     if (stat & LCDC_SYNC_LOST) {
0971         dev_err_ratelimited(dev->dev, "%s(0x%08x): Sync lost",
0972                     __func__, stat);
0973         tilcdc_crtc->frame_intact = false;
0974         if (priv->rev == 1) {
0975             reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG);
0976             if (reg & LCDC_RASTER_ENABLE) {
0977                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
0978                          LCDC_RASTER_ENABLE);
0979                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG,
0980                        LCDC_RASTER_ENABLE);
0981             }
0982         } else {
0983             if (tilcdc_crtc->sync_lost_count++ >
0984                 SYNC_LOST_COUNT_LIMIT) {
0985                 dev_err(dev->dev,
0986                     "%s(0x%08x): Sync lost flood detected, recovering",
0987                     __func__, stat);
0988                 queue_work(system_wq,
0989                        &tilcdc_crtc->recover_work);
0990                 tilcdc_write(dev, LCDC_INT_ENABLE_CLR_REG,
0991                          LCDC_SYNC_LOST);
0992                 tilcdc_crtc->sync_lost_count = 0;
0993             }
0994         }
0995     }
0996 
0997     if (stat & LCDC_FRAME_DONE) {
0998         tilcdc_crtc->frame_done = true;
0999         wake_up(&tilcdc_crtc->frame_done_wq);
1000         /* rev 1 lcdc appears to hang if irq is not disabled here */
1001         if (priv->rev == 1)
1002             tilcdc_clear(dev, LCDC_RASTER_CTRL_REG,
1003                      LCDC_V1_FRAME_DONE_INT_ENA);
1004     }
1005 
1006     /* For revision 2 only */
1007     if (priv->rev == 2) {
1008         /* Indicate to LCDC that the interrupt service routine has
1009          * completed, see 13.3.6.1.6 in AM335x TRM.
1010          */
1011         tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
1012     }
1013 
1014     return IRQ_HANDLED;
1015 }
1016 
1017 int tilcdc_crtc_create(struct drm_device *dev)
1018 {
1019     struct tilcdc_drm_private *priv = dev->dev_private;
1020     struct tilcdc_crtc *tilcdc_crtc;
1021     struct drm_crtc *crtc;
1022     int ret;
1023 
1024     tilcdc_crtc = devm_kzalloc(dev->dev, sizeof(*tilcdc_crtc), GFP_KERNEL);
1025     if (!tilcdc_crtc)
1026         return -ENOMEM;
1027 
1028     init_completion(&tilcdc_crtc->palette_loaded);
1029     tilcdc_crtc->palette_base = dmam_alloc_coherent(dev->dev,
1030                     TILCDC_PALETTE_SIZE,
1031                     &tilcdc_crtc->palette_dma_handle,
1032                     GFP_KERNEL | __GFP_ZERO);
1033     if (!tilcdc_crtc->palette_base)
1034         return -ENOMEM;
1035     *tilcdc_crtc->palette_base = TILCDC_PALETTE_FIRST_ENTRY;
1036 
1037     crtc = &tilcdc_crtc->base;
1038 
1039     ret = tilcdc_plane_init(dev, &tilcdc_crtc->primary);
1040     if (ret < 0)
1041         goto fail;
1042 
1043     mutex_init(&tilcdc_crtc->enable_lock);
1044 
1045     init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
1046 
1047     spin_lock_init(&tilcdc_crtc->irq_lock);
1048     INIT_WORK(&tilcdc_crtc->recover_work, tilcdc_crtc_recover_work);
1049 
1050     ret = drm_crtc_init_with_planes(dev, crtc,
1051                     &tilcdc_crtc->primary,
1052                     NULL,
1053                     &tilcdc_crtc_funcs,
1054                     "tilcdc crtc");
1055     if (ret < 0)
1056         goto fail;
1057 
1058     drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
1059 
1060     if (priv->is_componentized) {
1061         crtc->port = of_graph_get_port_by_id(dev->dev->of_node, 0);
1062         if (!crtc->port) { /* This should never happen */
1063             dev_err(dev->dev, "Port node not found in %pOF\n",
1064                 dev->dev->of_node);
1065             ret = -EINVAL;
1066             goto fail;
1067         }
1068     }
1069 
1070     priv->crtc = crtc;
1071     return 0;
1072 
1073 fail:
1074     tilcdc_crtc_destroy(crtc);
1075     return ret;
1076 }
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