drm/tidss/tidss_dispc.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com/
0004  * Author: Tomi Valkeinen <tomi.valkeinen@ti.com>
0005  */
0006
0007 #ifndef __TIDSS_DISPC_H__
0008 #define __TIDSS_DISPC_H__
0009
0010 #include "tidss_drv.h"
0011
0012 struct dispc_device;
0013
0014 struct drm_crtc_state;
0015
0016 enum tidss_gamma_type { TIDSS_GAMMA_8BIT, TIDSS_GAMMA_10BIT };
0017
0018 struct tidss_vp_feat {
0019     struct tidss_vp_color_feat {
0020         u32 gamma_size;
0021         enum tidss_gamma_type gamma_type;
0022         bool has_ctm;
0023     } color;
0024 };
0025
0026 struct tidss_plane_feat {
0027     struct tidss_plane_color_feat {
0028         u32 encodings;
0029         u32 ranges;
0030         enum drm_color_encoding default_encoding;
0031         enum drm_color_range default_range;
0032     } color;
0033     struct tidss_plane_blend_feat {
0034         bool global_alpha;
0035     } blend;
0036 };
0037
0038 struct dispc_features_scaling {
0039     u32 in_width_max_5tap_rgb;
0040     u32 in_width_max_3tap_rgb;
0041     u32 in_width_max_5tap_yuv;
0042     u32 in_width_max_3tap_yuv;
0043     u32 upscale_limit;
0044     u32 downscale_limit_5tap;
0045     u32 downscale_limit_3tap;
0046     u32 xinc_max;
0047 };
0048
0049 struct dispc_errata {
0050     bool i2000; /* DSS Does Not Support YUV Pixel Data Formats */
0051 };
0052
0053 enum dispc_vp_bus_type {
0054     DISPC_VP_DPI,       /* DPI output */
0055     DISPC_VP_OLDI,      /* OLDI (LVDS) output */
0056     DISPC_VP_INTERNAL,  /* SoC internal routing */
0057     DISPC_VP_MAX_BUS_TYPE,
0058 };
0059
0060 enum dispc_dss_subrevision {
0061     DISPC_K2G,
0062     DISPC_AM65X,
0063     DISPC_J721E,
0064 };
0065
0066 struct dispc_features {
0067     int min_pclk_khz;
0068     int max_pclk_khz[DISPC_VP_MAX_BUS_TYPE];
0069
0070     struct dispc_features_scaling scaling;
0071
0072     enum dispc_dss_subrevision subrev;
0073
0074     const char *common;
0075     const u16 *common_regs;
0076     u32 num_vps;
0077     const char *vp_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */
0078     const char *ovr_name[TIDSS_MAX_PORTS]; /* Should match dt reg names */
0079     const char *vpclk_name[TIDSS_MAX_PORTS]; /* Should match dt clk names */
0080     const enum dispc_vp_bus_type vp_bus_type[TIDSS_MAX_PORTS];
0081     struct tidss_vp_feat vp_feat;
0082     u32 num_planes;
0083     const char *vid_name[TIDSS_MAX_PLANES]; /* Should match dt reg names */
0084     bool vid_lite[TIDSS_MAX_PLANES];
0085     u32 vid_order[TIDSS_MAX_PLANES];
0086 };
0087
0088 extern const struct dispc_features dispc_k2g_feats;
0089 extern const struct dispc_features dispc_am65x_feats;
0090 extern const struct dispc_features dispc_j721e_feats;
0091
0092 void dispc_set_irqenable(struct dispc_device *dispc, dispc_irq_t mask);
0093 dispc_irq_t dispc_read_and_clear_irqstatus(struct dispc_device *dispc);
0094
0095 void dispc_ovr_set_plane(struct dispc_device *dispc, u32 hw_plane,
0096              u32 hw_videoport, u32 x, u32 y, u32 layer);
0097 void dispc_ovr_enable_layer(struct dispc_device *dispc,
0098                 u32 hw_videoport, u32 layer, bool enable);
0099
0100 void dispc_vp_prepare(struct dispc_device *dispc, u32 hw_videoport,
0101               const struct drm_crtc_state *state);
0102 void dispc_vp_enable(struct dispc_device *dispc, u32 hw_videoport,
0103              const struct drm_crtc_state *state);
0104 void dispc_vp_disable(struct dispc_device *dispc, u32 hw_videoport);
0105 void dispc_vp_unprepare(struct dispc_device *dispc, u32 hw_videoport);
0106 bool dispc_vp_go_busy(struct dispc_device *dispc, u32 hw_videoport);
0107 void dispc_vp_go(struct dispc_device *dispc, u32 hw_videoport);
0108 int dispc_vp_bus_check(struct dispc_device *dispc, u32 hw_videoport,
0109                const struct drm_crtc_state *state);
0110 enum drm_mode_status dispc_vp_mode_valid(struct dispc_device *dispc,
0111                      u32 hw_videoport,
0112                      const struct drm_display_mode *mode);
0113 int dispc_vp_enable_clk(struct dispc_device *dispc, u32 hw_videoport);
0114 void dispc_vp_disable_clk(struct dispc_device *dispc, u32 hw_videoport);
0115 int dispc_vp_set_clk_rate(struct dispc_device *dispc, u32 hw_videoport,
0116               unsigned long rate);
0117 void dispc_vp_setup(struct dispc_device *dispc, u32 hw_videoport,
0118             const struct drm_crtc_state *state, bool newmodeset);
0119
0120 int dispc_runtime_suspend(struct dispc_device *dispc);
0121 int dispc_runtime_resume(struct dispc_device *dispc);
0122
0123 int dispc_plane_check(struct dispc_device *dispc, u32 hw_plane,
0124               const struct drm_plane_state *state,
0125               u32 hw_videoport);
0126 int dispc_plane_setup(struct dispc_device *dispc, u32 hw_plane,
0127               const struct drm_plane_state *state,
0128               u32 hw_videoport);
0129 int dispc_plane_enable(struct dispc_device *dispc, u32 hw_plane, bool enable);
0130 const u32 *dispc_plane_formats(struct dispc_device *dispc, unsigned int *len);
0131
0132 int dispc_init(struct tidss_device *tidss);
0133 void dispc_remove(struct tidss_device *tidss);
0134
0135 #endif