drm/tegra/vic.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2015, NVIDIA Corporation.
0004  */
0005
0006 #ifndef TEGRA_VIC_H
0007 #define TEGRA_VIC_H
0008
0009 /* VIC methods */
0010
0011 #define VIC_SET_FCE_UCODE_SIZE          0x0000071C
0012 #define VIC_SET_FCE_UCODE_OFFSET        0x0000072C
0013
0014 /* VIC registers */
0015
0016 #define VIC_THI_STREAMID0   0x00000030
0017 #define VIC_THI_STREAMID1   0x00000034
0018
0019 #define NV_PVIC_MISC_PRI_VIC_CG         0x000016d0
0020 #define CG_IDLE_CG_DLY_CNT(val)         ((val & 0x3f) << 0)
0021 #define CG_IDLE_CG_EN               (1 << 6)
0022 #define CG_WAKEUP_DLY_CNT(val)          ((val & 0xf) << 16)
0023
0024 #define VIC_TFBIF_TRANSCFG  0x00002044
0025 #define  TRANSCFG_ATT(i, v) (((v) & 0x3) << (i * 4))
0026 #define  TRANSCFG_SID_HW    0
0027 #define  TRANSCFG_SID_PHY   1
0028 #define  TRANSCFG_SID_FALCON    2
0029
0030 /* Firmware offsets */
0031
0032 #define VIC_UCODE_FCE_HEADER_OFFSET     (6*4)
0033 #define VIC_UCODE_FCE_DATA_OFFSET       (7*4)
0034 #define FCE_UCODE_SIZE_OFFSET           (2*4)
0035
0036 #endif /* TEGRA_VIC_H */