drm/tegra/plane.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2017 NVIDIA CORPORATION.  All rights reserved.
0004  */
0005
0006 #ifndef TEGRA_PLANE_H
0007 #define TEGRA_PLANE_H 1
0008
0009 #include <drm/drm_plane.h>
0010
0011 struct icc_path;
0012 struct tegra_bo;
0013 struct tegra_dc;
0014
0015 struct tegra_plane {
0016     struct drm_plane base;
0017     struct tegra_dc *dc;
0018     unsigned int offset;
0019     unsigned int index;
0020
0021     struct icc_path *icc_mem;
0022     struct icc_path *icc_mem_vfilter;
0023 };
0024
0025 struct tegra_cursor {
0026     struct tegra_plane base;
0027
0028     struct tegra_bo *bo;
0029     unsigned int width;
0030     unsigned int height;
0031 };
0032
0033 static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
0034 {
0035     return container_of(plane, struct tegra_plane, base);
0036 }
0037
0038 struct tegra_plane_legacy_blending_state {
0039     bool alpha;
0040     bool top;
0041 };
0042
0043 struct tegra_plane_state {
0044     struct drm_plane_state base;
0045
0046     struct host1x_bo_mapping *map[3];
0047     dma_addr_t iova[3];
0048
0049     struct tegra_bo_tiling tiling;
0050     u32 format;
0051     u32 swap;
0052
0053     bool reflect_x;
0054     bool reflect_y;
0055
0056     /* used for legacy blending support only */
0057     struct tegra_plane_legacy_blending_state blending[2];
0058     bool opaque;
0059
0060     /* bandwidths are in ICC units, i.e. kbytes/sec */
0061     u32 total_peak_memory_bandwidth;
0062     u32 peak_memory_bandwidth;
0063     u32 avg_memory_bandwidth;
0064 };
0065
0066 static inline struct tegra_plane_state *
0067 to_tegra_plane_state(struct drm_plane_state *state)
0068 {
0069     if (state)
0070         return container_of(state, struct tegra_plane_state, base);
0071
0072     return NULL;
0073 }
0074
0075 static inline const struct tegra_plane_state *
0076 to_const_tegra_plane_state(const struct drm_plane_state *state)
0077 {
0078     return to_tegra_plane_state((struct drm_plane_state *)state);
0079 }
0080
0081 extern const struct drm_plane_funcs tegra_plane_funcs;
0082
0083 int tegra_plane_prepare_fb(struct drm_plane *plane,
0084                struct drm_plane_state *state);
0085 void tegra_plane_cleanup_fb(struct drm_plane *plane,
0086                 struct drm_plane_state *state);
0087
0088 int tegra_plane_state_add(struct tegra_plane *plane,
0089               struct drm_plane_state *state);
0090
0091 int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap);
0092 bool tegra_plane_format_is_indexed(unsigned int format);
0093 bool tegra_plane_format_is_yuv(unsigned int format, unsigned int *planes, unsigned int *bpc);
0094 int tegra_plane_setup_legacy_state(struct tegra_plane *tegra,
0095                    struct tegra_plane_state *state);
0096 int tegra_plane_interconnect_init(struct tegra_plane *plane);
0097
0098 #endif /* TEGRA_PLANE_H */