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OSCL-LXR

 
 

    


0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2013 NVIDIA Corporation
0004  */
0005 
0006 #ifndef DRM_TEGRA_MIPI_PHY_H
0007 #define DRM_TEGRA_MIPI_PHY_H
0008 
0009 /*
0010  * D-PHY timing parameters
0011  *
0012  * A detailed description of these parameters can be found in the  MIPI
0013  * Alliance Specification for D-PHY, Section 5.9 "Global Operation Timing
0014  * Parameters".
0015  *
0016  * All parameters are specified in nanoseconds.
0017  */
0018 struct mipi_dphy_timing {
0019     unsigned int clkmiss;
0020     unsigned int clkpost;
0021     unsigned int clkpre;
0022     unsigned int clkprepare;
0023     unsigned int clksettle;
0024     unsigned int clktermen;
0025     unsigned int clktrail;
0026     unsigned int clkzero;
0027     unsigned int dtermen;
0028     unsigned int eot;
0029     unsigned int hsexit;
0030     unsigned int hsprepare;
0031     unsigned int hszero;
0032     unsigned int hssettle;
0033     unsigned int hsskip;
0034     unsigned int hstrail;
0035     unsigned int init;
0036     unsigned int lpx;
0037     unsigned int taget;
0038     unsigned int tago;
0039     unsigned int tasure;
0040     unsigned int wakeup;
0041 };
0042 
0043 int mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing,
0044                  unsigned long period);
0045 int mipi_dphy_timing_validate(struct mipi_dphy_timing *timing,
0046                   unsigned long period);
0047 
0048 #endif