drm/tegra/hub.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) 2017 NVIDIA CORPORATION.  All rights reserved.
0004  */
0005
0006 #ifndef TEGRA_HUB_H
0007 #define TEGRA_HUB_H 1
0008
0009 #include <drm/drm_plane.h>
0010
0011 #include "plane.h"
0012
0013 struct tegra_dc;
0014
0015 struct tegra_windowgroup {
0016     unsigned int usecount;
0017     struct mutex lock;
0018
0019     unsigned int index;
0020     struct host1x_client *parent;
0021     struct reset_control *rst;
0022 };
0023
0024 struct tegra_shared_plane {
0025     struct tegra_plane base;
0026     struct tegra_windowgroup *wgrp;
0027 };
0028
0029 static inline struct tegra_shared_plane *
0030 to_tegra_shared_plane(struct drm_plane *plane)
0031 {
0032     return container_of(plane, struct tegra_shared_plane, base.base);
0033 }
0034
0035 struct tegra_display_hub_soc {
0036     unsigned int num_wgrps;
0037     bool supports_dsc;
0038 };
0039
0040 struct tegra_display_hub {
0041     struct drm_private_obj base;
0042     struct host1x_client client;
0043     struct clk *clk_disp;
0044     struct clk *clk_dsc;
0045     struct clk *clk_hub;
0046     struct reset_control *rst;
0047
0048     unsigned int num_heads;
0049     struct clk **clk_heads;
0050
0051     const struct tegra_display_hub_soc *soc;
0052     struct tegra_windowgroup *wgrps;
0053 };
0054
0055 static inline struct tegra_display_hub *
0056 to_tegra_display_hub(struct host1x_client *client)
0057 {
0058     return container_of(client, struct tegra_display_hub, client);
0059 }
0060
0061 struct tegra_display_hub_state {
0062     struct drm_private_state base;
0063
0064     struct tegra_dc *dc;
0065     unsigned long rate;
0066     struct clk *clk;
0067 };
0068
0069 static inline struct tegra_display_hub_state *
0070 to_tegra_display_hub_state(struct drm_private_state *priv)
0071 {
0072     return container_of(priv, struct tegra_display_hub_state, base);
0073 }
0074
0075 struct tegra_plane;
0076
0077 int tegra_display_hub_prepare(struct tegra_display_hub *hub);
0078 void tegra_display_hub_cleanup(struct tegra_display_hub *hub);
0079
0080 struct drm_plane *tegra_shared_plane_create(struct drm_device *drm,
0081                         struct tegra_dc *dc,
0082                         unsigned int wgrp,
0083                         unsigned int index);
0084
0085 int tegra_display_hub_atomic_check(struct drm_device *drm,
0086                    struct drm_atomic_state *state);
0087 void tegra_display_hub_atomic_commit(struct drm_device *drm,
0088                      struct drm_atomic_state *state);
0089
0090 #define DC_CMD_IHUB_COMMON_MISC_CTL 0x068
0091 #define  LATENCY_EVENT (1 << 3)
0092
0093 #define DC_DISP_IHUB_COMMON_DISPLAY_FETCH_METER 0x451
0094 #define  CURS_SLOTS(x) (((x) & 0xff) << 8)
0095 #define  WGRP_SLOTS(x) (((x) & 0xff) << 0)
0096
0097 #endif /* TEGRA_HUB_H */