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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2012 Avionic Design GmbH
0004  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
0005  */
0006 
0007 #include <linux/clk.h>
0008 #include <linux/debugfs.h>
0009 #include <linux/delay.h>
0010 #include <linux/hdmi.h>
0011 #include <linux/math64.h>
0012 #include <linux/module.h>
0013 #include <linux/of_device.h>
0014 #include <linux/pm_opp.h>
0015 #include <linux/pm_runtime.h>
0016 #include <linux/regulator/consumer.h>
0017 #include <linux/reset.h>
0018 
0019 #include <soc/tegra/common.h>
0020 #include <sound/hdmi-codec.h>
0021 
0022 #include <drm/drm_atomic_helper.h>
0023 #include <drm/drm_crtc.h>
0024 #include <drm/drm_debugfs.h>
0025 #include <drm/drm_file.h>
0026 #include <drm/drm_fourcc.h>
0027 #include <drm/drm_probe_helper.h>
0028 #include <drm/drm_simple_kms_helper.h>
0029 
0030 #include "hda.h"
0031 #include "hdmi.h"
0032 #include "drm.h"
0033 #include "dc.h"
0034 #include "trace.h"
0035 
0036 #define HDMI_ELD_BUFFER_SIZE 96
0037 
0038 struct tmds_config {
0039     unsigned int pclk;
0040     u32 pll0;
0041     u32 pll1;
0042     u32 pe_current;
0043     u32 drive_current;
0044     u32 peak_current;
0045 };
0046 
0047 struct tegra_hdmi_config {
0048     const struct tmds_config *tmds;
0049     unsigned int num_tmds;
0050 
0051     unsigned long fuse_override_offset;
0052     u32 fuse_override_value;
0053 
0054     bool has_sor_io_peak_current;
0055     bool has_hda;
0056     bool has_hbr;
0057 };
0058 
0059 struct tegra_hdmi {
0060     struct host1x_client client;
0061     struct tegra_output output;
0062     struct device *dev;
0063 
0064     struct regulator *hdmi;
0065     struct regulator *pll;
0066     struct regulator *vdd;
0067 
0068     void __iomem *regs;
0069     unsigned int irq;
0070 
0071     struct clk *clk_parent;
0072     struct clk *clk;
0073     struct reset_control *rst;
0074 
0075     const struct tegra_hdmi_config *config;
0076 
0077     unsigned int audio_source;
0078     struct tegra_hda_format format;
0079 
0080     unsigned int pixel_clock;
0081     bool stereo;
0082     bool dvi;
0083 
0084     struct drm_info_list *debugfs_files;
0085 
0086     struct platform_device *audio_pdev;
0087     struct mutex audio_lock;
0088 };
0089 
0090 static inline struct tegra_hdmi *
0091 host1x_client_to_hdmi(struct host1x_client *client)
0092 {
0093     return container_of(client, struct tegra_hdmi, client);
0094 }
0095 
0096 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
0097 {
0098     return container_of(output, struct tegra_hdmi, output);
0099 }
0100 
0101 #define HDMI_AUDIOCLK_FREQ 216000000
0102 #define HDMI_REKEY_DEFAULT 56
0103 
0104 enum {
0105     AUTO = 0,
0106     SPDIF,
0107     HDA,
0108 };
0109 
0110 static inline u32 tegra_hdmi_readl(struct tegra_hdmi *hdmi,
0111                    unsigned int offset)
0112 {
0113     u32 value = readl(hdmi->regs + (offset << 2));
0114 
0115     trace_hdmi_readl(hdmi->dev, offset, value);
0116 
0117     return value;
0118 }
0119 
0120 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, u32 value,
0121                      unsigned int offset)
0122 {
0123     trace_hdmi_writel(hdmi->dev, offset, value);
0124     writel(value, hdmi->regs + (offset << 2));
0125 }
0126 
0127 struct tegra_hdmi_audio_config {
0128     unsigned int n;
0129     unsigned int cts;
0130     unsigned int aval;
0131 };
0132 
0133 static const struct tmds_config tegra20_tmds_config[] = {
0134     { /* slow pixel clock modes */
0135         .pclk = 27000000,
0136         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
0137             SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
0138             SOR_PLL_TX_REG_LOAD(3),
0139         .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
0140         .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
0141             PE_CURRENT1(PE_CURRENT_0_0_mA) |
0142             PE_CURRENT2(PE_CURRENT_0_0_mA) |
0143             PE_CURRENT3(PE_CURRENT_0_0_mA),
0144         .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
0145             DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
0146             DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
0147             DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
0148     },
0149     { /* high pixel clock modes */
0150         .pclk = UINT_MAX,
0151         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
0152             SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
0153             SOR_PLL_TX_REG_LOAD(3),
0154         .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
0155         .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
0156             PE_CURRENT1(PE_CURRENT_6_0_mA) |
0157             PE_CURRENT2(PE_CURRENT_6_0_mA) |
0158             PE_CURRENT3(PE_CURRENT_6_0_mA),
0159         .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
0160             DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
0161             DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
0162             DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
0163     },
0164 };
0165 
0166 static const struct tmds_config tegra30_tmds_config[] = {
0167     { /* 480p modes */
0168         .pclk = 27000000,
0169         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
0170             SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
0171             SOR_PLL_TX_REG_LOAD(0),
0172         .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
0173         .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
0174             PE_CURRENT1(PE_CURRENT_0_0_mA) |
0175             PE_CURRENT2(PE_CURRENT_0_0_mA) |
0176             PE_CURRENT3(PE_CURRENT_0_0_mA),
0177         .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
0178             DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
0179             DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
0180             DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
0181     }, { /* 720p modes */
0182         .pclk = 74250000,
0183         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
0184             SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
0185             SOR_PLL_TX_REG_LOAD(0),
0186         .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
0187         .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
0188             PE_CURRENT1(PE_CURRENT_5_0_mA) |
0189             PE_CURRENT2(PE_CURRENT_5_0_mA) |
0190             PE_CURRENT3(PE_CURRENT_5_0_mA),
0191         .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
0192             DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
0193             DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
0194             DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
0195     }, { /* 1080p modes */
0196         .pclk = UINT_MAX,
0197         .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
0198             SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
0199             SOR_PLL_TX_REG_LOAD(0),
0200         .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
0201         .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
0202             PE_CURRENT1(PE_CURRENT_5_0_mA) |
0203             PE_CURRENT2(PE_CURRENT_5_0_mA) |
0204             PE_CURRENT3(PE_CURRENT_5_0_mA),
0205         .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
0206             DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
0207             DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
0208             DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
0209     },
0210 };
0211 
0212 static const struct tmds_config tegra114_tmds_config[] = {
0213     { /* 480p/576p / 25.2MHz/27MHz modes */
0214         .pclk = 27000000,
0215         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
0216             SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
0217         .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
0218         .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
0219             PE_CURRENT1(PE_CURRENT_0_mA_T114) |
0220             PE_CURRENT2(PE_CURRENT_0_mA_T114) |
0221             PE_CURRENT3(PE_CURRENT_0_mA_T114),
0222         .drive_current =
0223             DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
0224             DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
0225             DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
0226             DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
0227         .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
0228             PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
0229             PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
0230             PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
0231     }, { /* 720p / 74.25MHz modes */
0232         .pclk = 74250000,
0233         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
0234             SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
0235         .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
0236             SOR_PLL_TMDS_TERMADJ(0),
0237         .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
0238             PE_CURRENT1(PE_CURRENT_15_mA_T114) |
0239             PE_CURRENT2(PE_CURRENT_15_mA_T114) |
0240             PE_CURRENT3(PE_CURRENT_15_mA_T114),
0241         .drive_current =
0242             DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
0243             DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
0244             DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
0245             DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
0246         .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
0247             PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
0248             PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
0249             PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
0250     }, { /* 1080p / 148.5MHz modes */
0251         .pclk = 148500000,
0252         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
0253             SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
0254         .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
0255             SOR_PLL_TMDS_TERMADJ(0),
0256         .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
0257             PE_CURRENT1(PE_CURRENT_10_mA_T114) |
0258             PE_CURRENT2(PE_CURRENT_10_mA_T114) |
0259             PE_CURRENT3(PE_CURRENT_10_mA_T114),
0260         .drive_current =
0261             DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
0262             DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
0263             DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
0264             DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
0265         .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
0266             PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
0267             PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
0268             PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
0269     }, { /* 225/297MHz modes */
0270         .pclk = UINT_MAX,
0271         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
0272             SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
0273         .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
0274             | SOR_PLL_TMDS_TERM_ENABLE,
0275         .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
0276             PE_CURRENT1(PE_CURRENT_0_mA_T114) |
0277             PE_CURRENT2(PE_CURRENT_0_mA_T114) |
0278             PE_CURRENT3(PE_CURRENT_0_mA_T114),
0279         .drive_current =
0280             DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
0281             DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
0282             DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
0283             DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
0284         .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
0285             PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
0286             PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
0287             PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
0288     },
0289 };
0290 
0291 static const struct tmds_config tegra124_tmds_config[] = {
0292     { /* 480p/576p / 25.2MHz/27MHz modes */
0293         .pclk = 27000000,
0294         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
0295             SOR_PLL_VCOCAP(0) | SOR_PLL_RESISTORSEL,
0296         .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
0297         .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
0298             PE_CURRENT1(PE_CURRENT_0_mA_T114) |
0299             PE_CURRENT2(PE_CURRENT_0_mA_T114) |
0300             PE_CURRENT3(PE_CURRENT_0_mA_T114),
0301         .drive_current =
0302             DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
0303             DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
0304             DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
0305             DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
0306         .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
0307             PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
0308             PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
0309             PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
0310     }, { /* 720p / 74.25MHz modes */
0311         .pclk = 74250000,
0312         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
0313             SOR_PLL_VCOCAP(1) | SOR_PLL_RESISTORSEL,
0314         .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
0315             SOR_PLL_TMDS_TERMADJ(0),
0316         .pe_current = PE_CURRENT0(PE_CURRENT_15_mA_T114) |
0317             PE_CURRENT1(PE_CURRENT_15_mA_T114) |
0318             PE_CURRENT2(PE_CURRENT_15_mA_T114) |
0319             PE_CURRENT3(PE_CURRENT_15_mA_T114),
0320         .drive_current =
0321             DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_10_400_mA_T114) |
0322             DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_10_400_mA_T114) |
0323             DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_10_400_mA_T114) |
0324             DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_10_400_mA_T114),
0325         .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
0326             PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
0327             PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
0328             PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
0329     }, { /* 1080p / 148.5MHz modes */
0330         .pclk = 148500000,
0331         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
0332             SOR_PLL_VCOCAP(3) | SOR_PLL_RESISTORSEL,
0333         .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
0334             SOR_PLL_TMDS_TERMADJ(0),
0335         .pe_current = PE_CURRENT0(PE_CURRENT_10_mA_T114) |
0336             PE_CURRENT1(PE_CURRENT_10_mA_T114) |
0337             PE_CURRENT2(PE_CURRENT_10_mA_T114) |
0338             PE_CURRENT3(PE_CURRENT_10_mA_T114),
0339         .drive_current =
0340             DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_12_400_mA_T114) |
0341             DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_12_400_mA_T114) |
0342             DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_12_400_mA_T114) |
0343             DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_12_400_mA_T114),
0344         .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_0_000_mA) |
0345             PEAK_CURRENT_LANE1(PEAK_CURRENT_0_000_mA) |
0346             PEAK_CURRENT_LANE2(PEAK_CURRENT_0_000_mA) |
0347             PEAK_CURRENT_LANE3(PEAK_CURRENT_0_000_mA),
0348     }, { /* 225/297MHz modes */
0349         .pclk = UINT_MAX,
0350         .pll0 = SOR_PLL_ICHPMP(1) | SOR_PLL_BG_V17_S(3) |
0351             SOR_PLL_VCOCAP(0xf) | SOR_PLL_RESISTORSEL,
0352         .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
0353             | SOR_PLL_TMDS_TERM_ENABLE,
0354         .pe_current = PE_CURRENT0(PE_CURRENT_0_mA_T114) |
0355             PE_CURRENT1(PE_CURRENT_0_mA_T114) |
0356             PE_CURRENT2(PE_CURRENT_0_mA_T114) |
0357             PE_CURRENT3(PE_CURRENT_0_mA_T114),
0358         .drive_current =
0359             DRIVE_CURRENT_LANE0_T114(DRIVE_CURRENT_25_200_mA_T114) |
0360             DRIVE_CURRENT_LANE1_T114(DRIVE_CURRENT_25_200_mA_T114) |
0361             DRIVE_CURRENT_LANE2_T114(DRIVE_CURRENT_25_200_mA_T114) |
0362             DRIVE_CURRENT_LANE3_T114(DRIVE_CURRENT_19_200_mA_T114),
0363         .peak_current = PEAK_CURRENT_LANE0(PEAK_CURRENT_3_000_mA) |
0364             PEAK_CURRENT_LANE1(PEAK_CURRENT_3_000_mA) |
0365             PEAK_CURRENT_LANE2(PEAK_CURRENT_3_000_mA) |
0366             PEAK_CURRENT_LANE3(PEAK_CURRENT_0_800_mA),
0367     },
0368 };
0369 
0370 static void tegra_hdmi_audio_lock(struct tegra_hdmi *hdmi)
0371 {
0372     mutex_lock(&hdmi->audio_lock);
0373     disable_irq(hdmi->irq);
0374 }
0375 
0376 static void tegra_hdmi_audio_unlock(struct tegra_hdmi *hdmi)
0377 {
0378     enable_irq(hdmi->irq);
0379     mutex_unlock(&hdmi->audio_lock);
0380 }
0381 
0382 static int
0383 tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pix_clock,
0384                 struct tegra_hdmi_audio_config *config)
0385 {
0386     const unsigned int afreq = 128 * audio_freq;
0387     const unsigned int min_n = afreq / 1500;
0388     const unsigned int max_n = afreq / 300;
0389     const unsigned int ideal_n = afreq / 1000;
0390     int64_t min_err = (uint64_t)-1 >> 1;
0391     unsigned int min_delta = -1;
0392     int n;
0393 
0394     memset(config, 0, sizeof(*config));
0395     config->n = -1;
0396 
0397     for (n = min_n; n <= max_n; n++) {
0398         uint64_t cts_f, aval_f;
0399         unsigned int delta;
0400         int64_t cts, err;
0401 
0402         /* compute aval in 48.16 fixed point */
0403         aval_f = ((int64_t)24000000 << 16) * n;
0404         do_div(aval_f, afreq);
0405         /* It should round without any rest */
0406         if (aval_f & 0xFFFF)
0407             continue;
0408 
0409         /* Compute cts in 48.16 fixed point */
0410         cts_f = ((int64_t)pix_clock << 16) * n;
0411         do_div(cts_f, afreq);
0412         /* Round it to the nearest integer */
0413         cts = (cts_f & ~0xFFFF) + ((cts_f & BIT(15)) << 1);
0414 
0415         delta = abs(n - ideal_n);
0416 
0417         /* Compute the absolute error */
0418         err = abs((int64_t)cts_f - cts);
0419         if (err < min_err || (err == min_err && delta < min_delta)) {
0420             config->n = n;
0421             config->cts = cts >> 16;
0422             config->aval = aval_f >> 16;
0423             min_delta = delta;
0424             min_err = err;
0425         }
0426     }
0427 
0428     return config->n != -1 ? 0 : -EINVAL;
0429 }
0430 
0431 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
0432 {
0433     const unsigned int freqs[] = {
0434         32000, 44100, 48000, 88200, 96000, 176400, 192000
0435     };
0436     unsigned int i;
0437 
0438     for (i = 0; i < ARRAY_SIZE(freqs); i++) {
0439         unsigned int f = freqs[i];
0440         unsigned int eight_half;
0441         unsigned int delta;
0442         u32 value;
0443 
0444         if (f > 96000)
0445             delta = 2;
0446         else if (f > 48000)
0447             delta = 6;
0448         else
0449             delta = 9;
0450 
0451         eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
0452         value = AUDIO_FS_LOW(eight_half - delta) |
0453             AUDIO_FS_HIGH(eight_half + delta);
0454         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
0455     }
0456 }
0457 
0458 static void tegra_hdmi_write_aval(struct tegra_hdmi *hdmi, u32 value)
0459 {
0460     static const struct {
0461         unsigned int sample_rate;
0462         unsigned int offset;
0463     } regs[] = {
0464         {  32000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 },
0465         {  44100, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 },
0466         {  48000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 },
0467         {  88200, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 },
0468         {  96000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 },
0469         { 176400, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 },
0470         { 192000, HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 },
0471     };
0472     unsigned int i;
0473 
0474     for (i = 0; i < ARRAY_SIZE(regs); i++) {
0475         if (regs[i].sample_rate == hdmi->format.sample_rate) {
0476             tegra_hdmi_writel(hdmi, value, regs[i].offset);
0477             break;
0478         }
0479     }
0480 }
0481 
0482 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi)
0483 {
0484     struct tegra_hdmi_audio_config config;
0485     u32 source, value;
0486     int err;
0487 
0488     switch (hdmi->audio_source) {
0489     case HDA:
0490         if (hdmi->config->has_hda)
0491             source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
0492         else
0493             return -EINVAL;
0494 
0495         break;
0496 
0497     case SPDIF:
0498         if (hdmi->config->has_hda)
0499             source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
0500         else
0501             source = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
0502         break;
0503 
0504     default:
0505         if (hdmi->config->has_hda)
0506             source = SOR_AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
0507         else
0508             source = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
0509         break;
0510     }
0511 
0512     /*
0513      * Tegra30 and later use a slightly modified version of the register
0514      * layout to accomodate for changes related to supporting HDA as the
0515      * audio input source for HDMI. The source select field has moved to
0516      * the SOR_AUDIO_CNTRL0 register, but the error tolerance and frames
0517      * per block fields remain in the AUDIO_CNTRL0 register.
0518      */
0519     if (hdmi->config->has_hda) {
0520         /*
0521          * Inject null samples into the audio FIFO for every frame in
0522          * which the codec did not receive any samples. This applies
0523          * to stereo LPCM only.
0524          *
0525          * XXX: This seems to be a remnant of MCP days when this was
0526          * used to work around issues with monitors not being able to
0527          * play back system startup sounds early. It is possibly not
0528          * needed on Linux at all.
0529          */
0530         if (hdmi->format.channels == 2)
0531             value = SOR_AUDIO_CNTRL0_INJECT_NULLSMPL;
0532         else
0533             value = 0;
0534 
0535         value |= source;
0536 
0537         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
0538     }
0539 
0540     /*
0541      * On Tegra20, HDA is not a supported audio source and the source
0542      * select field is part of the AUDIO_CNTRL0 register.
0543      */
0544     value = AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0) |
0545         AUDIO_CNTRL0_ERROR_TOLERANCE(6);
0546 
0547     if (!hdmi->config->has_hda)
0548         value |= source;
0549 
0550     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
0551 
0552     /*
0553      * Advertise support for High Bit-Rate on Tegra114 and later.
0554      */
0555     if (hdmi->config->has_hbr) {
0556         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
0557         value |= SOR_AUDIO_SPARE0_HBR_ENABLE;
0558         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_SPARE0);
0559     }
0560 
0561     err = tegra_hdmi_get_audio_config(hdmi->format.sample_rate,
0562                       hdmi->pixel_clock, &config);
0563     if (err < 0) {
0564         dev_err(hdmi->dev,
0565             "cannot set audio to %u Hz at %u Hz pixel clock\n",
0566             hdmi->format.sample_rate, hdmi->pixel_clock);
0567         return err;
0568     }
0569 
0570     dev_dbg(hdmi->dev, "audio: pixclk=%u, n=%u, cts=%u, aval=%u\n",
0571         hdmi->pixel_clock, config.n, config.cts, config.aval);
0572 
0573     tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
0574 
0575     value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
0576         AUDIO_N_VALUE(config.n - 1);
0577     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
0578 
0579     tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config.n) | ACR_ENABLE,
0580               HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
0581 
0582     tegra_hdmi_writel(hdmi, ACR_SUBPACK_CTS(config.cts),
0583               HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
0584 
0585     value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
0586     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
0587 
0588     value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
0589     value &= ~AUDIO_N_RESETF;
0590     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
0591 
0592     if (hdmi->config->has_hda)
0593         tegra_hdmi_write_aval(hdmi, config.aval);
0594 
0595     tegra_hdmi_setup_audio_fs_tables(hdmi);
0596 
0597     return 0;
0598 }
0599 
0600 static void tegra_hdmi_disable_audio(struct tegra_hdmi *hdmi)
0601 {
0602     u32 value;
0603 
0604     value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
0605     value &= ~GENERIC_CTRL_AUDIO;
0606     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
0607 }
0608 
0609 static void tegra_hdmi_enable_audio(struct tegra_hdmi *hdmi)
0610 {
0611     u32 value;
0612 
0613     value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
0614     value |= GENERIC_CTRL_AUDIO;
0615     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
0616 }
0617 
0618 static void tegra_hdmi_write_eld(struct tegra_hdmi *hdmi)
0619 {
0620     size_t length = drm_eld_size(hdmi->output.connector.eld), i;
0621     u32 value;
0622 
0623     for (i = 0; i < length; i++)
0624         tegra_hdmi_writel(hdmi, i << 8 | hdmi->output.connector.eld[i],
0625                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
0626 
0627     /*
0628      * The HDA codec will always report an ELD buffer size of 96 bytes and
0629      * the HDA codec driver will check that each byte read from the buffer
0630      * is valid. Therefore every byte must be written, even if no 96 bytes
0631      * were parsed from EDID.
0632      */
0633     for (i = length; i < HDMI_ELD_BUFFER_SIZE; i++)
0634         tegra_hdmi_writel(hdmi, i << 8 | 0,
0635                   HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
0636 
0637     value = SOR_AUDIO_HDA_PRESENSE_VALID | SOR_AUDIO_HDA_PRESENSE_PRESENT;
0638     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
0639 }
0640 
0641 static inline u32 tegra_hdmi_subpack(const u8 *ptr, size_t size)
0642 {
0643     u32 value = 0;
0644     size_t i;
0645 
0646     for (i = size; i > 0; i--)
0647         value = (value << 8) | ptr[i - 1];
0648 
0649     return value;
0650 }
0651 
0652 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
0653                       size_t size)
0654 {
0655     const u8 *ptr = data;
0656     unsigned long offset;
0657     size_t i, j;
0658     u32 value;
0659 
0660     switch (ptr[0]) {
0661     case HDMI_INFOFRAME_TYPE_AVI:
0662         offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
0663         break;
0664 
0665     case HDMI_INFOFRAME_TYPE_AUDIO:
0666         offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
0667         break;
0668 
0669     case HDMI_INFOFRAME_TYPE_VENDOR:
0670         offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
0671         break;
0672 
0673     default:
0674         dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
0675             ptr[0]);
0676         return;
0677     }
0678 
0679     value = INFOFRAME_HEADER_TYPE(ptr[0]) |
0680         INFOFRAME_HEADER_VERSION(ptr[1]) |
0681         INFOFRAME_HEADER_LEN(ptr[2]);
0682     tegra_hdmi_writel(hdmi, value, offset);
0683     offset++;
0684 
0685     /*
0686      * Each subpack contains 7 bytes, divided into:
0687      * - subpack_low: bytes 0 - 3
0688      * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
0689      */
0690     for (i = 3, j = 0; i < size; i += 7, j += 8) {
0691         size_t rem = size - i, num = min_t(size_t, rem, 4);
0692 
0693         value = tegra_hdmi_subpack(&ptr[i], num);
0694         tegra_hdmi_writel(hdmi, value, offset++);
0695 
0696         num = min_t(size_t, rem - num, 3);
0697 
0698         value = tegra_hdmi_subpack(&ptr[i + 4], num);
0699         tegra_hdmi_writel(hdmi, value, offset++);
0700     }
0701 }
0702 
0703 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
0704                        struct drm_display_mode *mode)
0705 {
0706     struct hdmi_avi_infoframe frame;
0707     u8 buffer[17];
0708     ssize_t err;
0709 
0710     err = drm_hdmi_avi_infoframe_from_display_mode(&frame,
0711                                &hdmi->output.connector, mode);
0712     if (err < 0) {
0713         dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
0714         return;
0715     }
0716 
0717     err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
0718     if (err < 0) {
0719         dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
0720         return;
0721     }
0722 
0723     tegra_hdmi_write_infopack(hdmi, buffer, err);
0724 }
0725 
0726 static void tegra_hdmi_disable_avi_infoframe(struct tegra_hdmi *hdmi)
0727 {
0728     u32 value;
0729 
0730     value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
0731     value &= ~INFOFRAME_CTRL_ENABLE;
0732     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
0733 }
0734 
0735 static void tegra_hdmi_enable_avi_infoframe(struct tegra_hdmi *hdmi)
0736 {
0737     u32 value;
0738 
0739     value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
0740     value |= INFOFRAME_CTRL_ENABLE;
0741     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
0742 }
0743 
0744 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
0745 {
0746     struct hdmi_audio_infoframe frame;
0747     u8 buffer[14];
0748     ssize_t err;
0749 
0750     err = hdmi_audio_infoframe_init(&frame);
0751     if (err < 0) {
0752         dev_err(hdmi->dev, "failed to setup audio infoframe: %zd\n",
0753             err);
0754         return;
0755     }
0756 
0757     frame.channels = hdmi->format.channels;
0758 
0759     err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
0760     if (err < 0) {
0761         dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
0762             err);
0763         return;
0764     }
0765 
0766     /*
0767      * The audio infoframe has only one set of subpack registers, so the
0768      * infoframe needs to be truncated. One set of subpack registers can
0769      * contain 7 bytes. Including the 3 byte header only the first 10
0770      * bytes can be programmed.
0771      */
0772     tegra_hdmi_write_infopack(hdmi, buffer, min_t(size_t, 10, err));
0773 }
0774 
0775 static void tegra_hdmi_disable_audio_infoframe(struct tegra_hdmi *hdmi)
0776 {
0777     u32 value;
0778 
0779     value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
0780     value &= ~INFOFRAME_CTRL_ENABLE;
0781     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
0782 }
0783 
0784 static void tegra_hdmi_enable_audio_infoframe(struct tegra_hdmi *hdmi)
0785 {
0786     u32 value;
0787 
0788     value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
0789     value |= INFOFRAME_CTRL_ENABLE;
0790     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
0791 }
0792 
0793 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
0794 {
0795     struct hdmi_vendor_infoframe frame;
0796     u8 buffer[10];
0797     ssize_t err;
0798 
0799     hdmi_vendor_infoframe_init(&frame);
0800     frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
0801 
0802     err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
0803     if (err < 0) {
0804         dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
0805             err);
0806         return;
0807     }
0808 
0809     tegra_hdmi_write_infopack(hdmi, buffer, err);
0810 }
0811 
0812 static void tegra_hdmi_disable_stereo_infoframe(struct tegra_hdmi *hdmi)
0813 {
0814     u32 value;
0815 
0816     value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
0817     value &= ~GENERIC_CTRL_ENABLE;
0818     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
0819 }
0820 
0821 static void tegra_hdmi_enable_stereo_infoframe(struct tegra_hdmi *hdmi)
0822 {
0823     u32 value;
0824 
0825     value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
0826     value |= GENERIC_CTRL_ENABLE;
0827     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
0828 }
0829 
0830 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
0831                   const struct tmds_config *tmds)
0832 {
0833     u32 value;
0834 
0835     tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
0836     tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
0837     tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
0838 
0839     tegra_hdmi_writel(hdmi, tmds->drive_current,
0840               HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
0841 
0842     value = tegra_hdmi_readl(hdmi, hdmi->config->fuse_override_offset);
0843     value |= hdmi->config->fuse_override_value;
0844     tegra_hdmi_writel(hdmi, value, hdmi->config->fuse_override_offset);
0845 
0846     if (hdmi->config->has_sor_io_peak_current)
0847         tegra_hdmi_writel(hdmi, tmds->peak_current,
0848                   HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT);
0849 }
0850 
0851 static int tegra_hdmi_reconfigure_audio(struct tegra_hdmi *hdmi)
0852 {
0853     int err;
0854 
0855     err = tegra_hdmi_setup_audio(hdmi);
0856     if (err < 0) {
0857         tegra_hdmi_disable_audio_infoframe(hdmi);
0858         tegra_hdmi_disable_audio(hdmi);
0859     } else {
0860         tegra_hdmi_setup_audio_infoframe(hdmi);
0861         tegra_hdmi_enable_audio_infoframe(hdmi);
0862         tegra_hdmi_enable_audio(hdmi);
0863     }
0864 
0865     return err;
0866 }
0867 
0868 static bool tegra_output_is_hdmi(struct tegra_output *output)
0869 {
0870     struct edid *edid;
0871 
0872     if (!output->connector.edid_blob_ptr)
0873         return false;
0874 
0875     edid = (struct edid *)output->connector.edid_blob_ptr->data;
0876 
0877     return drm_detect_hdmi_monitor(edid);
0878 }
0879 
0880 static enum drm_connector_status
0881 tegra_hdmi_connector_detect(struct drm_connector *connector, bool force)
0882 {
0883     struct tegra_output *output = connector_to_output(connector);
0884     struct tegra_hdmi *hdmi = to_hdmi(output);
0885     enum drm_connector_status status;
0886 
0887     status = tegra_output_connector_detect(connector, force);
0888     if (status == connector_status_connected)
0889         return status;
0890 
0891     tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
0892     return status;
0893 }
0894 
0895 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
0896 
0897 static const struct debugfs_reg32 tegra_hdmi_regs[] = {
0898     DEBUGFS_REG32(HDMI_CTXSW),
0899     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE0),
0900     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE1),
0901     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_STATE2),
0902     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_MSB),
0903     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AN_LSB),
0904     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_MSB),
0905     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CN_LSB),
0906     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB),
0907     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB),
0908     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB),
0909     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB),
0910     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB),
0911     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB),
0912     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB),
0913     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB),
0914     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CTRL),
0915     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CMODE),
0916     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB),
0917     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB),
0918     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB),
0919     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2),
0920     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1),
0921     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_RI),
0922     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_MSB),
0923     DEBUGFS_REG32(HDMI_NV_PDISP_RG_HDCP_CS_LSB),
0924     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU0),
0925     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0),
0926     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU1),
0927     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_EMU2),
0928     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL),
0929     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS),
0930     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER),
0931     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW),
0932     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH),
0933     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL),
0934     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS),
0935     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER),
0936     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW),
0937     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH),
0938     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW),
0939     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH),
0940     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_CTRL),
0941     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_STATUS),
0942     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_HEADER),
0943     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW),
0944     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH),
0945     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW),
0946     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH),
0947     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW),
0948     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH),
0949     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW),
0950     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH),
0951     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_CTRL),
0952     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW),
0953     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH),
0954     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW),
0955     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH),
0956     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW),
0957     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH),
0958     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW),
0959     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH),
0960     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW),
0961     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH),
0962     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW),
0963     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH),
0964     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW),
0965     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH),
0966     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CTRL),
0967     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT),
0968     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW),
0969     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_CTRL),
0970     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_STATUS),
0971     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_GCP_SUBPACK),
0972     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1),
0973     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2),
0974     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU0),
0975     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1),
0976     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_EMU1_RDATA),
0977     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPARE),
0978     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1),
0979     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2),
0980     DEBUGFS_REG32(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL),
0981     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CAP),
0982     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PWR),
0983     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TEST),
0984     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL0),
0985     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL1),
0986     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_PLL2),
0987     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CSTM),
0988     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LVDS),
0989     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCA),
0990     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CRCB),
0991     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_BLANK),
0992     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_CTL),
0993     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(0)),
0994     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(1)),
0995     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(2)),
0996     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(3)),
0997     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(4)),
0998     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(5)),
0999     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(6)),
1000     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(7)),
1001     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(8)),
1002     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(9)),
1003     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(10)),
1004     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(11)),
1005     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(12)),
1006     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(13)),
1007     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(14)),
1008     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_SEQ_INST(15)),
1009     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA0),
1010     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_VCRCA1),
1011     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA0),
1012     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_CCRCA1),
1013     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA0),
1014     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_EDATAA1),
1015     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA0),
1016     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_COUNTA1),
1017     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA0),
1018     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_DEBUGA1),
1019     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_TRIG),
1020     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_MSCHECK),
1021     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT),
1022     DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG0),
1023     DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG1),
1024     DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_DEBUG2),
1025     DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(0)),
1026     DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(1)),
1027     DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(2)),
1028     DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(3)),
1029     DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(4)),
1030     DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(5)),
1031     DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_FS(6)),
1032     DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH),
1033     DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_THRESHOLD),
1034     DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_CNTRL0),
1035     DEBUGFS_REG32(HDMI_NV_PDISP_AUDIO_N),
1036     DEBUGFS_REG32(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING),
1037     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_REFCLK),
1038     DEBUGFS_REG32(HDMI_NV_PDISP_CRC_CONTROL),
1039     DEBUGFS_REG32(HDMI_NV_PDISP_INPUT_CONTROL),
1040     DEBUGFS_REG32(HDMI_NV_PDISP_SCRATCH),
1041     DEBUGFS_REG32(HDMI_NV_PDISP_PE_CURRENT),
1042     DEBUGFS_REG32(HDMI_NV_PDISP_KEY_CTRL),
1043     DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG0),
1044     DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG1),
1045     DEBUGFS_REG32(HDMI_NV_PDISP_KEY_DEBUG2),
1046     DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_0),
1047     DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_1),
1048     DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_2),
1049     DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_3),
1050     DEBUGFS_REG32(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG),
1051     DEBUGFS_REG32(HDMI_NV_PDISP_KEY_SKEY_INDEX),
1052     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0),
1053     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_SPARE0),
1054     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0),
1055     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH1),
1056     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR),
1057     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE),
1058     DEBUGFS_REG32(HDMI_NV_PDISP_INT_STATUS),
1059     DEBUGFS_REG32(HDMI_NV_PDISP_INT_MASK),
1060     DEBUGFS_REG32(HDMI_NV_PDISP_INT_ENABLE),
1061     DEBUGFS_REG32(HDMI_NV_PDISP_SOR_IO_PEAK_CURRENT),
1062 };
1063 
1064 static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
1065 {
1066     struct drm_info_node *node = s->private;
1067     struct tegra_hdmi *hdmi = node->info_ent->data;
1068     struct drm_crtc *crtc = hdmi->output.encoder.crtc;
1069     struct drm_device *drm = node->minor->dev;
1070     unsigned int i;
1071     int err = 0;
1072 
1073     drm_modeset_lock_all(drm);
1074 
1075     if (!crtc || !crtc->state->active) {
1076         err = -EBUSY;
1077         goto unlock;
1078     }
1079 
1080     for (i = 0; i < ARRAY_SIZE(tegra_hdmi_regs); i++) {
1081         unsigned int offset = tegra_hdmi_regs[i].offset;
1082 
1083         seq_printf(s, "%-56s %#05x %08x\n", tegra_hdmi_regs[i].name,
1084                offset, tegra_hdmi_readl(hdmi, offset));
1085     }
1086 
1087 unlock:
1088     drm_modeset_unlock_all(drm);
1089     return err;
1090 }
1091 
1092 static struct drm_info_list debugfs_files[] = {
1093     { "regs", tegra_hdmi_show_regs, 0, NULL },
1094 };
1095 
1096 static int tegra_hdmi_late_register(struct drm_connector *connector)
1097 {
1098     struct tegra_output *output = connector_to_output(connector);
1099     unsigned int i, count = ARRAY_SIZE(debugfs_files);
1100     struct drm_minor *minor = connector->dev->primary;
1101     struct dentry *root = connector->debugfs_entry;
1102     struct tegra_hdmi *hdmi = to_hdmi(output);
1103 
1104     hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1105                       GFP_KERNEL);
1106     if (!hdmi->debugfs_files)
1107         return -ENOMEM;
1108 
1109     for (i = 0; i < count; i++)
1110         hdmi->debugfs_files[i].data = hdmi;
1111 
1112     drm_debugfs_create_files(hdmi->debugfs_files, count, root, minor);
1113 
1114     return 0;
1115 }
1116 
1117 static void tegra_hdmi_early_unregister(struct drm_connector *connector)
1118 {
1119     struct tegra_output *output = connector_to_output(connector);
1120     struct drm_minor *minor = connector->dev->primary;
1121     unsigned int count = ARRAY_SIZE(debugfs_files);
1122     struct tegra_hdmi *hdmi = to_hdmi(output);
1123 
1124     drm_debugfs_remove_files(hdmi->debugfs_files, count, minor);
1125     kfree(hdmi->debugfs_files);
1126     hdmi->debugfs_files = NULL;
1127 }
1128 
1129 static const struct drm_connector_funcs tegra_hdmi_connector_funcs = {
1130     .reset = drm_atomic_helper_connector_reset,
1131     .detect = tegra_hdmi_connector_detect,
1132     .fill_modes = drm_helper_probe_single_connector_modes,
1133     .destroy = tegra_output_connector_destroy,
1134     .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1135     .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1136     .late_register = tegra_hdmi_late_register,
1137     .early_unregister = tegra_hdmi_early_unregister,
1138 };
1139 
1140 static enum drm_mode_status
1141 tegra_hdmi_connector_mode_valid(struct drm_connector *connector,
1142                 struct drm_display_mode *mode)
1143 {
1144     struct tegra_output *output = connector_to_output(connector);
1145     struct tegra_hdmi *hdmi = to_hdmi(output);
1146     unsigned long pclk = mode->clock * 1000;
1147     enum drm_mode_status status = MODE_OK;
1148     struct clk *parent;
1149     long err;
1150 
1151     parent = clk_get_parent(hdmi->clk_parent);
1152 
1153     err = clk_round_rate(parent, pclk * 4);
1154     if (err <= 0)
1155         status = MODE_NOCLOCK;
1156 
1157     return status;
1158 }
1159 
1160 static const struct drm_connector_helper_funcs
1161 tegra_hdmi_connector_helper_funcs = {
1162     .get_modes = tegra_output_connector_get_modes,
1163     .mode_valid = tegra_hdmi_connector_mode_valid,
1164 };
1165 
1166 static void tegra_hdmi_encoder_disable(struct drm_encoder *encoder)
1167 {
1168     struct tegra_output *output = encoder_to_output(encoder);
1169     struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1170     struct tegra_hdmi *hdmi = to_hdmi(output);
1171     u32 value;
1172     int err;
1173 
1174     tegra_hdmi_audio_lock(hdmi);
1175 
1176     /*
1177      * The following accesses registers of the display controller, so make
1178      * sure it's only executed when the output is attached to one.
1179      */
1180     if (dc) {
1181         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1182         value &= ~HDMI_ENABLE;
1183         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1184 
1185         tegra_dc_commit(dc);
1186     }
1187 
1188     if (!hdmi->dvi) {
1189         if (hdmi->stereo)
1190             tegra_hdmi_disable_stereo_infoframe(hdmi);
1191 
1192         tegra_hdmi_disable_audio_infoframe(hdmi);
1193         tegra_hdmi_disable_avi_infoframe(hdmi);
1194         tegra_hdmi_disable_audio(hdmi);
1195     }
1196 
1197     tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_ENABLE);
1198     tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_INT_MASK);
1199 
1200     hdmi->pixel_clock = 0;
1201 
1202     tegra_hdmi_audio_unlock(hdmi);
1203 
1204     err = host1x_client_suspend(&hdmi->client);
1205     if (err < 0)
1206         dev_err(hdmi->dev, "failed to suspend: %d\n", err);
1207 }
1208 
1209 static void tegra_hdmi_encoder_enable(struct drm_encoder *encoder)
1210 {
1211     struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
1212     unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
1213     struct tegra_output *output = encoder_to_output(encoder);
1214     struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1215     struct tegra_hdmi *hdmi = to_hdmi(output);
1216     unsigned int pulse_start, div82;
1217     int retries = 1000;
1218     u32 value;
1219     int err;
1220 
1221     err = host1x_client_resume(&hdmi->client);
1222     if (err < 0) {
1223         dev_err(hdmi->dev, "failed to resume: %d\n", err);
1224         return;
1225     }
1226 
1227     tegra_hdmi_audio_lock(hdmi);
1228 
1229     /*
1230      * Enable and unmask the HDA codec SCRATCH0 register interrupt. This
1231      * is used for interoperability between the HDA codec driver and the
1232      * HDMI driver.
1233      */
1234     tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_ENABLE);
1235     tegra_hdmi_writel(hdmi, INT_CODEC_SCRATCH0, HDMI_NV_PDISP_INT_MASK);
1236 
1237     hdmi->pixel_clock = mode->clock * 1000;
1238     h_sync_width = mode->hsync_end - mode->hsync_start;
1239     h_back_porch = mode->htotal - mode->hsync_end;
1240     h_front_porch = mode->hsync_start - mode->hdisplay;
1241 
1242     err = dev_pm_opp_set_rate(hdmi->dev, hdmi->pixel_clock);
1243     if (err < 0) {
1244         dev_err(hdmi->dev, "failed to set HDMI clock frequency: %d\n",
1245             err);
1246     }
1247 
1248     DRM_DEBUG_KMS("HDMI clock rate: %lu Hz\n", clk_get_rate(hdmi->clk));
1249 
1250     /* power up sequence */
1251     value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1252     value &= ~SOR_PLL_PDBG;
1253     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1254 
1255     usleep_range(10, 20);
1256 
1257     value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PLL0);
1258     value &= ~SOR_PLL_PWR;
1259     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_PLL0);
1260 
1261     tegra_dc_writel(dc, VSYNC_H_POSITION(1),
1262             DC_DISP_DISP_TIMING_OPTIONS);
1263     tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE_888,
1264             DC_DISP_DISP_COLOR_CONTROL);
1265 
1266     /* video_preamble uses h_pulse2 */
1267     pulse_start = 1 + h_sync_width + h_back_porch - 10;
1268 
1269     tegra_dc_writel(dc, H_PULSE2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
1270 
1271     value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
1272         PULSE_LAST_END_A;
1273     tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
1274 
1275     value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
1276     tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
1277 
1278     value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
1279         VSYNC_WINDOW_ENABLE;
1280     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1281 
1282     if (dc->pipe)
1283         value = HDMI_SRC_DISPLAYB;
1284     else
1285         value = HDMI_SRC_DISPLAYA;
1286 
1287     if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
1288                     (mode->vdisplay == 576)))
1289         tegra_hdmi_writel(hdmi,
1290                   value | ARM_VIDEO_RANGE_FULL,
1291                   HDMI_NV_PDISP_INPUT_CONTROL);
1292     else
1293         tegra_hdmi_writel(hdmi,
1294                   value | ARM_VIDEO_RANGE_LIMITED,
1295                   HDMI_NV_PDISP_INPUT_CONTROL);
1296 
1297     div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
1298     value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
1299     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
1300 
1301     hdmi->dvi = !tegra_output_is_hdmi(output);
1302     if (!hdmi->dvi) {
1303         /*
1304          * Make sure that the audio format has been configured before
1305          * enabling audio, otherwise we may try to divide by zero.
1306         */
1307         if (hdmi->format.sample_rate > 0) {
1308             err = tegra_hdmi_setup_audio(hdmi);
1309             if (err < 0)
1310                 hdmi->dvi = true;
1311         }
1312     }
1313 
1314     if (hdmi->config->has_hda)
1315         tegra_hdmi_write_eld(hdmi);
1316 
1317     rekey = HDMI_REKEY_DEFAULT;
1318     value = HDMI_CTRL_REKEY(rekey);
1319     value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
1320                       h_front_porch - rekey - 18) / 32);
1321 
1322     if (!hdmi->dvi)
1323         value |= HDMI_CTRL_ENABLE;
1324 
1325     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
1326 
1327     if (!hdmi->dvi) {
1328         tegra_hdmi_setup_avi_infoframe(hdmi, mode);
1329         tegra_hdmi_setup_audio_infoframe(hdmi);
1330 
1331         if (hdmi->stereo)
1332             tegra_hdmi_setup_stereo_infoframe(hdmi);
1333     }
1334 
1335     /* TMDS CONFIG */
1336     for (i = 0; i < hdmi->config->num_tmds; i++) {
1337         if (hdmi->pixel_clock <= hdmi->config->tmds[i].pclk) {
1338             tegra_hdmi_setup_tmds(hdmi, &hdmi->config->tmds[i]);
1339             break;
1340         }
1341     }
1342 
1343     tegra_hdmi_writel(hdmi,
1344               SOR_SEQ_PU_PC(0) |
1345               SOR_SEQ_PU_PC_ALT(0) |
1346               SOR_SEQ_PD_PC(8) |
1347               SOR_SEQ_PD_PC_ALT(8),
1348               HDMI_NV_PDISP_SOR_SEQ_CTL);
1349 
1350     value = SOR_SEQ_INST_WAIT_TIME(1) |
1351         SOR_SEQ_INST_WAIT_UNITS_VSYNC |
1352         SOR_SEQ_INST_HALT |
1353         SOR_SEQ_INST_PIN_A_LOW |
1354         SOR_SEQ_INST_PIN_B_LOW |
1355         SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
1356 
1357     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
1358     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
1359 
1360     value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_CSTM);
1361     value &= ~SOR_CSTM_ROTCLK(~0);
1362     value |= SOR_CSTM_ROTCLK(2);
1363     value |= SOR_CSTM_PLLDIV;
1364     value &= ~SOR_CSTM_LVDS_ENABLE;
1365     value &= ~SOR_CSTM_MODE_MASK;
1366     value |= SOR_CSTM_MODE_TMDS;
1367     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
1368 
1369     /* start SOR */
1370     tegra_hdmi_writel(hdmi,
1371               SOR_PWR_NORMAL_STATE_PU |
1372               SOR_PWR_NORMAL_START_NORMAL |
1373               SOR_PWR_SAFE_STATE_PD |
1374               SOR_PWR_SETTING_NEW_TRIGGER,
1375               HDMI_NV_PDISP_SOR_PWR);
1376     tegra_hdmi_writel(hdmi,
1377               SOR_PWR_NORMAL_STATE_PU |
1378               SOR_PWR_NORMAL_START_NORMAL |
1379               SOR_PWR_SAFE_STATE_PD |
1380               SOR_PWR_SETTING_NEW_DONE,
1381               HDMI_NV_PDISP_SOR_PWR);
1382 
1383     do {
1384         BUG_ON(--retries < 0);
1385         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
1386     } while (value & SOR_PWR_SETTING_NEW_PENDING);
1387 
1388     value = SOR_STATE_ASY_CRCMODE_COMPLETE |
1389         SOR_STATE_ASY_OWNER_HEAD0 |
1390         SOR_STATE_ASY_SUBOWNER_BOTH |
1391         SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
1392         SOR_STATE_ASY_DEPOL_POS;
1393 
1394     /* setup sync polarities */
1395     if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1396         value |= SOR_STATE_ASY_HSYNCPOL_POS;
1397 
1398     if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1399         value |= SOR_STATE_ASY_HSYNCPOL_NEG;
1400 
1401     if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1402         value |= SOR_STATE_ASY_VSYNCPOL_POS;
1403 
1404     if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1405         value |= SOR_STATE_ASY_VSYNCPOL_NEG;
1406 
1407     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
1408 
1409     value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
1410     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
1411 
1412     tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1413     tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
1414     tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
1415               HDMI_NV_PDISP_SOR_STATE1);
1416     tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
1417 
1418     value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1419     value |= HDMI_ENABLE;
1420     tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1421 
1422     tegra_dc_commit(dc);
1423 
1424     if (!hdmi->dvi) {
1425         tegra_hdmi_enable_avi_infoframe(hdmi);
1426         tegra_hdmi_enable_audio_infoframe(hdmi);
1427         tegra_hdmi_enable_audio(hdmi);
1428 
1429         if (hdmi->stereo)
1430             tegra_hdmi_enable_stereo_infoframe(hdmi);
1431     }
1432 
1433     /* TODO: add HDCP support */
1434 
1435     tegra_hdmi_audio_unlock(hdmi);
1436 }
1437 
1438 static int
1439 tegra_hdmi_encoder_atomic_check(struct drm_encoder *encoder,
1440                 struct drm_crtc_state *crtc_state,
1441                 struct drm_connector_state *conn_state)
1442 {
1443     struct tegra_output *output = encoder_to_output(encoder);
1444     struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1445     unsigned long pclk = crtc_state->mode.clock * 1000;
1446     struct tegra_hdmi *hdmi = to_hdmi(output);
1447     int err;
1448 
1449     err = tegra_dc_state_setup_clock(dc, crtc_state, hdmi->clk_parent,
1450                      pclk, 0);
1451     if (err < 0) {
1452         dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1453         return err;
1454     }
1455 
1456     return err;
1457 }
1458 
1459 static const struct drm_encoder_helper_funcs tegra_hdmi_encoder_helper_funcs = {
1460     .disable = tegra_hdmi_encoder_disable,
1461     .enable = tegra_hdmi_encoder_enable,
1462     .atomic_check = tegra_hdmi_encoder_atomic_check,
1463 };
1464 
1465 static int tegra_hdmi_hw_params(struct device *dev, void *data,
1466                 struct hdmi_codec_daifmt *fmt,
1467                 struct hdmi_codec_params *hparms)
1468 {
1469     struct tegra_hdmi *hdmi = data;
1470     int ret = 0;
1471 
1472     tegra_hdmi_audio_lock(hdmi);
1473 
1474     hdmi->format.sample_rate = hparms->sample_rate;
1475     hdmi->format.channels = hparms->channels;
1476 
1477     if (hdmi->pixel_clock && !hdmi->dvi)
1478         ret = tegra_hdmi_reconfigure_audio(hdmi);
1479 
1480     tegra_hdmi_audio_unlock(hdmi);
1481 
1482     return ret;
1483 }
1484 
1485 static int tegra_hdmi_audio_startup(struct device *dev, void *data)
1486 {
1487     struct tegra_hdmi *hdmi = data;
1488     int ret;
1489 
1490     ret = host1x_client_resume(&hdmi->client);
1491     if (ret < 0)
1492         dev_err(hdmi->dev, "failed to resume: %d\n", ret);
1493 
1494     return ret;
1495 }
1496 
1497 static void tegra_hdmi_audio_shutdown(struct device *dev, void *data)
1498 {
1499     struct tegra_hdmi *hdmi = data;
1500     int ret;
1501 
1502     tegra_hdmi_audio_lock(hdmi);
1503 
1504     hdmi->format.sample_rate = 0;
1505     hdmi->format.channels = 0;
1506 
1507     tegra_hdmi_audio_unlock(hdmi);
1508 
1509     ret = host1x_client_suspend(&hdmi->client);
1510     if (ret < 0)
1511         dev_err(hdmi->dev, "failed to suspend: %d\n", ret);
1512 }
1513 
1514 static const struct hdmi_codec_ops tegra_hdmi_codec_ops = {
1515     .hw_params = tegra_hdmi_hw_params,
1516     .audio_startup = tegra_hdmi_audio_startup,
1517     .audio_shutdown = tegra_hdmi_audio_shutdown,
1518 };
1519 
1520 static int tegra_hdmi_codec_register(struct tegra_hdmi *hdmi)
1521 {
1522     struct hdmi_codec_pdata codec_data = {};
1523 
1524     if (hdmi->config->has_hda)
1525         return 0;
1526 
1527     codec_data.ops = &tegra_hdmi_codec_ops;
1528     codec_data.data = hdmi;
1529     codec_data.spdif = 1;
1530 
1531     hdmi->audio_pdev = platform_device_register_data(hdmi->dev,
1532                              HDMI_CODEC_DRV_NAME,
1533                              PLATFORM_DEVID_AUTO,
1534                              &codec_data,
1535                              sizeof(codec_data));
1536     if (IS_ERR(hdmi->audio_pdev))
1537         return PTR_ERR(hdmi->audio_pdev);
1538 
1539     hdmi->format.channels = 2;
1540 
1541     return 0;
1542 }
1543 
1544 static void tegra_hdmi_codec_unregister(struct tegra_hdmi *hdmi)
1545 {
1546     if (hdmi->audio_pdev)
1547         platform_device_unregister(hdmi->audio_pdev);
1548 }
1549 
1550 static int tegra_hdmi_init(struct host1x_client *client)
1551 {
1552     struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1553     struct drm_device *drm = dev_get_drvdata(client->host);
1554     int err;
1555 
1556     hdmi->output.dev = client->dev;
1557 
1558     drm_connector_init_with_ddc(drm, &hdmi->output.connector,
1559                     &tegra_hdmi_connector_funcs,
1560                     DRM_MODE_CONNECTOR_HDMIA,
1561                     hdmi->output.ddc);
1562     drm_connector_helper_add(&hdmi->output.connector,
1563                  &tegra_hdmi_connector_helper_funcs);
1564     hdmi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1565 
1566     drm_simple_encoder_init(drm, &hdmi->output.encoder,
1567                 DRM_MODE_ENCODER_TMDS);
1568     drm_encoder_helper_add(&hdmi->output.encoder,
1569                    &tegra_hdmi_encoder_helper_funcs);
1570 
1571     drm_connector_attach_encoder(&hdmi->output.connector,
1572                       &hdmi->output.encoder);
1573     drm_connector_register(&hdmi->output.connector);
1574 
1575     err = tegra_output_init(drm, &hdmi->output);
1576     if (err < 0) {
1577         dev_err(client->dev, "failed to initialize output: %d\n", err);
1578         return err;
1579     }
1580 
1581     hdmi->output.encoder.possible_crtcs = 0x3;
1582 
1583     err = regulator_enable(hdmi->hdmi);
1584     if (err < 0) {
1585         dev_err(client->dev, "failed to enable HDMI regulator: %d\n",
1586             err);
1587         goto output_exit;
1588     }
1589 
1590     err = regulator_enable(hdmi->pll);
1591     if (err < 0) {
1592         dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
1593         goto disable_hdmi;
1594     }
1595 
1596     err = regulator_enable(hdmi->vdd);
1597     if (err < 0) {
1598         dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
1599         goto disable_pll;
1600     }
1601 
1602     err = tegra_hdmi_codec_register(hdmi);
1603     if (err < 0) {
1604         dev_err(hdmi->dev, "failed to register audio codec: %d\n", err);
1605         goto disable_vdd;
1606     }
1607 
1608     return 0;
1609 
1610 disable_vdd:
1611     regulator_disable(hdmi->vdd);
1612 disable_pll:
1613     regulator_disable(hdmi->pll);
1614 disable_hdmi:
1615     regulator_disable(hdmi->hdmi);
1616 output_exit:
1617     tegra_output_exit(&hdmi->output);
1618 
1619     return err;
1620 }
1621 
1622 static int tegra_hdmi_exit(struct host1x_client *client)
1623 {
1624     struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1625 
1626     tegra_hdmi_codec_unregister(hdmi);
1627 
1628     tegra_output_exit(&hdmi->output);
1629 
1630     regulator_disable(hdmi->vdd);
1631     regulator_disable(hdmi->pll);
1632     regulator_disable(hdmi->hdmi);
1633 
1634     return 0;
1635 }
1636 
1637 static int tegra_hdmi_runtime_suspend(struct host1x_client *client)
1638 {
1639     struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1640     struct device *dev = client->dev;
1641     int err;
1642 
1643     err = reset_control_assert(hdmi->rst);
1644     if (err < 0) {
1645         dev_err(dev, "failed to assert reset: %d\n", err);
1646         return err;
1647     }
1648 
1649     usleep_range(1000, 2000);
1650 
1651     clk_disable_unprepare(hdmi->clk);
1652     pm_runtime_put_sync(dev);
1653 
1654     return 0;
1655 }
1656 
1657 static int tegra_hdmi_runtime_resume(struct host1x_client *client)
1658 {
1659     struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1660     struct device *dev = client->dev;
1661     int err;
1662 
1663     err = pm_runtime_resume_and_get(dev);
1664     if (err < 0) {
1665         dev_err(dev, "failed to get runtime PM: %d\n", err);
1666         return err;
1667     }
1668 
1669     err = clk_prepare_enable(hdmi->clk);
1670     if (err < 0) {
1671         dev_err(dev, "failed to enable clock: %d\n", err);
1672         goto put_rpm;
1673     }
1674 
1675     usleep_range(1000, 2000);
1676 
1677     err = reset_control_deassert(hdmi->rst);
1678     if (err < 0) {
1679         dev_err(dev, "failed to deassert reset: %d\n", err);
1680         goto disable_clk;
1681     }
1682 
1683     return 0;
1684 
1685 disable_clk:
1686     clk_disable_unprepare(hdmi->clk);
1687 put_rpm:
1688     pm_runtime_put_sync(dev);
1689     return err;
1690 }
1691 
1692 static const struct host1x_client_ops hdmi_client_ops = {
1693     .init = tegra_hdmi_init,
1694     .exit = tegra_hdmi_exit,
1695     .suspend = tegra_hdmi_runtime_suspend,
1696     .resume = tegra_hdmi_runtime_resume,
1697 };
1698 
1699 static const struct tegra_hdmi_config tegra20_hdmi_config = {
1700     .tmds = tegra20_tmds_config,
1701     .num_tmds = ARRAY_SIZE(tegra20_tmds_config),
1702     .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1703     .fuse_override_value = 1 << 31,
1704     .has_sor_io_peak_current = false,
1705     .has_hda = false,
1706     .has_hbr = false,
1707 };
1708 
1709 static const struct tegra_hdmi_config tegra30_hdmi_config = {
1710     .tmds = tegra30_tmds_config,
1711     .num_tmds = ARRAY_SIZE(tegra30_tmds_config),
1712     .fuse_override_offset = HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT,
1713     .fuse_override_value = 1 << 31,
1714     .has_sor_io_peak_current = false,
1715     .has_hda = true,
1716     .has_hbr = false,
1717 };
1718 
1719 static const struct tegra_hdmi_config tegra114_hdmi_config = {
1720     .tmds = tegra114_tmds_config,
1721     .num_tmds = ARRAY_SIZE(tegra114_tmds_config),
1722     .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1723     .fuse_override_value = 1 << 31,
1724     .has_sor_io_peak_current = true,
1725     .has_hda = true,
1726     .has_hbr = true,
1727 };
1728 
1729 static const struct tegra_hdmi_config tegra124_hdmi_config = {
1730     .tmds = tegra124_tmds_config,
1731     .num_tmds = ARRAY_SIZE(tegra124_tmds_config),
1732     .fuse_override_offset = HDMI_NV_PDISP_SOR_PAD_CTLS0,
1733     .fuse_override_value = 1 << 31,
1734     .has_sor_io_peak_current = true,
1735     .has_hda = true,
1736     .has_hbr = true,
1737 };
1738 
1739 static const struct of_device_id tegra_hdmi_of_match[] = {
1740     { .compatible = "nvidia,tegra124-hdmi", .data = &tegra124_hdmi_config },
1741     { .compatible = "nvidia,tegra114-hdmi", .data = &tegra114_hdmi_config },
1742     { .compatible = "nvidia,tegra30-hdmi", .data = &tegra30_hdmi_config },
1743     { .compatible = "nvidia,tegra20-hdmi", .data = &tegra20_hdmi_config },
1744     { },
1745 };
1746 MODULE_DEVICE_TABLE(of, tegra_hdmi_of_match);
1747 
1748 static irqreturn_t tegra_hdmi_irq(int irq, void *data)
1749 {
1750     struct tegra_hdmi *hdmi = data;
1751     u32 value;
1752 
1753     value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_INT_STATUS);
1754     tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_INT_STATUS);
1755 
1756     if (value & INT_CODEC_SCRATCH0) {
1757         unsigned int format;
1758         u32 value;
1759 
1760         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_AUDIO_HDA_CODEC_SCRATCH0);
1761 
1762         if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) {
1763             format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK;
1764 
1765             tegra_hda_parse_format(format, &hdmi->format);
1766             tegra_hdmi_reconfigure_audio(hdmi);
1767         } else {
1768             tegra_hdmi_disable_audio_infoframe(hdmi);
1769             tegra_hdmi_disable_audio(hdmi);
1770         }
1771     }
1772 
1773     return IRQ_HANDLED;
1774 }
1775 
1776 static int tegra_hdmi_probe(struct platform_device *pdev)
1777 {
1778     struct tegra_hdmi *hdmi;
1779     struct resource *regs;
1780     int err;
1781 
1782     hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1783     if (!hdmi)
1784         return -ENOMEM;
1785 
1786     hdmi->config = of_device_get_match_data(&pdev->dev);
1787     hdmi->dev = &pdev->dev;
1788 
1789     hdmi->audio_source = AUTO;
1790     hdmi->stereo = false;
1791     hdmi->dvi = false;
1792 
1793     mutex_init(&hdmi->audio_lock);
1794 
1795     hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1796     if (IS_ERR(hdmi->clk)) {
1797         dev_err(&pdev->dev, "failed to get clock\n");
1798         return PTR_ERR(hdmi->clk);
1799     }
1800 
1801     hdmi->rst = devm_reset_control_get(&pdev->dev, "hdmi");
1802     if (IS_ERR(hdmi->rst)) {
1803         dev_err(&pdev->dev, "failed to get reset\n");
1804         return PTR_ERR(hdmi->rst);
1805     }
1806 
1807     hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1808     if (IS_ERR(hdmi->clk_parent))
1809         return PTR_ERR(hdmi->clk_parent);
1810 
1811     err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1812     if (err < 0) {
1813         dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1814         return err;
1815     }
1816 
1817     hdmi->hdmi = devm_regulator_get(&pdev->dev, "hdmi");
1818     err = PTR_ERR_OR_ZERO(hdmi->hdmi);
1819     if (err)
1820         return dev_err_probe(&pdev->dev, err,
1821                      "failed to get HDMI regulator\n");
1822 
1823     hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1824     err = PTR_ERR_OR_ZERO(hdmi->pll);
1825     if (err)
1826         return dev_err_probe(&pdev->dev, err,
1827                      "failed to get PLL regulator\n");
1828 
1829     hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1830     err = PTR_ERR_OR_ZERO(hdmi->vdd);
1831     if (err)
1832         return dev_err_probe(&pdev->dev, err,
1833                      "failed to get VDD regulator\n");
1834 
1835     hdmi->output.dev = &pdev->dev;
1836 
1837     err = tegra_output_probe(&hdmi->output);
1838     if (err < 0)
1839         return err;
1840 
1841     regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1842     hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
1843     if (IS_ERR(hdmi->regs))
1844         return PTR_ERR(hdmi->regs);
1845 
1846     err = platform_get_irq(pdev, 0);
1847     if (err < 0)
1848         return err;
1849 
1850     hdmi->irq = err;
1851 
1852     err = devm_request_irq(hdmi->dev, hdmi->irq, tegra_hdmi_irq, 0,
1853                    dev_name(hdmi->dev), hdmi);
1854     if (err < 0) {
1855         dev_err(&pdev->dev, "failed to request IRQ#%u: %d\n",
1856             hdmi->irq, err);
1857         return err;
1858     }
1859 
1860     platform_set_drvdata(pdev, hdmi);
1861 
1862     err = devm_pm_runtime_enable(&pdev->dev);
1863     if (err)
1864         return err;
1865 
1866     err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
1867     if (err)
1868         return err;
1869 
1870     INIT_LIST_HEAD(&hdmi->client.list);
1871     hdmi->client.ops = &hdmi_client_ops;
1872     hdmi->client.dev = &pdev->dev;
1873 
1874     err = host1x_client_register(&hdmi->client);
1875     if (err < 0) {
1876         dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1877             err);
1878         return err;
1879     }
1880 
1881     return 0;
1882 }
1883 
1884 static int tegra_hdmi_remove(struct platform_device *pdev)
1885 {
1886     struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1887     int err;
1888 
1889     err = host1x_client_unregister(&hdmi->client);
1890     if (err < 0) {
1891         dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1892             err);
1893         return err;
1894     }
1895 
1896     tegra_output_remove(&hdmi->output);
1897 
1898     return 0;
1899 }
1900 
1901 struct platform_driver tegra_hdmi_driver = {
1902     .driver = {
1903         .name = "tegra-hdmi",
1904         .of_match_table = tegra_hdmi_of_match,
1905     },
1906     .probe = tegra_hdmi_probe,
1907     .remove = tegra_hdmi_remove,
1908 };
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