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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2013 Avionic Design GmbH
0004  * Copyright (C) 2013 NVIDIA Corporation
0005  */
0006 
0007 #include <linux/clk.h>
0008 #include <linux/delay.h>
0009 #include <linux/host1x.h>
0010 #include <linux/iommu.h>
0011 #include <linux/module.h>
0012 #include <linux/of_device.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/pm_domain.h>
0015 #include <linux/pm_opp.h>
0016 #include <linux/pm_runtime.h>
0017 #include <linux/reset.h>
0018 
0019 #include <soc/tegra/common.h>
0020 #include <soc/tegra/pmc.h>
0021 
0022 #include "drm.h"
0023 #include "gem.h"
0024 #include "gr3d.h"
0025 
0026 enum {
0027     RST_MC,
0028     RST_GR3D,
0029     RST_MC2,
0030     RST_GR3D2,
0031     RST_GR3D_MAX,
0032 };
0033 
0034 struct gr3d_soc {
0035     unsigned int version;
0036     unsigned int num_clocks;
0037     unsigned int num_resets;
0038 };
0039 
0040 struct gr3d {
0041     struct tegra_drm_client client;
0042     struct host1x_channel *channel;
0043 
0044     const struct gr3d_soc *soc;
0045     struct clk_bulk_data *clocks;
0046     unsigned int nclocks;
0047     struct reset_control_bulk_data resets[RST_GR3D_MAX];
0048     unsigned int nresets;
0049 
0050     DECLARE_BITMAP(addr_regs, GR3D_NUM_REGS);
0051 };
0052 
0053 static inline struct gr3d *to_gr3d(struct tegra_drm_client *client)
0054 {
0055     return container_of(client, struct gr3d, client);
0056 }
0057 
0058 static int gr3d_init(struct host1x_client *client)
0059 {
0060     struct tegra_drm_client *drm = host1x_to_drm_client(client);
0061     struct drm_device *dev = dev_get_drvdata(client->host);
0062     unsigned long flags = HOST1X_SYNCPT_HAS_BASE;
0063     struct gr3d *gr3d = to_gr3d(drm);
0064     int err;
0065 
0066     gr3d->channel = host1x_channel_request(client);
0067     if (!gr3d->channel)
0068         return -ENOMEM;
0069 
0070     client->syncpts[0] = host1x_syncpt_request(client, flags);
0071     if (!client->syncpts[0]) {
0072         err = -ENOMEM;
0073         dev_err(client->dev, "failed to request syncpoint: %d\n", err);
0074         goto put;
0075     }
0076 
0077     err = host1x_client_iommu_attach(client);
0078     if (err < 0) {
0079         dev_err(client->dev, "failed to attach to domain: %d\n", err);
0080         goto free;
0081     }
0082 
0083     pm_runtime_enable(client->dev);
0084     pm_runtime_use_autosuspend(client->dev);
0085     pm_runtime_set_autosuspend_delay(client->dev, 200);
0086 
0087     err = tegra_drm_register_client(dev->dev_private, drm);
0088     if (err < 0) {
0089         dev_err(client->dev, "failed to register client: %d\n", err);
0090         goto disable_rpm;
0091     }
0092 
0093     return 0;
0094 
0095 disable_rpm:
0096     pm_runtime_dont_use_autosuspend(client->dev);
0097     pm_runtime_force_suspend(client->dev);
0098 
0099     host1x_client_iommu_detach(client);
0100 free:
0101     host1x_syncpt_put(client->syncpts[0]);
0102 put:
0103     host1x_channel_put(gr3d->channel);
0104     return err;
0105 }
0106 
0107 static int gr3d_exit(struct host1x_client *client)
0108 {
0109     struct tegra_drm_client *drm = host1x_to_drm_client(client);
0110     struct drm_device *dev = dev_get_drvdata(client->host);
0111     struct gr3d *gr3d = to_gr3d(drm);
0112     int err;
0113 
0114     err = tegra_drm_unregister_client(dev->dev_private, drm);
0115     if (err < 0)
0116         return err;
0117 
0118     pm_runtime_dont_use_autosuspend(client->dev);
0119     pm_runtime_force_suspend(client->dev);
0120 
0121     host1x_client_iommu_detach(client);
0122     host1x_syncpt_put(client->syncpts[0]);
0123     host1x_channel_put(gr3d->channel);
0124 
0125     gr3d->channel = NULL;
0126 
0127     return 0;
0128 }
0129 
0130 static const struct host1x_client_ops gr3d_client_ops = {
0131     .init = gr3d_init,
0132     .exit = gr3d_exit,
0133 };
0134 
0135 static int gr3d_open_channel(struct tegra_drm_client *client,
0136                  struct tegra_drm_context *context)
0137 {
0138     struct gr3d *gr3d = to_gr3d(client);
0139 
0140     context->channel = host1x_channel_get(gr3d->channel);
0141     if (!context->channel)
0142         return -ENOMEM;
0143 
0144     return 0;
0145 }
0146 
0147 static void gr3d_close_channel(struct tegra_drm_context *context)
0148 {
0149     host1x_channel_put(context->channel);
0150 }
0151 
0152 static int gr3d_is_addr_reg(struct device *dev, u32 class, u32 offset)
0153 {
0154     struct gr3d *gr3d = dev_get_drvdata(dev);
0155 
0156     switch (class) {
0157     case HOST1X_CLASS_HOST1X:
0158         if (offset == 0x2b)
0159             return 1;
0160 
0161         break;
0162 
0163     case HOST1X_CLASS_GR3D:
0164         if (offset >= GR3D_NUM_REGS)
0165             break;
0166 
0167         if (test_bit(offset, gr3d->addr_regs))
0168             return 1;
0169 
0170         break;
0171     }
0172 
0173     return 0;
0174 }
0175 
0176 static const struct tegra_drm_client_ops gr3d_ops = {
0177     .open_channel = gr3d_open_channel,
0178     .close_channel = gr3d_close_channel,
0179     .is_addr_reg = gr3d_is_addr_reg,
0180     .submit = tegra_drm_submit,
0181 };
0182 
0183 static const struct gr3d_soc tegra20_gr3d_soc = {
0184     .version = 0x20,
0185     .num_clocks = 1,
0186     .num_resets = 2,
0187 };
0188 
0189 static const struct gr3d_soc tegra30_gr3d_soc = {
0190     .version = 0x30,
0191     .num_clocks = 2,
0192     .num_resets = 4,
0193 };
0194 
0195 static const struct gr3d_soc tegra114_gr3d_soc = {
0196     .version = 0x35,
0197     .num_clocks = 1,
0198     .num_resets = 2,
0199 };
0200 
0201 static const struct of_device_id tegra_gr3d_match[] = {
0202     { .compatible = "nvidia,tegra114-gr3d", .data = &tegra114_gr3d_soc },
0203     { .compatible = "nvidia,tegra30-gr3d", .data = &tegra30_gr3d_soc },
0204     { .compatible = "nvidia,tegra20-gr3d", .data = &tegra20_gr3d_soc },
0205     { }
0206 };
0207 MODULE_DEVICE_TABLE(of, tegra_gr3d_match);
0208 
0209 static const u32 gr3d_addr_regs[] = {
0210     GR3D_IDX_ATTRIBUTE( 0),
0211     GR3D_IDX_ATTRIBUTE( 1),
0212     GR3D_IDX_ATTRIBUTE( 2),
0213     GR3D_IDX_ATTRIBUTE( 3),
0214     GR3D_IDX_ATTRIBUTE( 4),
0215     GR3D_IDX_ATTRIBUTE( 5),
0216     GR3D_IDX_ATTRIBUTE( 6),
0217     GR3D_IDX_ATTRIBUTE( 7),
0218     GR3D_IDX_ATTRIBUTE( 8),
0219     GR3D_IDX_ATTRIBUTE( 9),
0220     GR3D_IDX_ATTRIBUTE(10),
0221     GR3D_IDX_ATTRIBUTE(11),
0222     GR3D_IDX_ATTRIBUTE(12),
0223     GR3D_IDX_ATTRIBUTE(13),
0224     GR3D_IDX_ATTRIBUTE(14),
0225     GR3D_IDX_ATTRIBUTE(15),
0226     GR3D_IDX_INDEX_BASE,
0227     GR3D_QR_ZTAG_ADDR,
0228     GR3D_QR_CTAG_ADDR,
0229     GR3D_QR_CZ_ADDR,
0230     GR3D_TEX_TEX_ADDR( 0),
0231     GR3D_TEX_TEX_ADDR( 1),
0232     GR3D_TEX_TEX_ADDR( 2),
0233     GR3D_TEX_TEX_ADDR( 3),
0234     GR3D_TEX_TEX_ADDR( 4),
0235     GR3D_TEX_TEX_ADDR( 5),
0236     GR3D_TEX_TEX_ADDR( 6),
0237     GR3D_TEX_TEX_ADDR( 7),
0238     GR3D_TEX_TEX_ADDR( 8),
0239     GR3D_TEX_TEX_ADDR( 9),
0240     GR3D_TEX_TEX_ADDR(10),
0241     GR3D_TEX_TEX_ADDR(11),
0242     GR3D_TEX_TEX_ADDR(12),
0243     GR3D_TEX_TEX_ADDR(13),
0244     GR3D_TEX_TEX_ADDR(14),
0245     GR3D_TEX_TEX_ADDR(15),
0246     GR3D_DW_MEMORY_OUTPUT_ADDRESS,
0247     GR3D_GLOBAL_SURFADDR( 0),
0248     GR3D_GLOBAL_SURFADDR( 1),
0249     GR3D_GLOBAL_SURFADDR( 2),
0250     GR3D_GLOBAL_SURFADDR( 3),
0251     GR3D_GLOBAL_SURFADDR( 4),
0252     GR3D_GLOBAL_SURFADDR( 5),
0253     GR3D_GLOBAL_SURFADDR( 6),
0254     GR3D_GLOBAL_SURFADDR( 7),
0255     GR3D_GLOBAL_SURFADDR( 8),
0256     GR3D_GLOBAL_SURFADDR( 9),
0257     GR3D_GLOBAL_SURFADDR(10),
0258     GR3D_GLOBAL_SURFADDR(11),
0259     GR3D_GLOBAL_SURFADDR(12),
0260     GR3D_GLOBAL_SURFADDR(13),
0261     GR3D_GLOBAL_SURFADDR(14),
0262     GR3D_GLOBAL_SURFADDR(15),
0263     GR3D_GLOBAL_SPILLSURFADDR,
0264     GR3D_GLOBAL_SURFOVERADDR( 0),
0265     GR3D_GLOBAL_SURFOVERADDR( 1),
0266     GR3D_GLOBAL_SURFOVERADDR( 2),
0267     GR3D_GLOBAL_SURFOVERADDR( 3),
0268     GR3D_GLOBAL_SURFOVERADDR( 4),
0269     GR3D_GLOBAL_SURFOVERADDR( 5),
0270     GR3D_GLOBAL_SURFOVERADDR( 6),
0271     GR3D_GLOBAL_SURFOVERADDR( 7),
0272     GR3D_GLOBAL_SURFOVERADDR( 8),
0273     GR3D_GLOBAL_SURFOVERADDR( 9),
0274     GR3D_GLOBAL_SURFOVERADDR(10),
0275     GR3D_GLOBAL_SURFOVERADDR(11),
0276     GR3D_GLOBAL_SURFOVERADDR(12),
0277     GR3D_GLOBAL_SURFOVERADDR(13),
0278     GR3D_GLOBAL_SURFOVERADDR(14),
0279     GR3D_GLOBAL_SURFOVERADDR(15),
0280     GR3D_GLOBAL_SAMP01SURFADDR( 0),
0281     GR3D_GLOBAL_SAMP01SURFADDR( 1),
0282     GR3D_GLOBAL_SAMP01SURFADDR( 2),
0283     GR3D_GLOBAL_SAMP01SURFADDR( 3),
0284     GR3D_GLOBAL_SAMP01SURFADDR( 4),
0285     GR3D_GLOBAL_SAMP01SURFADDR( 5),
0286     GR3D_GLOBAL_SAMP01SURFADDR( 6),
0287     GR3D_GLOBAL_SAMP01SURFADDR( 7),
0288     GR3D_GLOBAL_SAMP01SURFADDR( 8),
0289     GR3D_GLOBAL_SAMP01SURFADDR( 9),
0290     GR3D_GLOBAL_SAMP01SURFADDR(10),
0291     GR3D_GLOBAL_SAMP01SURFADDR(11),
0292     GR3D_GLOBAL_SAMP01SURFADDR(12),
0293     GR3D_GLOBAL_SAMP01SURFADDR(13),
0294     GR3D_GLOBAL_SAMP01SURFADDR(14),
0295     GR3D_GLOBAL_SAMP01SURFADDR(15),
0296     GR3D_GLOBAL_SAMP23SURFADDR( 0),
0297     GR3D_GLOBAL_SAMP23SURFADDR( 1),
0298     GR3D_GLOBAL_SAMP23SURFADDR( 2),
0299     GR3D_GLOBAL_SAMP23SURFADDR( 3),
0300     GR3D_GLOBAL_SAMP23SURFADDR( 4),
0301     GR3D_GLOBAL_SAMP23SURFADDR( 5),
0302     GR3D_GLOBAL_SAMP23SURFADDR( 6),
0303     GR3D_GLOBAL_SAMP23SURFADDR( 7),
0304     GR3D_GLOBAL_SAMP23SURFADDR( 8),
0305     GR3D_GLOBAL_SAMP23SURFADDR( 9),
0306     GR3D_GLOBAL_SAMP23SURFADDR(10),
0307     GR3D_GLOBAL_SAMP23SURFADDR(11),
0308     GR3D_GLOBAL_SAMP23SURFADDR(12),
0309     GR3D_GLOBAL_SAMP23SURFADDR(13),
0310     GR3D_GLOBAL_SAMP23SURFADDR(14),
0311     GR3D_GLOBAL_SAMP23SURFADDR(15),
0312 };
0313 
0314 static int gr3d_power_up_legacy_domain(struct device *dev, const char *name,
0315                        unsigned int id)
0316 {
0317     struct gr3d *gr3d = dev_get_drvdata(dev);
0318     struct reset_control *reset;
0319     struct clk *clk;
0320     unsigned int i;
0321     int err;
0322 
0323     /*
0324      * Tegra20 device-tree doesn't specify 3d clock name and there is only
0325      * one clock for Tegra20. Tegra30+ device-trees always specified names
0326      * for the clocks.
0327      */
0328     if (gr3d->nclocks == 1) {
0329         if (id == TEGRA_POWERGATE_3D1)
0330             return 0;
0331 
0332         clk = gr3d->clocks[0].clk;
0333     } else {
0334         for (i = 0; i < gr3d->nclocks; i++) {
0335             if (WARN_ON(!gr3d->clocks[i].id))
0336                 continue;
0337 
0338             if (!strcmp(gr3d->clocks[i].id, name)) {
0339                 clk = gr3d->clocks[i].clk;
0340                 break;
0341             }
0342         }
0343 
0344         if (WARN_ON(i == gr3d->nclocks))
0345             return -EINVAL;
0346     }
0347 
0348     /*
0349      * We use array of resets, which includes MC resets, and MC
0350      * reset shouldn't be asserted while hardware is gated because
0351      * MC flushing will fail for gated hardware. Hence for legacy
0352      * PD we request the individual reset separately.
0353      */
0354     reset = reset_control_get_exclusive_released(dev, name);
0355     if (IS_ERR(reset))
0356         return PTR_ERR(reset);
0357 
0358     err = reset_control_acquire(reset);
0359     if (err) {
0360         dev_err(dev, "failed to acquire %s reset: %d\n", name, err);
0361     } else {
0362         err = tegra_powergate_sequence_power_up(id, clk, reset);
0363         reset_control_release(reset);
0364     }
0365 
0366     reset_control_put(reset);
0367     if (err)
0368         return err;
0369 
0370     /*
0371      * tegra_powergate_sequence_power_up() leaves clocks enabled,
0372      * while GENPD not. Hence keep clock-enable balanced.
0373      */
0374     clk_disable_unprepare(clk);
0375 
0376     return 0;
0377 }
0378 
0379 static void gr3d_del_link(void *link)
0380 {
0381     device_link_del(link);
0382 }
0383 
0384 static int gr3d_init_power(struct device *dev, struct gr3d *gr3d)
0385 {
0386     static const char * const opp_genpd_names[] = { "3d0", "3d1", NULL };
0387     const u32 link_flags = DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME;
0388     struct device **opp_virt_devs, *pd_dev;
0389     struct device_link *link;
0390     unsigned int i;
0391     int err;
0392 
0393     err = of_count_phandle_with_args(dev->of_node, "power-domains",
0394                      "#power-domain-cells");
0395     if (err < 0) {
0396         if (err != -ENOENT)
0397             return err;
0398 
0399         /*
0400          * Older device-trees don't use GENPD. In this case we should
0401          * toggle power domain manually.
0402          */
0403         err = gr3d_power_up_legacy_domain(dev, "3d",
0404                           TEGRA_POWERGATE_3D);
0405         if (err)
0406             return err;
0407 
0408         err = gr3d_power_up_legacy_domain(dev, "3d2",
0409                           TEGRA_POWERGATE_3D1);
0410         if (err)
0411             return err;
0412 
0413         return 0;
0414     }
0415 
0416     /*
0417      * The PM domain core automatically attaches a single power domain,
0418      * otherwise it skips attaching completely. We have a single domain
0419      * on Tegra20 and two domains on Tegra30+.
0420      */
0421     if (dev->pm_domain)
0422         return 0;
0423 
0424     err = devm_pm_opp_attach_genpd(dev, opp_genpd_names, &opp_virt_devs);
0425     if (err)
0426         return err;
0427 
0428     for (i = 0; opp_genpd_names[i]; i++) {
0429         pd_dev = opp_virt_devs[i];
0430         if (!pd_dev) {
0431             dev_err(dev, "failed to get %s power domain\n",
0432                 opp_genpd_names[i]);
0433             return -EINVAL;
0434         }
0435 
0436         link = device_link_add(dev, pd_dev, link_flags);
0437         if (!link) {
0438             dev_err(dev, "failed to link to %s\n", dev_name(pd_dev));
0439             return -EINVAL;
0440         }
0441 
0442         err = devm_add_action_or_reset(dev, gr3d_del_link, link);
0443         if (err)
0444             return err;
0445     }
0446 
0447     return 0;
0448 }
0449 
0450 static int gr3d_get_clocks(struct device *dev, struct gr3d *gr3d)
0451 {
0452     int err;
0453 
0454     err = devm_clk_bulk_get_all(dev, &gr3d->clocks);
0455     if (err < 0) {
0456         dev_err(dev, "failed to get clock: %d\n", err);
0457         return err;
0458     }
0459     gr3d->nclocks = err;
0460 
0461     if (gr3d->nclocks != gr3d->soc->num_clocks) {
0462         dev_err(dev, "invalid number of clocks: %u\n", gr3d->nclocks);
0463         return -ENOENT;
0464     }
0465 
0466     return 0;
0467 }
0468 
0469 static int gr3d_get_resets(struct device *dev, struct gr3d *gr3d)
0470 {
0471     int err;
0472 
0473     gr3d->resets[RST_MC].id = "mc";
0474     gr3d->resets[RST_MC2].id = "mc2";
0475     gr3d->resets[RST_GR3D].id = "3d";
0476     gr3d->resets[RST_GR3D2].id = "3d2";
0477     gr3d->nresets = gr3d->soc->num_resets;
0478 
0479     err = devm_reset_control_bulk_get_optional_exclusive_released(
0480                 dev, gr3d->nresets, gr3d->resets);
0481     if (err) {
0482         dev_err(dev, "failed to get reset: %d\n", err);
0483         return err;
0484     }
0485 
0486     if (WARN_ON(!gr3d->resets[RST_GR3D].rstc) ||
0487         WARN_ON(!gr3d->resets[RST_GR3D2].rstc && gr3d->nresets == 4))
0488         return -ENOENT;
0489 
0490     return 0;
0491 }
0492 
0493 static int gr3d_probe(struct platform_device *pdev)
0494 {
0495     struct host1x_syncpt **syncpts;
0496     struct gr3d *gr3d;
0497     unsigned int i;
0498     int err;
0499 
0500     gr3d = devm_kzalloc(&pdev->dev, sizeof(*gr3d), GFP_KERNEL);
0501     if (!gr3d)
0502         return -ENOMEM;
0503 
0504     platform_set_drvdata(pdev, gr3d);
0505 
0506     gr3d->soc = of_device_get_match_data(&pdev->dev);
0507 
0508     syncpts = devm_kzalloc(&pdev->dev, sizeof(*syncpts), GFP_KERNEL);
0509     if (!syncpts)
0510         return -ENOMEM;
0511 
0512     err = gr3d_get_clocks(&pdev->dev, gr3d);
0513     if (err)
0514         return err;
0515 
0516     err = gr3d_get_resets(&pdev->dev, gr3d);
0517     if (err)
0518         return err;
0519 
0520     err = gr3d_init_power(&pdev->dev, gr3d);
0521     if (err)
0522         return err;
0523 
0524     INIT_LIST_HEAD(&gr3d->client.base.list);
0525     gr3d->client.base.ops = &gr3d_client_ops;
0526     gr3d->client.base.dev = &pdev->dev;
0527     gr3d->client.base.class = HOST1X_CLASS_GR3D;
0528     gr3d->client.base.syncpts = syncpts;
0529     gr3d->client.base.num_syncpts = 1;
0530 
0531     INIT_LIST_HEAD(&gr3d->client.list);
0532     gr3d->client.version = gr3d->soc->version;
0533     gr3d->client.ops = &gr3d_ops;
0534 
0535     err = devm_tegra_core_dev_init_opp_table_common(&pdev->dev);
0536     if (err)
0537         return err;
0538 
0539     err = host1x_client_register(&gr3d->client.base);
0540     if (err < 0) {
0541         dev_err(&pdev->dev, "failed to register host1x client: %d\n",
0542             err);
0543         return err;
0544     }
0545 
0546     /* initialize address register map */
0547     for (i = 0; i < ARRAY_SIZE(gr3d_addr_regs); i++)
0548         set_bit(gr3d_addr_regs[i], gr3d->addr_regs);
0549 
0550     return 0;
0551 }
0552 
0553 static int gr3d_remove(struct platform_device *pdev)
0554 {
0555     struct gr3d *gr3d = platform_get_drvdata(pdev);
0556     int err;
0557 
0558     err = host1x_client_unregister(&gr3d->client.base);
0559     if (err < 0) {
0560         dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
0561             err);
0562         return err;
0563     }
0564 
0565     return 0;
0566 }
0567 
0568 static int __maybe_unused gr3d_runtime_suspend(struct device *dev)
0569 {
0570     struct gr3d *gr3d = dev_get_drvdata(dev);
0571     int err;
0572 
0573     host1x_channel_stop(gr3d->channel);
0574 
0575     err = reset_control_bulk_assert(gr3d->nresets, gr3d->resets);
0576     if (err) {
0577         dev_err(dev, "failed to assert reset: %d\n", err);
0578         return err;
0579     }
0580 
0581     usleep_range(10, 20);
0582 
0583     /*
0584      * Older device-trees don't specify MC resets and power-gating can't
0585      * be done safely in that case. Hence we will keep the power ungated
0586      * for older DTBs. For newer DTBs, GENPD will perform the power-gating.
0587      */
0588 
0589     clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks);
0590     reset_control_bulk_release(gr3d->nresets, gr3d->resets);
0591 
0592     return 0;
0593 }
0594 
0595 static int __maybe_unused gr3d_runtime_resume(struct device *dev)
0596 {
0597     struct gr3d *gr3d = dev_get_drvdata(dev);
0598     int err;
0599 
0600     err = reset_control_bulk_acquire(gr3d->nresets, gr3d->resets);
0601     if (err) {
0602         dev_err(dev, "failed to acquire reset: %d\n", err);
0603         return err;
0604     }
0605 
0606     err = clk_bulk_prepare_enable(gr3d->nclocks, gr3d->clocks);
0607     if (err) {
0608         dev_err(dev, "failed to enable clock: %d\n", err);
0609         goto release_reset;
0610     }
0611 
0612     err = reset_control_bulk_deassert(gr3d->nresets, gr3d->resets);
0613     if (err) {
0614         dev_err(dev, "failed to deassert reset: %d\n", err);
0615         goto disable_clk;
0616     }
0617 
0618     return 0;
0619 
0620 disable_clk:
0621     clk_bulk_disable_unprepare(gr3d->nclocks, gr3d->clocks);
0622 release_reset:
0623     reset_control_bulk_release(gr3d->nresets, gr3d->resets);
0624 
0625     return err;
0626 }
0627 
0628 static const struct dev_pm_ops tegra_gr3d_pm = {
0629     SET_RUNTIME_PM_OPS(gr3d_runtime_suspend, gr3d_runtime_resume, NULL)
0630     SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
0631                 pm_runtime_force_resume)
0632 };
0633 
0634 struct platform_driver tegra_gr3d_driver = {
0635     .driver = {
0636         .name = "tegra-gr3d",
0637         .of_match_table = tegra_gr3d_match,
0638         .pm = &tegra_gr3d_pm,
0639     },
0640     .probe = gr3d_probe,
0641     .remove = gr3d_remove,
0642 };
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