drm/tegra/falcon.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (c) 2015, NVIDIA Corporation.
0004  */
0005
0006 #ifndef _FALCON_H_
0007 #define _FALCON_H_
0008
0009 #include <linux/types.h>
0010
0011 #define FALCON_UCLASS_METHOD_OFFSET     0x00000040
0012
0013 #define FALCON_UCLASS_METHOD_DATA       0x00000044
0014
0015 #define FALCON_IRQMSET              0x00001010
0016 #define FALCON_IRQMSET_WDTMR            (1 << 1)
0017 #define FALCON_IRQMSET_HALT         (1 << 4)
0018 #define FALCON_IRQMSET_EXTERR           (1 << 5)
0019 #define FALCON_IRQMSET_SWGEN0           (1 << 6)
0020 #define FALCON_IRQMSET_SWGEN1           (1 << 7)
0021 #define FALCON_IRQMSET_EXT(v)           (((v) & 0xff) << 8)
0022
0023 #define FALCON_IRQDEST              0x0000101c
0024 #define FALCON_IRQDEST_HALT         (1 << 4)
0025 #define FALCON_IRQDEST_EXTERR           (1 << 5)
0026 #define FALCON_IRQDEST_SWGEN0           (1 << 6)
0027 #define FALCON_IRQDEST_SWGEN1           (1 << 7)
0028 #define FALCON_IRQDEST_EXT(v)           (((v) & 0xff) << 8)
0029
0030 #define FALCON_ITFEN                0x00001048
0031 #define FALCON_ITFEN_CTXEN          (1 << 0)
0032 #define FALCON_ITFEN_MTHDEN         (1 << 1)
0033
0034 #define FALCON_IDLESTATE            0x0000104c
0035
0036 #define FALCON_CPUCTL               0x00001100
0037 #define FALCON_CPUCTL_STARTCPU          (1 << 1)
0038
0039 #define FALCON_BOOTVEC              0x00001104
0040
0041 #define FALCON_DMACTL               0x0000110c
0042 #define FALCON_DMACTL_DMEM_SCRUBBING        (1 << 1)
0043 #define FALCON_DMACTL_IMEM_SCRUBBING        (1 << 2)
0044
0045 #define FALCON_DMATRFBASE           0x00001110
0046
0047 #define FALCON_DMATRFMOFFS          0x00001114
0048
0049 #define FALCON_DMATRFCMD            0x00001118
0050 #define FALCON_DMATRFCMD_IDLE           (1 << 1)
0051 #define FALCON_DMATRFCMD_IMEM           (1 << 4)
0052 #define FALCON_DMATRFCMD_SIZE_256B      (6 << 8)
0053 #define FALCON_DMATRFCMD_DMACTX(v)      (((v) & 0x7) << 12)
0054
0055 #define FALCON_DMATRFFBOFFS         0x0000111c
0056
0057 struct falcon_fw_bin_header_v1 {
0058     u32 magic;      /* 0x10de */
0059     u32 version;        /* version of bin format (1) */
0060     u32 size;       /* entire image size including this header */
0061     u32 os_header_offset;
0062     u32 os_data_offset;
0063     u32 os_size;
0064 };
0065
0066 struct falcon_fw_os_app_v1 {
0067     u32 offset;
0068     u32 size;
0069 };
0070
0071 struct falcon_fw_os_header_v1 {
0072     u32 code_offset;
0073     u32 code_size;
0074     u32 data_offset;
0075     u32 data_size;
0076 };
0077
0078 struct falcon_firmware_section {
0079     unsigned long offset;
0080     size_t size;
0081 };
0082
0083 struct falcon_firmware {
0084     /* Firmware after it is read but not loaded */
0085     const struct firmware *firmware;
0086
0087     /* Raw firmware data */
0088     dma_addr_t iova;
0089     dma_addr_t phys;
0090     void *virt;
0091     size_t size;
0092
0093     /* Parsed firmware information */
0094     struct falcon_firmware_section bin_data;
0095     struct falcon_firmware_section data;
0096     struct falcon_firmware_section code;
0097 };
0098
0099 struct falcon {
0100     /* Set by falcon client */
0101     struct device *dev;
0102     void __iomem *regs;
0103
0104     struct falcon_firmware firmware;
0105 };
0106
0107 int falcon_init(struct falcon *falcon);
0108 void falcon_exit(struct falcon *falcon);
0109 int falcon_read_firmware(struct falcon *falcon, const char *firmware_name);
0110 int falcon_load_firmware(struct falcon *falcon);
0111 int falcon_boot(struct falcon *falcon);
0112 void falcon_execute_method(struct falcon *falcon, u32 method, u32 data);
0113 int falcon_wait_idle(struct falcon *falcon);
0114
0115 #endif /* _FALCON_H_ */