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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2013 NVIDIA Corporation
0004  */
0005 
0006 #include <linux/clk.h>
0007 #include <linux/debugfs.h>
0008 #include <linux/delay.h>
0009 #include <linux/host1x.h>
0010 #include <linux/module.h>
0011 #include <linux/of.h>
0012 #include <linux/of_platform.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/pm_runtime.h>
0015 #include <linux/regulator/consumer.h>
0016 #include <linux/reset.h>
0017 
0018 #include <video/mipi_display.h>
0019 
0020 #include <drm/drm_atomic_helper.h>
0021 #include <drm/drm_debugfs.h>
0022 #include <drm/drm_file.h>
0023 #include <drm/drm_mipi_dsi.h>
0024 #include <drm/drm_panel.h>
0025 #include <drm/drm_simple_kms_helper.h>
0026 
0027 #include "dc.h"
0028 #include "drm.h"
0029 #include "dsi.h"
0030 #include "mipi-phy.h"
0031 #include "trace.h"
0032 
0033 struct tegra_dsi_state {
0034     struct drm_connector_state base;
0035 
0036     struct mipi_dphy_timing timing;
0037     unsigned long period;
0038 
0039     unsigned int vrefresh;
0040     unsigned int lanes;
0041     unsigned long pclk;
0042     unsigned long bclk;
0043 
0044     enum tegra_dsi_format format;
0045     unsigned int mul;
0046     unsigned int div;
0047 };
0048 
0049 static inline struct tegra_dsi_state *
0050 to_dsi_state(struct drm_connector_state *state)
0051 {
0052     return container_of(state, struct tegra_dsi_state, base);
0053 }
0054 
0055 struct tegra_dsi {
0056     struct host1x_client client;
0057     struct tegra_output output;
0058     struct device *dev;
0059 
0060     void __iomem *regs;
0061 
0062     struct reset_control *rst;
0063     struct clk *clk_parent;
0064     struct clk *clk_lp;
0065     struct clk *clk;
0066 
0067     struct drm_info_list *debugfs_files;
0068 
0069     unsigned long flags;
0070     enum mipi_dsi_pixel_format format;
0071     unsigned int lanes;
0072 
0073     struct tegra_mipi_device *mipi;
0074     struct mipi_dsi_host host;
0075 
0076     struct regulator *vdd;
0077 
0078     unsigned int video_fifo_depth;
0079     unsigned int host_fifo_depth;
0080 
0081     /* for ganged-mode support */
0082     struct tegra_dsi *master;
0083     struct tegra_dsi *slave;
0084 };
0085 
0086 static inline struct tegra_dsi *
0087 host1x_client_to_dsi(struct host1x_client *client)
0088 {
0089     return container_of(client, struct tegra_dsi, client);
0090 }
0091 
0092 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
0093 {
0094     return container_of(host, struct tegra_dsi, host);
0095 }
0096 
0097 static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
0098 {
0099     return container_of(output, struct tegra_dsi, output);
0100 }
0101 
0102 static struct tegra_dsi_state *tegra_dsi_get_state(struct tegra_dsi *dsi)
0103 {
0104     return to_dsi_state(dsi->output.connector.state);
0105 }
0106 
0107 static inline u32 tegra_dsi_readl(struct tegra_dsi *dsi, unsigned int offset)
0108 {
0109     u32 value = readl(dsi->regs + (offset << 2));
0110 
0111     trace_dsi_readl(dsi->dev, offset, value);
0112 
0113     return value;
0114 }
0115 
0116 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, u32 value,
0117                     unsigned int offset)
0118 {
0119     trace_dsi_writel(dsi->dev, offset, value);
0120     writel(value, dsi->regs + (offset << 2));
0121 }
0122 
0123 #define DEBUGFS_REG32(_name) { .name = #_name, .offset = _name }
0124 
0125 static const struct debugfs_reg32 tegra_dsi_regs[] = {
0126     DEBUGFS_REG32(DSI_INCR_SYNCPT),
0127     DEBUGFS_REG32(DSI_INCR_SYNCPT_CONTROL),
0128     DEBUGFS_REG32(DSI_INCR_SYNCPT_ERROR),
0129     DEBUGFS_REG32(DSI_CTXSW),
0130     DEBUGFS_REG32(DSI_RD_DATA),
0131     DEBUGFS_REG32(DSI_WR_DATA),
0132     DEBUGFS_REG32(DSI_POWER_CONTROL),
0133     DEBUGFS_REG32(DSI_INT_ENABLE),
0134     DEBUGFS_REG32(DSI_INT_STATUS),
0135     DEBUGFS_REG32(DSI_INT_MASK),
0136     DEBUGFS_REG32(DSI_HOST_CONTROL),
0137     DEBUGFS_REG32(DSI_CONTROL),
0138     DEBUGFS_REG32(DSI_SOL_DELAY),
0139     DEBUGFS_REG32(DSI_MAX_THRESHOLD),
0140     DEBUGFS_REG32(DSI_TRIGGER),
0141     DEBUGFS_REG32(DSI_TX_CRC),
0142     DEBUGFS_REG32(DSI_STATUS),
0143     DEBUGFS_REG32(DSI_INIT_SEQ_CONTROL),
0144     DEBUGFS_REG32(DSI_INIT_SEQ_DATA_0),
0145     DEBUGFS_REG32(DSI_INIT_SEQ_DATA_1),
0146     DEBUGFS_REG32(DSI_INIT_SEQ_DATA_2),
0147     DEBUGFS_REG32(DSI_INIT_SEQ_DATA_3),
0148     DEBUGFS_REG32(DSI_INIT_SEQ_DATA_4),
0149     DEBUGFS_REG32(DSI_INIT_SEQ_DATA_5),
0150     DEBUGFS_REG32(DSI_INIT_SEQ_DATA_6),
0151     DEBUGFS_REG32(DSI_INIT_SEQ_DATA_7),
0152     DEBUGFS_REG32(DSI_PKT_SEQ_0_LO),
0153     DEBUGFS_REG32(DSI_PKT_SEQ_0_HI),
0154     DEBUGFS_REG32(DSI_PKT_SEQ_1_LO),
0155     DEBUGFS_REG32(DSI_PKT_SEQ_1_HI),
0156     DEBUGFS_REG32(DSI_PKT_SEQ_2_LO),
0157     DEBUGFS_REG32(DSI_PKT_SEQ_2_HI),
0158     DEBUGFS_REG32(DSI_PKT_SEQ_3_LO),
0159     DEBUGFS_REG32(DSI_PKT_SEQ_3_HI),
0160     DEBUGFS_REG32(DSI_PKT_SEQ_4_LO),
0161     DEBUGFS_REG32(DSI_PKT_SEQ_4_HI),
0162     DEBUGFS_REG32(DSI_PKT_SEQ_5_LO),
0163     DEBUGFS_REG32(DSI_PKT_SEQ_5_HI),
0164     DEBUGFS_REG32(DSI_DCS_CMDS),
0165     DEBUGFS_REG32(DSI_PKT_LEN_0_1),
0166     DEBUGFS_REG32(DSI_PKT_LEN_2_3),
0167     DEBUGFS_REG32(DSI_PKT_LEN_4_5),
0168     DEBUGFS_REG32(DSI_PKT_LEN_6_7),
0169     DEBUGFS_REG32(DSI_PHY_TIMING_0),
0170     DEBUGFS_REG32(DSI_PHY_TIMING_1),
0171     DEBUGFS_REG32(DSI_PHY_TIMING_2),
0172     DEBUGFS_REG32(DSI_BTA_TIMING),
0173     DEBUGFS_REG32(DSI_TIMEOUT_0),
0174     DEBUGFS_REG32(DSI_TIMEOUT_1),
0175     DEBUGFS_REG32(DSI_TO_TALLY),
0176     DEBUGFS_REG32(DSI_PAD_CONTROL_0),
0177     DEBUGFS_REG32(DSI_PAD_CONTROL_CD),
0178     DEBUGFS_REG32(DSI_PAD_CD_STATUS),
0179     DEBUGFS_REG32(DSI_VIDEO_MODE_CONTROL),
0180     DEBUGFS_REG32(DSI_PAD_CONTROL_1),
0181     DEBUGFS_REG32(DSI_PAD_CONTROL_2),
0182     DEBUGFS_REG32(DSI_PAD_CONTROL_3),
0183     DEBUGFS_REG32(DSI_PAD_CONTROL_4),
0184     DEBUGFS_REG32(DSI_GANGED_MODE_CONTROL),
0185     DEBUGFS_REG32(DSI_GANGED_MODE_START),
0186     DEBUGFS_REG32(DSI_GANGED_MODE_SIZE),
0187     DEBUGFS_REG32(DSI_RAW_DATA_BYTE_COUNT),
0188     DEBUGFS_REG32(DSI_ULTRA_LOW_POWER_CONTROL),
0189     DEBUGFS_REG32(DSI_INIT_SEQ_DATA_8),
0190     DEBUGFS_REG32(DSI_INIT_SEQ_DATA_9),
0191     DEBUGFS_REG32(DSI_INIT_SEQ_DATA_10),
0192     DEBUGFS_REG32(DSI_INIT_SEQ_DATA_11),
0193     DEBUGFS_REG32(DSI_INIT_SEQ_DATA_12),
0194     DEBUGFS_REG32(DSI_INIT_SEQ_DATA_13),
0195     DEBUGFS_REG32(DSI_INIT_SEQ_DATA_14),
0196     DEBUGFS_REG32(DSI_INIT_SEQ_DATA_15),
0197 };
0198 
0199 static int tegra_dsi_show_regs(struct seq_file *s, void *data)
0200 {
0201     struct drm_info_node *node = s->private;
0202     struct tegra_dsi *dsi = node->info_ent->data;
0203     struct drm_crtc *crtc = dsi->output.encoder.crtc;
0204     struct drm_device *drm = node->minor->dev;
0205     unsigned int i;
0206     int err = 0;
0207 
0208     drm_modeset_lock_all(drm);
0209 
0210     if (!crtc || !crtc->state->active) {
0211         err = -EBUSY;
0212         goto unlock;
0213     }
0214 
0215     for (i = 0; i < ARRAY_SIZE(tegra_dsi_regs); i++) {
0216         unsigned int offset = tegra_dsi_regs[i].offset;
0217 
0218         seq_printf(s, "%-32s %#05x %08x\n", tegra_dsi_regs[i].name,
0219                offset, tegra_dsi_readl(dsi, offset));
0220     }
0221 
0222 unlock:
0223     drm_modeset_unlock_all(drm);
0224     return err;
0225 }
0226 
0227 static struct drm_info_list debugfs_files[] = {
0228     { "regs", tegra_dsi_show_regs, 0, NULL },
0229 };
0230 
0231 static int tegra_dsi_late_register(struct drm_connector *connector)
0232 {
0233     struct tegra_output *output = connector_to_output(connector);
0234     unsigned int i, count = ARRAY_SIZE(debugfs_files);
0235     struct drm_minor *minor = connector->dev->primary;
0236     struct dentry *root = connector->debugfs_entry;
0237     struct tegra_dsi *dsi = to_dsi(output);
0238 
0239     dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
0240                      GFP_KERNEL);
0241     if (!dsi->debugfs_files)
0242         return -ENOMEM;
0243 
0244     for (i = 0; i < count; i++)
0245         dsi->debugfs_files[i].data = dsi;
0246 
0247     drm_debugfs_create_files(dsi->debugfs_files, count, root, minor);
0248 
0249     return 0;
0250 }
0251 
0252 static void tegra_dsi_early_unregister(struct drm_connector *connector)
0253 {
0254     struct tegra_output *output = connector_to_output(connector);
0255     unsigned int count = ARRAY_SIZE(debugfs_files);
0256     struct tegra_dsi *dsi = to_dsi(output);
0257 
0258     drm_debugfs_remove_files(dsi->debugfs_files, count,
0259                  connector->dev->primary);
0260     kfree(dsi->debugfs_files);
0261     dsi->debugfs_files = NULL;
0262 }
0263 
0264 #define PKT_ID0(id) ((((id) & 0x3f) <<  3) | (1 <<  9))
0265 #define PKT_LEN0(len)   (((len) & 0x07) <<  0)
0266 #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
0267 #define PKT_LEN1(len)   (((len) & 0x07) << 10)
0268 #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
0269 #define PKT_LEN2(len)   (((len) & 0x07) << 20)
0270 
0271 #define PKT_LP      (1 << 30)
0272 #define NUM_PKT_SEQ 12
0273 
0274 /*
0275  * non-burst mode with sync pulses
0276  */
0277 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
0278     [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
0279            PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
0280            PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
0281            PKT_LP,
0282     [ 1] = 0,
0283     [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
0284            PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
0285            PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
0286            PKT_LP,
0287     [ 3] = 0,
0288     [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
0289            PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
0290            PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
0291            PKT_LP,
0292     [ 5] = 0,
0293     [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
0294            PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
0295            PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
0296     [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
0297            PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
0298            PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
0299     [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
0300            PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
0301            PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
0302            PKT_LP,
0303     [ 9] = 0,
0304     [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
0305            PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
0306            PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
0307     [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
0308            PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
0309            PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
0310 };
0311 
0312 /*
0313  * non-burst mode with sync events
0314  */
0315 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
0316     [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
0317            PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
0318            PKT_LP,
0319     [ 1] = 0,
0320     [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
0321            PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
0322            PKT_LP,
0323     [ 3] = 0,
0324     [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
0325            PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
0326            PKT_LP,
0327     [ 5] = 0,
0328     [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
0329            PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
0330            PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
0331     [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
0332     [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
0333            PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
0334            PKT_LP,
0335     [ 9] = 0,
0336     [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
0337            PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
0338            PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
0339     [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
0340 };
0341 
0342 static const u32 pkt_seq_command_mode[NUM_PKT_SEQ] = {
0343     [ 0] = 0,
0344     [ 1] = 0,
0345     [ 2] = 0,
0346     [ 3] = 0,
0347     [ 4] = 0,
0348     [ 5] = 0,
0349     [ 6] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(3) | PKT_LP,
0350     [ 7] = 0,
0351     [ 8] = 0,
0352     [ 9] = 0,
0353     [10] = PKT_ID0(MIPI_DSI_DCS_LONG_WRITE) | PKT_LEN0(5) | PKT_LP,
0354     [11] = 0,
0355 };
0356 
0357 static void tegra_dsi_set_phy_timing(struct tegra_dsi *dsi,
0358                      unsigned long period,
0359                      const struct mipi_dphy_timing *timing)
0360 {
0361     u32 value;
0362 
0363     value = DSI_TIMING_FIELD(timing->hsexit, period, 1) << 24 |
0364         DSI_TIMING_FIELD(timing->hstrail, period, 0) << 16 |
0365         DSI_TIMING_FIELD(timing->hszero, period, 3) << 8 |
0366         DSI_TIMING_FIELD(timing->hsprepare, period, 1);
0367     tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
0368 
0369     value = DSI_TIMING_FIELD(timing->clktrail, period, 1) << 24 |
0370         DSI_TIMING_FIELD(timing->clkpost, period, 1) << 16 |
0371         DSI_TIMING_FIELD(timing->clkzero, period, 1) << 8 |
0372         DSI_TIMING_FIELD(timing->lpx, period, 1);
0373     tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
0374 
0375     value = DSI_TIMING_FIELD(timing->clkprepare, period, 1) << 16 |
0376         DSI_TIMING_FIELD(timing->clkpre, period, 1) << 8 |
0377         DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
0378     tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
0379 
0380     value = DSI_TIMING_FIELD(timing->taget, period, 1) << 16 |
0381         DSI_TIMING_FIELD(timing->tasure, period, 1) << 8 |
0382         DSI_TIMING_FIELD(timing->tago, period, 1);
0383     tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
0384 
0385     if (dsi->slave)
0386         tegra_dsi_set_phy_timing(dsi->slave, period, timing);
0387 }
0388 
0389 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
0390                 unsigned int *mulp, unsigned int *divp)
0391 {
0392     switch (format) {
0393     case MIPI_DSI_FMT_RGB666_PACKED:
0394     case MIPI_DSI_FMT_RGB888:
0395         *mulp = 3;
0396         *divp = 1;
0397         break;
0398 
0399     case MIPI_DSI_FMT_RGB565:
0400         *mulp = 2;
0401         *divp = 1;
0402         break;
0403 
0404     case MIPI_DSI_FMT_RGB666:
0405         *mulp = 9;
0406         *divp = 4;
0407         break;
0408 
0409     default:
0410         return -EINVAL;
0411     }
0412 
0413     return 0;
0414 }
0415 
0416 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
0417                 enum tegra_dsi_format *fmt)
0418 {
0419     switch (format) {
0420     case MIPI_DSI_FMT_RGB888:
0421         *fmt = TEGRA_DSI_FORMAT_24P;
0422         break;
0423 
0424     case MIPI_DSI_FMT_RGB666:
0425         *fmt = TEGRA_DSI_FORMAT_18NP;
0426         break;
0427 
0428     case MIPI_DSI_FMT_RGB666_PACKED:
0429         *fmt = TEGRA_DSI_FORMAT_18P;
0430         break;
0431 
0432     case MIPI_DSI_FMT_RGB565:
0433         *fmt = TEGRA_DSI_FORMAT_16P;
0434         break;
0435 
0436     default:
0437         return -EINVAL;
0438     }
0439 
0440     return 0;
0441 }
0442 
0443 static void tegra_dsi_ganged_enable(struct tegra_dsi *dsi, unsigned int start,
0444                     unsigned int size)
0445 {
0446     u32 value;
0447 
0448     tegra_dsi_writel(dsi, start, DSI_GANGED_MODE_START);
0449     tegra_dsi_writel(dsi, size << 16 | size, DSI_GANGED_MODE_SIZE);
0450 
0451     value = DSI_GANGED_MODE_CONTROL_ENABLE;
0452     tegra_dsi_writel(dsi, value, DSI_GANGED_MODE_CONTROL);
0453 }
0454 
0455 static void tegra_dsi_enable(struct tegra_dsi *dsi)
0456 {
0457     u32 value;
0458 
0459     value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
0460     value |= DSI_POWER_CONTROL_ENABLE;
0461     tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
0462 
0463     if (dsi->slave)
0464         tegra_dsi_enable(dsi->slave);
0465 }
0466 
0467 static unsigned int tegra_dsi_get_lanes(struct tegra_dsi *dsi)
0468 {
0469     if (dsi->master)
0470         return dsi->master->lanes + dsi->lanes;
0471 
0472     if (dsi->slave)
0473         return dsi->lanes + dsi->slave->lanes;
0474 
0475     return dsi->lanes;
0476 }
0477 
0478 static void tegra_dsi_configure(struct tegra_dsi *dsi, unsigned int pipe,
0479                 const struct drm_display_mode *mode)
0480 {
0481     unsigned int hact, hsw, hbp, hfp, i, mul, div;
0482     struct tegra_dsi_state *state;
0483     const u32 *pkt_seq;
0484     u32 value;
0485 
0486     /* XXX: pass in state into this function? */
0487     if (dsi->master)
0488         state = tegra_dsi_get_state(dsi->master);
0489     else
0490         state = tegra_dsi_get_state(dsi);
0491 
0492     mul = state->mul;
0493     div = state->div;
0494 
0495     if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
0496         DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
0497         pkt_seq = pkt_seq_video_non_burst_sync_pulses;
0498     } else if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
0499         DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
0500         pkt_seq = pkt_seq_video_non_burst_sync_events;
0501     } else {
0502         DRM_DEBUG_KMS("Command mode\n");
0503         pkt_seq = pkt_seq_command_mode;
0504     }
0505 
0506     value = DSI_CONTROL_CHANNEL(0) |
0507         DSI_CONTROL_FORMAT(state->format) |
0508         DSI_CONTROL_LANES(dsi->lanes - 1) |
0509         DSI_CONTROL_SOURCE(pipe);
0510     tegra_dsi_writel(dsi, value, DSI_CONTROL);
0511 
0512     tegra_dsi_writel(dsi, dsi->video_fifo_depth, DSI_MAX_THRESHOLD);
0513 
0514     value = DSI_HOST_CONTROL_HS;
0515     tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
0516 
0517     value = tegra_dsi_readl(dsi, DSI_CONTROL);
0518 
0519     if (dsi->flags & MIPI_DSI_CLOCK_NON_CONTINUOUS)
0520         value |= DSI_CONTROL_HS_CLK_CTRL;
0521 
0522     value &= ~DSI_CONTROL_TX_TRIG(3);
0523 
0524     /* enable DCS commands for command mode */
0525     if (dsi->flags & MIPI_DSI_MODE_VIDEO)
0526         value &= ~DSI_CONTROL_DCS_ENABLE;
0527     else
0528         value |= DSI_CONTROL_DCS_ENABLE;
0529 
0530     value |= DSI_CONTROL_VIDEO_ENABLE;
0531     value &= ~DSI_CONTROL_HOST_ENABLE;
0532     tegra_dsi_writel(dsi, value, DSI_CONTROL);
0533 
0534     for (i = 0; i < NUM_PKT_SEQ; i++)
0535         tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
0536 
0537     if (dsi->flags & MIPI_DSI_MODE_VIDEO) {
0538         /* horizontal active pixels */
0539         hact = mode->hdisplay * mul / div;
0540 
0541         /* horizontal sync width */
0542         hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
0543 
0544         /* horizontal back porch */
0545         hbp = (mode->htotal - mode->hsync_end) * mul / div;
0546 
0547         if ((dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) == 0)
0548             hbp += hsw;
0549 
0550         /* horizontal front porch */
0551         hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
0552 
0553         /* subtract packet overhead */
0554         hsw -= 10;
0555         hbp -= 14;
0556         hfp -= 8;
0557 
0558         tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
0559         tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
0560         tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
0561         tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
0562 
0563         /* set SOL delay (for non-burst mode only) */
0564         tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
0565 
0566         /* TODO: implement ganged mode */
0567     } else {
0568         u16 bytes;
0569 
0570         if (dsi->master || dsi->slave) {
0571             /*
0572              * For ganged mode, assume symmetric left-right mode.
0573              */
0574             bytes = 1 + (mode->hdisplay / 2) * mul / div;
0575         } else {
0576             /* 1 byte (DCS command) + pixel data */
0577             bytes = 1 + mode->hdisplay * mul / div;
0578         }
0579 
0580         tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_0_1);
0581         tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_2_3);
0582         tegra_dsi_writel(dsi, bytes << 16, DSI_PKT_LEN_4_5);
0583         tegra_dsi_writel(dsi, 0, DSI_PKT_LEN_6_7);
0584 
0585         value = MIPI_DCS_WRITE_MEMORY_START << 8 |
0586             MIPI_DCS_WRITE_MEMORY_CONTINUE;
0587         tegra_dsi_writel(dsi, value, DSI_DCS_CMDS);
0588 
0589         /* set SOL delay */
0590         if (dsi->master || dsi->slave) {
0591             unsigned long delay, bclk, bclk_ganged;
0592             unsigned int lanes = state->lanes;
0593 
0594             /* SOL to valid, valid to FIFO and FIFO write delay */
0595             delay = 4 + 4 + 2;
0596             delay = DIV_ROUND_UP(delay * mul, div * lanes);
0597             /* FIFO read delay */
0598             delay = delay + 6;
0599 
0600             bclk = DIV_ROUND_UP(mode->htotal * mul, div * lanes);
0601             bclk_ganged = DIV_ROUND_UP(bclk * lanes / 2, lanes);
0602             value = bclk - bclk_ganged + delay + 20;
0603         } else {
0604             /* TODO: revisit for non-ganged mode */
0605             value = 8 * mul / div;
0606         }
0607 
0608         tegra_dsi_writel(dsi, value, DSI_SOL_DELAY);
0609     }
0610 
0611     if (dsi->slave) {
0612         tegra_dsi_configure(dsi->slave, pipe, mode);
0613 
0614         /*
0615          * TODO: Support modes other than symmetrical left-right
0616          * split.
0617          */
0618         tegra_dsi_ganged_enable(dsi, 0, mode->hdisplay / 2);
0619         tegra_dsi_ganged_enable(dsi->slave, mode->hdisplay / 2,
0620                     mode->hdisplay / 2);
0621     }
0622 }
0623 
0624 static int tegra_dsi_wait_idle(struct tegra_dsi *dsi, unsigned long timeout)
0625 {
0626     u32 value;
0627 
0628     timeout = jiffies + msecs_to_jiffies(timeout);
0629 
0630     while (time_before(jiffies, timeout)) {
0631         value = tegra_dsi_readl(dsi, DSI_STATUS);
0632         if (value & DSI_STATUS_IDLE)
0633             return 0;
0634 
0635         usleep_range(1000, 2000);
0636     }
0637 
0638     return -ETIMEDOUT;
0639 }
0640 
0641 static void tegra_dsi_video_disable(struct tegra_dsi *dsi)
0642 {
0643     u32 value;
0644 
0645     value = tegra_dsi_readl(dsi, DSI_CONTROL);
0646     value &= ~DSI_CONTROL_VIDEO_ENABLE;
0647     tegra_dsi_writel(dsi, value, DSI_CONTROL);
0648 
0649     if (dsi->slave)
0650         tegra_dsi_video_disable(dsi->slave);
0651 }
0652 
0653 static void tegra_dsi_ganged_disable(struct tegra_dsi *dsi)
0654 {
0655     tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_START);
0656     tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_SIZE);
0657     tegra_dsi_writel(dsi, 0, DSI_GANGED_MODE_CONTROL);
0658 }
0659 
0660 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
0661 {
0662     u32 value;
0663 
0664     value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
0665     tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
0666 
0667     return 0;
0668 }
0669 
0670 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
0671 {
0672     u32 value;
0673     int err;
0674 
0675     /*
0676      * XXX Is this still needed? The module reset is deasserted right
0677      * before this function is called.
0678      */
0679     tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
0680     tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
0681     tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
0682     tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
0683     tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
0684 
0685     /* start calibration */
0686     tegra_dsi_pad_enable(dsi);
0687 
0688     value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
0689         DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
0690         DSI_PAD_OUT_CLK(0x0);
0691     tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
0692 
0693     value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) |
0694         DSI_PAD_PREEMP_PD(0x03) | DSI_PAD_PREEMP_PU(0x3);
0695     tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_3);
0696 
0697     err = tegra_mipi_start_calibration(dsi->mipi);
0698     if (err < 0)
0699         return err;
0700 
0701     return tegra_mipi_finish_calibration(dsi->mipi);
0702 }
0703 
0704 static void tegra_dsi_set_timeout(struct tegra_dsi *dsi, unsigned long bclk,
0705                   unsigned int vrefresh)
0706 {
0707     unsigned int timeout;
0708     u32 value;
0709 
0710     /* one frame high-speed transmission timeout */
0711     timeout = (bclk / vrefresh) / 512;
0712     value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
0713     tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
0714 
0715     /* 2 ms peripheral timeout for panel */
0716     timeout = 2 * bclk / 512 * 1000;
0717     value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
0718     tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
0719 
0720     value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
0721     tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
0722 
0723     if (dsi->slave)
0724         tegra_dsi_set_timeout(dsi->slave, bclk, vrefresh);
0725 }
0726 
0727 static void tegra_dsi_disable(struct tegra_dsi *dsi)
0728 {
0729     u32 value;
0730 
0731     if (dsi->slave) {
0732         tegra_dsi_ganged_disable(dsi->slave);
0733         tegra_dsi_ganged_disable(dsi);
0734     }
0735 
0736     value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
0737     value &= ~DSI_POWER_CONTROL_ENABLE;
0738     tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
0739 
0740     if (dsi->slave)
0741         tegra_dsi_disable(dsi->slave);
0742 
0743     usleep_range(5000, 10000);
0744 }
0745 
0746 static void tegra_dsi_soft_reset(struct tegra_dsi *dsi)
0747 {
0748     u32 value;
0749 
0750     value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
0751     value &= ~DSI_POWER_CONTROL_ENABLE;
0752     tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
0753 
0754     usleep_range(300, 1000);
0755 
0756     value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
0757     value |= DSI_POWER_CONTROL_ENABLE;
0758     tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
0759 
0760     usleep_range(300, 1000);
0761 
0762     value = tegra_dsi_readl(dsi, DSI_TRIGGER);
0763     if (value)
0764         tegra_dsi_writel(dsi, 0, DSI_TRIGGER);
0765 
0766     if (dsi->slave)
0767         tegra_dsi_soft_reset(dsi->slave);
0768 }
0769 
0770 static void tegra_dsi_connector_reset(struct drm_connector *connector)
0771 {
0772     struct tegra_dsi_state *state = kzalloc(sizeof(*state), GFP_KERNEL);
0773 
0774     if (!state)
0775         return;
0776 
0777     if (connector->state) {
0778         __drm_atomic_helper_connector_destroy_state(connector->state);
0779         kfree(connector->state);
0780     }
0781 
0782     __drm_atomic_helper_connector_reset(connector, &state->base);
0783 }
0784 
0785 static struct drm_connector_state *
0786 tegra_dsi_connector_duplicate_state(struct drm_connector *connector)
0787 {
0788     struct tegra_dsi_state *state = to_dsi_state(connector->state);
0789     struct tegra_dsi_state *copy;
0790 
0791     copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
0792     if (!copy)
0793         return NULL;
0794 
0795     __drm_atomic_helper_connector_duplicate_state(connector,
0796                               &copy->base);
0797 
0798     return &copy->base;
0799 }
0800 
0801 static const struct drm_connector_funcs tegra_dsi_connector_funcs = {
0802     .reset = tegra_dsi_connector_reset,
0803     .detect = tegra_output_connector_detect,
0804     .fill_modes = drm_helper_probe_single_connector_modes,
0805     .destroy = tegra_output_connector_destroy,
0806     .atomic_duplicate_state = tegra_dsi_connector_duplicate_state,
0807     .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
0808     .late_register = tegra_dsi_late_register,
0809     .early_unregister = tegra_dsi_early_unregister,
0810 };
0811 
0812 static enum drm_mode_status
0813 tegra_dsi_connector_mode_valid(struct drm_connector *connector,
0814                    struct drm_display_mode *mode)
0815 {
0816     return MODE_OK;
0817 }
0818 
0819 static const struct drm_connector_helper_funcs tegra_dsi_connector_helper_funcs = {
0820     .get_modes = tegra_output_connector_get_modes,
0821     .mode_valid = tegra_dsi_connector_mode_valid,
0822 };
0823 
0824 static void tegra_dsi_unprepare(struct tegra_dsi *dsi)
0825 {
0826     int err;
0827 
0828     if (dsi->slave)
0829         tegra_dsi_unprepare(dsi->slave);
0830 
0831     err = tegra_mipi_disable(dsi->mipi);
0832     if (err < 0)
0833         dev_err(dsi->dev, "failed to disable MIPI calibration: %d\n",
0834             err);
0835 
0836     err = host1x_client_suspend(&dsi->client);
0837     if (err < 0)
0838         dev_err(dsi->dev, "failed to suspend: %d\n", err);
0839 }
0840 
0841 static void tegra_dsi_encoder_disable(struct drm_encoder *encoder)
0842 {
0843     struct tegra_output *output = encoder_to_output(encoder);
0844     struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
0845     struct tegra_dsi *dsi = to_dsi(output);
0846     u32 value;
0847     int err;
0848 
0849     if (output->panel)
0850         drm_panel_disable(output->panel);
0851 
0852     tegra_dsi_video_disable(dsi);
0853 
0854     /*
0855      * The following accesses registers of the display controller, so make
0856      * sure it's only executed when the output is attached to one.
0857      */
0858     if (dc) {
0859         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
0860         value &= ~DSI_ENABLE;
0861         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
0862 
0863         tegra_dc_commit(dc);
0864     }
0865 
0866     err = tegra_dsi_wait_idle(dsi, 100);
0867     if (err < 0)
0868         dev_dbg(dsi->dev, "failed to idle DSI: %d\n", err);
0869 
0870     tegra_dsi_soft_reset(dsi);
0871 
0872     if (output->panel)
0873         drm_panel_unprepare(output->panel);
0874 
0875     tegra_dsi_disable(dsi);
0876 
0877     tegra_dsi_unprepare(dsi);
0878 }
0879 
0880 static int tegra_dsi_prepare(struct tegra_dsi *dsi)
0881 {
0882     int err;
0883 
0884     err = host1x_client_resume(&dsi->client);
0885     if (err < 0) {
0886         dev_err(dsi->dev, "failed to resume: %d\n", err);
0887         return err;
0888     }
0889 
0890     err = tegra_mipi_enable(dsi->mipi);
0891     if (err < 0)
0892         dev_err(dsi->dev, "failed to enable MIPI calibration: %d\n",
0893             err);
0894 
0895     err = tegra_dsi_pad_calibrate(dsi);
0896     if (err < 0)
0897         dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
0898 
0899     if (dsi->slave)
0900         tegra_dsi_prepare(dsi->slave);
0901 
0902     return 0;
0903 }
0904 
0905 static void tegra_dsi_encoder_enable(struct drm_encoder *encoder)
0906 {
0907     struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
0908     struct tegra_output *output = encoder_to_output(encoder);
0909     struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
0910     struct tegra_dsi *dsi = to_dsi(output);
0911     struct tegra_dsi_state *state;
0912     u32 value;
0913     int err;
0914 
0915     err = tegra_dsi_prepare(dsi);
0916     if (err < 0) {
0917         dev_err(dsi->dev, "failed to prepare: %d\n", err);
0918         return;
0919     }
0920 
0921     state = tegra_dsi_get_state(dsi);
0922 
0923     tegra_dsi_set_timeout(dsi, state->bclk, state->vrefresh);
0924 
0925     /*
0926      * The D-PHY timing fields are expressed in byte-clock cycles, so
0927      * multiply the period by 8.
0928      */
0929     tegra_dsi_set_phy_timing(dsi, state->period * 8, &state->timing);
0930 
0931     if (output->panel)
0932         drm_panel_prepare(output->panel);
0933 
0934     tegra_dsi_configure(dsi, dc->pipe, mode);
0935 
0936     /* enable display controller */
0937     value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
0938     value |= DSI_ENABLE;
0939     tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
0940 
0941     tegra_dc_commit(dc);
0942 
0943     /* enable DSI controller */
0944     tegra_dsi_enable(dsi);
0945 
0946     if (output->panel)
0947         drm_panel_enable(output->panel);
0948 }
0949 
0950 static int
0951 tegra_dsi_encoder_atomic_check(struct drm_encoder *encoder,
0952                    struct drm_crtc_state *crtc_state,
0953                    struct drm_connector_state *conn_state)
0954 {
0955     struct tegra_output *output = encoder_to_output(encoder);
0956     struct tegra_dsi_state *state = to_dsi_state(conn_state);
0957     struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
0958     struct tegra_dsi *dsi = to_dsi(output);
0959     unsigned int scdiv;
0960     unsigned long plld;
0961     int err;
0962 
0963     state->pclk = crtc_state->mode.clock * 1000;
0964 
0965     err = tegra_dsi_get_muldiv(dsi->format, &state->mul, &state->div);
0966     if (err < 0)
0967         return err;
0968 
0969     state->lanes = tegra_dsi_get_lanes(dsi);
0970 
0971     err = tegra_dsi_get_format(dsi->format, &state->format);
0972     if (err < 0)
0973         return err;
0974 
0975     state->vrefresh = drm_mode_vrefresh(&crtc_state->mode);
0976 
0977     /* compute byte clock */
0978     state->bclk = (state->pclk * state->mul) / (state->div * state->lanes);
0979 
0980     DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", state->mul, state->div,
0981               state->lanes);
0982     DRM_DEBUG_KMS("format: %u, vrefresh: %u\n", state->format,
0983               state->vrefresh);
0984     DRM_DEBUG_KMS("bclk: %lu\n", state->bclk);
0985 
0986     /*
0987      * Compute bit clock and round up to the next MHz.
0988      */
0989     plld = DIV_ROUND_UP(state->bclk * 8, USEC_PER_SEC) * USEC_PER_SEC;
0990     state->period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, plld);
0991 
0992     err = mipi_dphy_timing_get_default(&state->timing, state->period);
0993     if (err < 0)
0994         return err;
0995 
0996     err = mipi_dphy_timing_validate(&state->timing, state->period);
0997     if (err < 0) {
0998         dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
0999         return err;
1000     }
1001 
1002     /*
1003      * We divide the frequency by two here, but we make up for that by
1004      * setting the shift clock divider (further below) to half of the
1005      * correct value.
1006      */
1007     plld /= 2;
1008 
1009     /*
1010      * Derive pixel clock from bit clock using the shift clock divider.
1011      * Note that this is only half of what we would expect, but we need
1012      * that to make up for the fact that we divided the bit clock by a
1013      * factor of two above.
1014      *
1015      * It's not clear exactly why this is necessary, but the display is
1016      * not working properly otherwise. Perhaps the PLLs cannot generate
1017      * frequencies sufficiently high.
1018      */
1019     scdiv = ((8 * state->mul) / (state->div * state->lanes)) - 2;
1020 
1021     err = tegra_dc_state_setup_clock(dc, crtc_state, dsi->clk_parent,
1022                      plld, scdiv);
1023     if (err < 0) {
1024         dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1025         return err;
1026     }
1027 
1028     return err;
1029 }
1030 
1031 static const struct drm_encoder_helper_funcs tegra_dsi_encoder_helper_funcs = {
1032     .disable = tegra_dsi_encoder_disable,
1033     .enable = tegra_dsi_encoder_enable,
1034     .atomic_check = tegra_dsi_encoder_atomic_check,
1035 };
1036 
1037 static int tegra_dsi_init(struct host1x_client *client)
1038 {
1039     struct drm_device *drm = dev_get_drvdata(client->host);
1040     struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1041     int err;
1042 
1043     /* Gangsters must not register their own outputs. */
1044     if (!dsi->master) {
1045         dsi->output.dev = client->dev;
1046 
1047         drm_connector_init(drm, &dsi->output.connector,
1048                    &tegra_dsi_connector_funcs,
1049                    DRM_MODE_CONNECTOR_DSI);
1050         drm_connector_helper_add(&dsi->output.connector,
1051                      &tegra_dsi_connector_helper_funcs);
1052         dsi->output.connector.dpms = DRM_MODE_DPMS_OFF;
1053 
1054         drm_simple_encoder_init(drm, &dsi->output.encoder,
1055                     DRM_MODE_ENCODER_DSI);
1056         drm_encoder_helper_add(&dsi->output.encoder,
1057                        &tegra_dsi_encoder_helper_funcs);
1058 
1059         drm_connector_attach_encoder(&dsi->output.connector,
1060                           &dsi->output.encoder);
1061         drm_connector_register(&dsi->output.connector);
1062 
1063         err = tegra_output_init(drm, &dsi->output);
1064         if (err < 0)
1065             dev_err(dsi->dev, "failed to initialize output: %d\n",
1066                 err);
1067 
1068         dsi->output.encoder.possible_crtcs = 0x3;
1069     }
1070 
1071     return 0;
1072 }
1073 
1074 static int tegra_dsi_exit(struct host1x_client *client)
1075 {
1076     struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1077 
1078     tegra_output_exit(&dsi->output);
1079 
1080     return 0;
1081 }
1082 
1083 static int tegra_dsi_runtime_suspend(struct host1x_client *client)
1084 {
1085     struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1086     struct device *dev = client->dev;
1087     int err;
1088 
1089     if (dsi->rst) {
1090         err = reset_control_assert(dsi->rst);
1091         if (err < 0) {
1092             dev_err(dev, "failed to assert reset: %d\n", err);
1093             return err;
1094         }
1095     }
1096 
1097     usleep_range(1000, 2000);
1098 
1099     clk_disable_unprepare(dsi->clk_lp);
1100     clk_disable_unprepare(dsi->clk);
1101 
1102     regulator_disable(dsi->vdd);
1103     pm_runtime_put_sync(dev);
1104 
1105     return 0;
1106 }
1107 
1108 static int tegra_dsi_runtime_resume(struct host1x_client *client)
1109 {
1110     struct tegra_dsi *dsi = host1x_client_to_dsi(client);
1111     struct device *dev = client->dev;
1112     int err;
1113 
1114     err = pm_runtime_resume_and_get(dev);
1115     if (err < 0) {
1116         dev_err(dev, "failed to get runtime PM: %d\n", err);
1117         return err;
1118     }
1119 
1120     err = regulator_enable(dsi->vdd);
1121     if (err < 0) {
1122         dev_err(dev, "failed to enable VDD supply: %d\n", err);
1123         goto put_rpm;
1124     }
1125 
1126     err = clk_prepare_enable(dsi->clk);
1127     if (err < 0) {
1128         dev_err(dev, "cannot enable DSI clock: %d\n", err);
1129         goto disable_vdd;
1130     }
1131 
1132     err = clk_prepare_enable(dsi->clk_lp);
1133     if (err < 0) {
1134         dev_err(dev, "cannot enable low-power clock: %d\n", err);
1135         goto disable_clk;
1136     }
1137 
1138     usleep_range(1000, 2000);
1139 
1140     if (dsi->rst) {
1141         err = reset_control_deassert(dsi->rst);
1142         if (err < 0) {
1143             dev_err(dev, "cannot assert reset: %d\n", err);
1144             goto disable_clk_lp;
1145         }
1146     }
1147 
1148     return 0;
1149 
1150 disable_clk_lp:
1151     clk_disable_unprepare(dsi->clk_lp);
1152 disable_clk:
1153     clk_disable_unprepare(dsi->clk);
1154 disable_vdd:
1155     regulator_disable(dsi->vdd);
1156 put_rpm:
1157     pm_runtime_put_sync(dev);
1158     return err;
1159 }
1160 
1161 static const struct host1x_client_ops dsi_client_ops = {
1162     .init = tegra_dsi_init,
1163     .exit = tegra_dsi_exit,
1164     .suspend = tegra_dsi_runtime_suspend,
1165     .resume = tegra_dsi_runtime_resume,
1166 };
1167 
1168 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
1169 {
1170     struct clk *parent;
1171     int err;
1172 
1173     parent = clk_get_parent(dsi->clk);
1174     if (!parent)
1175         return -EINVAL;
1176 
1177     err = clk_set_parent(parent, dsi->clk_parent);
1178     if (err < 0)
1179         return err;
1180 
1181     return 0;
1182 }
1183 
1184 static const char * const error_report[16] = {
1185     "SoT Error",
1186     "SoT Sync Error",
1187     "EoT Sync Error",
1188     "Escape Mode Entry Command Error",
1189     "Low-Power Transmit Sync Error",
1190     "Peripheral Timeout Error",
1191     "False Control Error",
1192     "Contention Detected",
1193     "ECC Error, single-bit",
1194     "ECC Error, multi-bit",
1195     "Checksum Error",
1196     "DSI Data Type Not Recognized",
1197     "DSI VC ID Invalid",
1198     "Invalid Transmission Length",
1199     "Reserved",
1200     "DSI Protocol Violation",
1201 };
1202 
1203 static ssize_t tegra_dsi_read_response(struct tegra_dsi *dsi,
1204                        const struct mipi_dsi_msg *msg,
1205                        size_t count)
1206 {
1207     u8 *rx = msg->rx_buf;
1208     unsigned int i, j, k;
1209     size_t size = 0;
1210     u16 errors;
1211     u32 value;
1212 
1213     /* read and parse packet header */
1214     value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1215 
1216     switch (value & 0x3f) {
1217     case MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT:
1218         errors = (value >> 8) & 0xffff;
1219         dev_dbg(dsi->dev, "Acknowledge and error report: %04x\n",
1220             errors);
1221         for (i = 0; i < ARRAY_SIZE(error_report); i++)
1222             if (errors & BIT(i))
1223                 dev_dbg(dsi->dev, "  %2u: %s\n", i,
1224                     error_report[i]);
1225         break;
1226 
1227     case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE:
1228         rx[0] = (value >> 8) & 0xff;
1229         size = 1;
1230         break;
1231 
1232     case MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE:
1233         rx[0] = (value >>  8) & 0xff;
1234         rx[1] = (value >> 16) & 0xff;
1235         size = 2;
1236         break;
1237 
1238     case MIPI_DSI_RX_DCS_LONG_READ_RESPONSE:
1239         size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1240         break;
1241 
1242     case MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE:
1243         size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff);
1244         break;
1245 
1246     default:
1247         dev_err(dsi->dev, "unhandled response type: %02x\n",
1248             value & 0x3f);
1249         return -EPROTO;
1250     }
1251 
1252     size = min(size, msg->rx_len);
1253 
1254     if (msg->rx_buf && size > 0) {
1255         for (i = 0, j = 0; i < count - 1; i++, j += 4) {
1256             u8 *rx = msg->rx_buf + j;
1257 
1258             value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1259 
1260             for (k = 0; k < 4 && (j + k) < msg->rx_len; k++)
1261                 rx[j + k] = (value >> (k << 3)) & 0xff;
1262         }
1263     }
1264 
1265     return size;
1266 }
1267 
1268 static int tegra_dsi_transmit(struct tegra_dsi *dsi, unsigned long timeout)
1269 {
1270     tegra_dsi_writel(dsi, DSI_TRIGGER_HOST, DSI_TRIGGER);
1271 
1272     timeout = jiffies + msecs_to_jiffies(timeout);
1273 
1274     while (time_before(jiffies, timeout)) {
1275         u32 value = tegra_dsi_readl(dsi, DSI_TRIGGER);
1276         if ((value & DSI_TRIGGER_HOST) == 0)
1277             return 0;
1278 
1279         usleep_range(1000, 2000);
1280     }
1281 
1282     DRM_DEBUG_KMS("timeout waiting for transmission to complete\n");
1283     return -ETIMEDOUT;
1284 }
1285 
1286 static int tegra_dsi_wait_for_response(struct tegra_dsi *dsi,
1287                        unsigned long timeout)
1288 {
1289     timeout = jiffies + msecs_to_jiffies(250);
1290 
1291     while (time_before(jiffies, timeout)) {
1292         u32 value = tegra_dsi_readl(dsi, DSI_STATUS);
1293         u8 count = value & 0x1f;
1294 
1295         if (count > 0)
1296             return count;
1297 
1298         usleep_range(1000, 2000);
1299     }
1300 
1301     DRM_DEBUG_KMS("peripheral returned no data\n");
1302     return -ETIMEDOUT;
1303 }
1304 
1305 static void tegra_dsi_writesl(struct tegra_dsi *dsi, unsigned long offset,
1306                   const void *buffer, size_t size)
1307 {
1308     const u8 *buf = buffer;
1309     size_t i, j;
1310     u32 value;
1311 
1312     for (j = 0; j < size; j += 4) {
1313         value = 0;
1314 
1315         for (i = 0; i < 4 && j + i < size; i++)
1316             value |= buf[j + i] << (i << 3);
1317 
1318         tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1319     }
1320 }
1321 
1322 static ssize_t tegra_dsi_host_transfer(struct mipi_dsi_host *host,
1323                        const struct mipi_dsi_msg *msg)
1324 {
1325     struct tegra_dsi *dsi = host_to_tegra(host);
1326     struct mipi_dsi_packet packet;
1327     const u8 *header;
1328     size_t count;
1329     ssize_t err;
1330     u32 value;
1331 
1332     err = mipi_dsi_create_packet(&packet, msg);
1333     if (err < 0)
1334         return err;
1335 
1336     header = packet.header;
1337 
1338     /* maximum FIFO depth is 1920 words */
1339     if (packet.size > dsi->video_fifo_depth * 4)
1340         return -ENOSPC;
1341 
1342     /* reset underflow/overflow flags */
1343     value = tegra_dsi_readl(dsi, DSI_STATUS);
1344     if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) {
1345         value = DSI_HOST_CONTROL_FIFO_RESET;
1346         tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1347         usleep_range(10, 20);
1348     }
1349 
1350     value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
1351     value |= DSI_POWER_CONTROL_ENABLE;
1352     tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
1353 
1354     usleep_range(5000, 10000);
1355 
1356     value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST |
1357         DSI_HOST_CONTROL_CS | DSI_HOST_CONTROL_ECC;
1358 
1359     if ((msg->flags & MIPI_DSI_MSG_USE_LPM) == 0)
1360         value |= DSI_HOST_CONTROL_HS;
1361 
1362     /*
1363      * The host FIFO has a maximum of 64 words, so larger transmissions
1364      * need to use the video FIFO.
1365      */
1366     if (packet.size > dsi->host_fifo_depth * 4)
1367         value |= DSI_HOST_CONTROL_FIFO_SEL;
1368 
1369     tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1370 
1371     /*
1372      * For reads and messages with explicitly requested ACK, generate a
1373      * BTA sequence after the transmission of the packet.
1374      */
1375     if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1376         (msg->rx_buf && msg->rx_len > 0)) {
1377         value = tegra_dsi_readl(dsi, DSI_HOST_CONTROL);
1378         value |= DSI_HOST_CONTROL_PKT_BTA;
1379         tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
1380     }
1381 
1382     value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE;
1383     tegra_dsi_writel(dsi, value, DSI_CONTROL);
1384 
1385     /* write packet header, ECC is generated by hardware */
1386     value = header[2] << 16 | header[1] << 8 | header[0];
1387     tegra_dsi_writel(dsi, value, DSI_WR_DATA);
1388 
1389     /* write payload (if any) */
1390     if (packet.payload_length > 0)
1391         tegra_dsi_writesl(dsi, DSI_WR_DATA, packet.payload,
1392                   packet.payload_length);
1393 
1394     err = tegra_dsi_transmit(dsi, 250);
1395     if (err < 0)
1396         return err;
1397 
1398     if ((msg->flags & MIPI_DSI_MSG_REQ_ACK) ||
1399         (msg->rx_buf && msg->rx_len > 0)) {
1400         err = tegra_dsi_wait_for_response(dsi, 250);
1401         if (err < 0)
1402             return err;
1403 
1404         count = err;
1405 
1406         value = tegra_dsi_readl(dsi, DSI_RD_DATA);
1407         switch (value) {
1408         case 0x84:
1409             /*
1410             dev_dbg(dsi->dev, "ACK\n");
1411             */
1412             break;
1413 
1414         case 0x87:
1415             /*
1416             dev_dbg(dsi->dev, "ESCAPE\n");
1417             */
1418             break;
1419 
1420         default:
1421             dev_err(dsi->dev, "unknown status: %08x\n", value);
1422             break;
1423         }
1424 
1425         if (count > 1) {
1426             err = tegra_dsi_read_response(dsi, msg, count);
1427             if (err < 0)
1428                 dev_err(dsi->dev,
1429                     "failed to parse response: %zd\n",
1430                     err);
1431             else {
1432                 /*
1433                  * For read commands, return the number of
1434                  * bytes returned by the peripheral.
1435                  */
1436                 count = err;
1437             }
1438         }
1439     } else {
1440         /*
1441          * For write commands, we have transmitted the 4-byte header
1442          * plus the variable-length payload.
1443          */
1444         count = 4 + packet.payload_length;
1445     }
1446 
1447     return count;
1448 }
1449 
1450 static int tegra_dsi_ganged_setup(struct tegra_dsi *dsi)
1451 {
1452     struct clk *parent;
1453     int err;
1454 
1455     /* make sure both DSI controllers share the same PLL */
1456     parent = clk_get_parent(dsi->slave->clk);
1457     if (!parent)
1458         return -EINVAL;
1459 
1460     err = clk_set_parent(parent, dsi->clk_parent);
1461     if (err < 0)
1462         return err;
1463 
1464     return 0;
1465 }
1466 
1467 static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
1468                  struct mipi_dsi_device *device)
1469 {
1470     struct tegra_dsi *dsi = host_to_tegra(host);
1471 
1472     dsi->flags = device->mode_flags;
1473     dsi->format = device->format;
1474     dsi->lanes = device->lanes;
1475 
1476     if (dsi->slave) {
1477         int err;
1478 
1479         dev_dbg(dsi->dev, "attaching dual-channel device %s\n",
1480             dev_name(&device->dev));
1481 
1482         err = tegra_dsi_ganged_setup(dsi);
1483         if (err < 0) {
1484             dev_err(dsi->dev, "failed to set up ganged mode: %d\n",
1485                 err);
1486             return err;
1487         }
1488     }
1489 
1490     /*
1491      * Slaves don't have a panel associated with them, so they provide
1492      * merely the second channel.
1493      */
1494     if (!dsi->master) {
1495         struct tegra_output *output = &dsi->output;
1496 
1497         output->panel = of_drm_find_panel(device->dev.of_node);
1498         if (IS_ERR(output->panel))
1499             output->panel = NULL;
1500 
1501         if (output->panel && output->connector.dev)
1502             drm_helper_hpd_irq_event(output->connector.dev);
1503     }
1504 
1505     return 0;
1506 }
1507 
1508 static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
1509                  struct mipi_dsi_device *device)
1510 {
1511     struct tegra_dsi *dsi = host_to_tegra(host);
1512     struct tegra_output *output = &dsi->output;
1513 
1514     if (output->panel && &device->dev == output->panel->dev) {
1515         output->panel = NULL;
1516 
1517         if (output->connector.dev)
1518             drm_helper_hpd_irq_event(output->connector.dev);
1519     }
1520 
1521     return 0;
1522 }
1523 
1524 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
1525     .attach = tegra_dsi_host_attach,
1526     .detach = tegra_dsi_host_detach,
1527     .transfer = tegra_dsi_host_transfer,
1528 };
1529 
1530 static int tegra_dsi_ganged_probe(struct tegra_dsi *dsi)
1531 {
1532     struct device_node *np;
1533 
1534     np = of_parse_phandle(dsi->dev->of_node, "nvidia,ganged-mode", 0);
1535     if (np) {
1536         struct platform_device *gangster = of_find_device_by_node(np);
1537 
1538         dsi->slave = platform_get_drvdata(gangster);
1539         of_node_put(np);
1540 
1541         if (!dsi->slave) {
1542             put_device(&gangster->dev);
1543             return -EPROBE_DEFER;
1544         }
1545 
1546         dsi->slave->master = dsi;
1547     }
1548 
1549     return 0;
1550 }
1551 
1552 static int tegra_dsi_probe(struct platform_device *pdev)
1553 {
1554     struct tegra_dsi *dsi;
1555     struct resource *regs;
1556     int err;
1557 
1558     dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
1559     if (!dsi)
1560         return -ENOMEM;
1561 
1562     dsi->output.dev = dsi->dev = &pdev->dev;
1563     dsi->video_fifo_depth = 1920;
1564     dsi->host_fifo_depth = 64;
1565 
1566     err = tegra_dsi_ganged_probe(dsi);
1567     if (err < 0)
1568         return err;
1569 
1570     err = tegra_output_probe(&dsi->output);
1571     if (err < 0)
1572         return err;
1573 
1574     dsi->output.connector.polled = DRM_CONNECTOR_POLL_HPD;
1575 
1576     /*
1577      * Assume these values by default. When a DSI peripheral driver
1578      * attaches to the DSI host, the parameters will be taken from
1579      * the attached device.
1580      */
1581     dsi->flags = MIPI_DSI_MODE_VIDEO;
1582     dsi->format = MIPI_DSI_FMT_RGB888;
1583     dsi->lanes = 4;
1584 
1585     if (!pdev->dev.pm_domain) {
1586         dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
1587         if (IS_ERR(dsi->rst))
1588             return PTR_ERR(dsi->rst);
1589     }
1590 
1591     dsi->clk = devm_clk_get(&pdev->dev, NULL);
1592     if (IS_ERR(dsi->clk)) {
1593         dev_err(&pdev->dev, "cannot get DSI clock\n");
1594         return PTR_ERR(dsi->clk);
1595     }
1596 
1597     dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
1598     if (IS_ERR(dsi->clk_lp)) {
1599         dev_err(&pdev->dev, "cannot get low-power clock\n");
1600         return PTR_ERR(dsi->clk_lp);
1601     }
1602 
1603     dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1604     if (IS_ERR(dsi->clk_parent)) {
1605         dev_err(&pdev->dev, "cannot get parent clock\n");
1606         return PTR_ERR(dsi->clk_parent);
1607     }
1608 
1609     dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
1610     if (IS_ERR(dsi->vdd)) {
1611         dev_err(&pdev->dev, "cannot get VDD supply\n");
1612         return PTR_ERR(dsi->vdd);
1613     }
1614 
1615     err = tegra_dsi_setup_clocks(dsi);
1616     if (err < 0) {
1617         dev_err(&pdev->dev, "cannot setup clocks\n");
1618         return err;
1619     }
1620 
1621     regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1622     dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
1623     if (IS_ERR(dsi->regs))
1624         return PTR_ERR(dsi->regs);
1625 
1626     dsi->mipi = tegra_mipi_request(&pdev->dev, pdev->dev.of_node);
1627     if (IS_ERR(dsi->mipi))
1628         return PTR_ERR(dsi->mipi);
1629 
1630     dsi->host.ops = &tegra_dsi_host_ops;
1631     dsi->host.dev = &pdev->dev;
1632 
1633     err = mipi_dsi_host_register(&dsi->host);
1634     if (err < 0) {
1635         dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
1636         goto mipi_free;
1637     }
1638 
1639     platform_set_drvdata(pdev, dsi);
1640     pm_runtime_enable(&pdev->dev);
1641 
1642     INIT_LIST_HEAD(&dsi->client.list);
1643     dsi->client.ops = &dsi_client_ops;
1644     dsi->client.dev = &pdev->dev;
1645 
1646     err = host1x_client_register(&dsi->client);
1647     if (err < 0) {
1648         dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1649             err);
1650         goto unregister;
1651     }
1652 
1653     return 0;
1654 
1655 unregister:
1656     mipi_dsi_host_unregister(&dsi->host);
1657 mipi_free:
1658     tegra_mipi_free(dsi->mipi);
1659     return err;
1660 }
1661 
1662 static int tegra_dsi_remove(struct platform_device *pdev)
1663 {
1664     struct tegra_dsi *dsi = platform_get_drvdata(pdev);
1665     int err;
1666 
1667     pm_runtime_disable(&pdev->dev);
1668 
1669     err = host1x_client_unregister(&dsi->client);
1670     if (err < 0) {
1671         dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1672             err);
1673         return err;
1674     }
1675 
1676     tegra_output_remove(&dsi->output);
1677 
1678     mipi_dsi_host_unregister(&dsi->host);
1679     tegra_mipi_free(dsi->mipi);
1680 
1681     return 0;
1682 }
1683 
1684 static const struct of_device_id tegra_dsi_of_match[] = {
1685     { .compatible = "nvidia,tegra210-dsi", },
1686     { .compatible = "nvidia,tegra132-dsi", },
1687     { .compatible = "nvidia,tegra124-dsi", },
1688     { .compatible = "nvidia,tegra114-dsi", },
1689     { },
1690 };
1691 MODULE_DEVICE_TABLE(of, tegra_dsi_of_match);
1692 
1693 struct platform_driver tegra_dsi_driver = {
1694     .driver = {
1695         .name = "tegra-dsi",
1696         .of_match_table = tegra_dsi_of_match,
1697     },
1698     .probe = tegra_dsi_probe,
1699     .remove = tegra_dsi_remove,
1700 };
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