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0001 // SPDX-License-Identifier: GPL-2.0-only
0002 /*
0003  * Copyright (C) 2012 Avionic Design GmbH
0004  * Copyright (C) 2012-2016 NVIDIA CORPORATION.  All rights reserved.
0005  */
0006 
0007 #include <linux/bitops.h>
0008 #include <linux/host1x.h>
0009 #include <linux/idr.h>
0010 #include <linux/iommu.h>
0011 #include <linux/module.h>
0012 #include <linux/platform_device.h>
0013 #include <linux/pm_runtime.h>
0014 
0015 #include <drm/drm_aperture.h>
0016 #include <drm/drm_atomic.h>
0017 #include <drm/drm_atomic_helper.h>
0018 #include <drm/drm_debugfs.h>
0019 #include <drm/drm_drv.h>
0020 #include <drm/drm_fourcc.h>
0021 #include <drm/drm_framebuffer.h>
0022 #include <drm/drm_ioctl.h>
0023 #include <drm/drm_prime.h>
0024 #include <drm/drm_vblank.h>
0025 
0026 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
0027 #include <asm/dma-iommu.h>
0028 #endif
0029 
0030 #include "dc.h"
0031 #include "drm.h"
0032 #include "gem.h"
0033 #include "uapi.h"
0034 
0035 #define DRIVER_NAME "tegra"
0036 #define DRIVER_DESC "NVIDIA Tegra graphics"
0037 #define DRIVER_DATE "20120330"
0038 #define DRIVER_MAJOR 1
0039 #define DRIVER_MINOR 0
0040 #define DRIVER_PATCHLEVEL 0
0041 
0042 #define CARVEOUT_SZ SZ_64M
0043 #define CDMA_GATHER_FETCHES_MAX_NB 16383
0044 
0045 static int tegra_atomic_check(struct drm_device *drm,
0046                   struct drm_atomic_state *state)
0047 {
0048     int err;
0049 
0050     err = drm_atomic_helper_check(drm, state);
0051     if (err < 0)
0052         return err;
0053 
0054     return tegra_display_hub_atomic_check(drm, state);
0055 }
0056 
0057 static const struct drm_mode_config_funcs tegra_drm_mode_config_funcs = {
0058     .fb_create = tegra_fb_create,
0059 #ifdef CONFIG_DRM_FBDEV_EMULATION
0060     .output_poll_changed = drm_fb_helper_output_poll_changed,
0061 #endif
0062     .atomic_check = tegra_atomic_check,
0063     .atomic_commit = drm_atomic_helper_commit,
0064 };
0065 
0066 static void tegra_atomic_post_commit(struct drm_device *drm,
0067                      struct drm_atomic_state *old_state)
0068 {
0069     struct drm_crtc_state *old_crtc_state __maybe_unused;
0070     struct drm_crtc *crtc;
0071     unsigned int i;
0072 
0073     for_each_old_crtc_in_state(old_state, crtc, old_crtc_state, i)
0074         tegra_crtc_atomic_post_commit(crtc, old_state);
0075 }
0076 
0077 static void tegra_atomic_commit_tail(struct drm_atomic_state *old_state)
0078 {
0079     struct drm_device *drm = old_state->dev;
0080     struct tegra_drm *tegra = drm->dev_private;
0081 
0082     if (tegra->hub) {
0083         bool fence_cookie = dma_fence_begin_signalling();
0084 
0085         drm_atomic_helper_commit_modeset_disables(drm, old_state);
0086         tegra_display_hub_atomic_commit(drm, old_state);
0087         drm_atomic_helper_commit_planes(drm, old_state, 0);
0088         drm_atomic_helper_commit_modeset_enables(drm, old_state);
0089         drm_atomic_helper_commit_hw_done(old_state);
0090         dma_fence_end_signalling(fence_cookie);
0091         drm_atomic_helper_wait_for_vblanks(drm, old_state);
0092         drm_atomic_helper_cleanup_planes(drm, old_state);
0093     } else {
0094         drm_atomic_helper_commit_tail_rpm(old_state);
0095     }
0096 
0097     tegra_atomic_post_commit(drm, old_state);
0098 }
0099 
0100 static const struct drm_mode_config_helper_funcs
0101 tegra_drm_mode_config_helpers = {
0102     .atomic_commit_tail = tegra_atomic_commit_tail,
0103 };
0104 
0105 static int tegra_drm_open(struct drm_device *drm, struct drm_file *filp)
0106 {
0107     struct tegra_drm_file *fpriv;
0108 
0109     fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
0110     if (!fpriv)
0111         return -ENOMEM;
0112 
0113     idr_init_base(&fpriv->legacy_contexts, 1);
0114     xa_init_flags(&fpriv->contexts, XA_FLAGS_ALLOC1);
0115     xa_init(&fpriv->syncpoints);
0116     mutex_init(&fpriv->lock);
0117     filp->driver_priv = fpriv;
0118 
0119     return 0;
0120 }
0121 
0122 static void tegra_drm_context_free(struct tegra_drm_context *context)
0123 {
0124     context->client->ops->close_channel(context);
0125     pm_runtime_put(context->client->base.dev);
0126     kfree(context);
0127 }
0128 
0129 static int host1x_reloc_copy_from_user(struct host1x_reloc *dest,
0130                        struct drm_tegra_reloc __user *src,
0131                        struct drm_device *drm,
0132                        struct drm_file *file)
0133 {
0134     u32 cmdbuf, target;
0135     int err;
0136 
0137     err = get_user(cmdbuf, &src->cmdbuf.handle);
0138     if (err < 0)
0139         return err;
0140 
0141     err = get_user(dest->cmdbuf.offset, &src->cmdbuf.offset);
0142     if (err < 0)
0143         return err;
0144 
0145     err = get_user(target, &src->target.handle);
0146     if (err < 0)
0147         return err;
0148 
0149     err = get_user(dest->target.offset, &src->target.offset);
0150     if (err < 0)
0151         return err;
0152 
0153     err = get_user(dest->shift, &src->shift);
0154     if (err < 0)
0155         return err;
0156 
0157     dest->flags = HOST1X_RELOC_READ | HOST1X_RELOC_WRITE;
0158 
0159     dest->cmdbuf.bo = tegra_gem_lookup(file, cmdbuf);
0160     if (!dest->cmdbuf.bo)
0161         return -ENOENT;
0162 
0163     dest->target.bo = tegra_gem_lookup(file, target);
0164     if (!dest->target.bo)
0165         return -ENOENT;
0166 
0167     return 0;
0168 }
0169 
0170 int tegra_drm_submit(struct tegra_drm_context *context,
0171              struct drm_tegra_submit *args, struct drm_device *drm,
0172              struct drm_file *file)
0173 {
0174     struct host1x_client *client = &context->client->base;
0175     unsigned int num_cmdbufs = args->num_cmdbufs;
0176     unsigned int num_relocs = args->num_relocs;
0177     struct drm_tegra_cmdbuf __user *user_cmdbufs;
0178     struct drm_tegra_reloc __user *user_relocs;
0179     struct drm_tegra_syncpt __user *user_syncpt;
0180     struct drm_tegra_syncpt syncpt;
0181     struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
0182     struct drm_gem_object **refs;
0183     struct host1x_syncpt *sp = NULL;
0184     struct host1x_job *job;
0185     unsigned int num_refs;
0186     int err;
0187 
0188     user_cmdbufs = u64_to_user_ptr(args->cmdbufs);
0189     user_relocs = u64_to_user_ptr(args->relocs);
0190     user_syncpt = u64_to_user_ptr(args->syncpts);
0191 
0192     /* We don't yet support other than one syncpt_incr struct per submit */
0193     if (args->num_syncpts != 1)
0194         return -EINVAL;
0195 
0196     /* We don't yet support waitchks */
0197     if (args->num_waitchks != 0)
0198         return -EINVAL;
0199 
0200     job = host1x_job_alloc(context->channel, args->num_cmdbufs,
0201                    args->num_relocs, false);
0202     if (!job)
0203         return -ENOMEM;
0204 
0205     job->num_relocs = args->num_relocs;
0206     job->client = client;
0207     job->class = client->class;
0208     job->serialize = true;
0209     job->syncpt_recovery = true;
0210 
0211     /*
0212      * Track referenced BOs so that they can be unreferenced after the
0213      * submission is complete.
0214      */
0215     num_refs = num_cmdbufs + num_relocs * 2;
0216 
0217     refs = kmalloc_array(num_refs, sizeof(*refs), GFP_KERNEL);
0218     if (!refs) {
0219         err = -ENOMEM;
0220         goto put;
0221     }
0222 
0223     /* reuse as an iterator later */
0224     num_refs = 0;
0225 
0226     while (num_cmdbufs) {
0227         struct drm_tegra_cmdbuf cmdbuf;
0228         struct host1x_bo *bo;
0229         struct tegra_bo *obj;
0230         u64 offset;
0231 
0232         if (copy_from_user(&cmdbuf, user_cmdbufs, sizeof(cmdbuf))) {
0233             err = -EFAULT;
0234             goto fail;
0235         }
0236 
0237         /*
0238          * The maximum number of CDMA gather fetches is 16383, a higher
0239          * value means the words count is malformed.
0240          */
0241         if (cmdbuf.words > CDMA_GATHER_FETCHES_MAX_NB) {
0242             err = -EINVAL;
0243             goto fail;
0244         }
0245 
0246         bo = tegra_gem_lookup(file, cmdbuf.handle);
0247         if (!bo) {
0248             err = -ENOENT;
0249             goto fail;
0250         }
0251 
0252         offset = (u64)cmdbuf.offset + (u64)cmdbuf.words * sizeof(u32);
0253         obj = host1x_to_tegra_bo(bo);
0254         refs[num_refs++] = &obj->gem;
0255 
0256         /*
0257          * Gather buffer base address must be 4-bytes aligned,
0258          * unaligned offset is malformed and cause commands stream
0259          * corruption on the buffer address relocation.
0260          */
0261         if (offset & 3 || offset > obj->gem.size) {
0262             err = -EINVAL;
0263             goto fail;
0264         }
0265 
0266         host1x_job_add_gather(job, bo, cmdbuf.words, cmdbuf.offset);
0267         num_cmdbufs--;
0268         user_cmdbufs++;
0269     }
0270 
0271     /* copy and resolve relocations from submit */
0272     while (num_relocs--) {
0273         struct host1x_reloc *reloc;
0274         struct tegra_bo *obj;
0275 
0276         err = host1x_reloc_copy_from_user(&job->relocs[num_relocs],
0277                           &user_relocs[num_relocs], drm,
0278                           file);
0279         if (err < 0)
0280             goto fail;
0281 
0282         reloc = &job->relocs[num_relocs];
0283         obj = host1x_to_tegra_bo(reloc->cmdbuf.bo);
0284         refs[num_refs++] = &obj->gem;
0285 
0286         /*
0287          * The unaligned cmdbuf offset will cause an unaligned write
0288          * during of the relocations patching, corrupting the commands
0289          * stream.
0290          */
0291         if (reloc->cmdbuf.offset & 3 ||
0292             reloc->cmdbuf.offset >= obj->gem.size) {
0293             err = -EINVAL;
0294             goto fail;
0295         }
0296 
0297         obj = host1x_to_tegra_bo(reloc->target.bo);
0298         refs[num_refs++] = &obj->gem;
0299 
0300         if (reloc->target.offset >= obj->gem.size) {
0301             err = -EINVAL;
0302             goto fail;
0303         }
0304     }
0305 
0306     if (copy_from_user(&syncpt, user_syncpt, sizeof(syncpt))) {
0307         err = -EFAULT;
0308         goto fail;
0309     }
0310 
0311     /* Syncpoint ref will be dropped on job release. */
0312     sp = host1x_syncpt_get_by_id(host1x, syncpt.id);
0313     if (!sp) {
0314         err = -ENOENT;
0315         goto fail;
0316     }
0317 
0318     job->is_addr_reg = context->client->ops->is_addr_reg;
0319     job->is_valid_class = context->client->ops->is_valid_class;
0320     job->syncpt_incrs = syncpt.incrs;
0321     job->syncpt = sp;
0322     job->timeout = 10000;
0323 
0324     if (args->timeout && args->timeout < 10000)
0325         job->timeout = args->timeout;
0326 
0327     err = host1x_job_pin(job, context->client->base.dev);
0328     if (err)
0329         goto fail;
0330 
0331     err = host1x_job_submit(job);
0332     if (err) {
0333         host1x_job_unpin(job);
0334         goto fail;
0335     }
0336 
0337     args->fence = job->syncpt_end;
0338 
0339 fail:
0340     while (num_refs--)
0341         drm_gem_object_put(refs[num_refs]);
0342 
0343     kfree(refs);
0344 
0345 put:
0346     host1x_job_put(job);
0347     return err;
0348 }
0349 
0350 
0351 #ifdef CONFIG_DRM_TEGRA_STAGING
0352 static int tegra_gem_create(struct drm_device *drm, void *data,
0353                 struct drm_file *file)
0354 {
0355     struct drm_tegra_gem_create *args = data;
0356     struct tegra_bo *bo;
0357 
0358     bo = tegra_bo_create_with_handle(file, drm, args->size, args->flags,
0359                      &args->handle);
0360     if (IS_ERR(bo))
0361         return PTR_ERR(bo);
0362 
0363     return 0;
0364 }
0365 
0366 static int tegra_gem_mmap(struct drm_device *drm, void *data,
0367               struct drm_file *file)
0368 {
0369     struct drm_tegra_gem_mmap *args = data;
0370     struct drm_gem_object *gem;
0371     struct tegra_bo *bo;
0372 
0373     gem = drm_gem_object_lookup(file, args->handle);
0374     if (!gem)
0375         return -EINVAL;
0376 
0377     bo = to_tegra_bo(gem);
0378 
0379     args->offset = drm_vma_node_offset_addr(&bo->gem.vma_node);
0380 
0381     drm_gem_object_put(gem);
0382 
0383     return 0;
0384 }
0385 
0386 static int tegra_syncpt_read(struct drm_device *drm, void *data,
0387                  struct drm_file *file)
0388 {
0389     struct host1x *host = dev_get_drvdata(drm->dev->parent);
0390     struct drm_tegra_syncpt_read *args = data;
0391     struct host1x_syncpt *sp;
0392 
0393     sp = host1x_syncpt_get_by_id_noref(host, args->id);
0394     if (!sp)
0395         return -EINVAL;
0396 
0397     args->value = host1x_syncpt_read_min(sp);
0398     return 0;
0399 }
0400 
0401 static int tegra_syncpt_incr(struct drm_device *drm, void *data,
0402                  struct drm_file *file)
0403 {
0404     struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
0405     struct drm_tegra_syncpt_incr *args = data;
0406     struct host1x_syncpt *sp;
0407 
0408     sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
0409     if (!sp)
0410         return -EINVAL;
0411 
0412     return host1x_syncpt_incr(sp);
0413 }
0414 
0415 static int tegra_syncpt_wait(struct drm_device *drm, void *data,
0416                  struct drm_file *file)
0417 {
0418     struct host1x *host1x = dev_get_drvdata(drm->dev->parent);
0419     struct drm_tegra_syncpt_wait *args = data;
0420     struct host1x_syncpt *sp;
0421 
0422     sp = host1x_syncpt_get_by_id_noref(host1x, args->id);
0423     if (!sp)
0424         return -EINVAL;
0425 
0426     return host1x_syncpt_wait(sp, args->thresh,
0427                   msecs_to_jiffies(args->timeout),
0428                   &args->value);
0429 }
0430 
0431 static int tegra_client_open(struct tegra_drm_file *fpriv,
0432                  struct tegra_drm_client *client,
0433                  struct tegra_drm_context *context)
0434 {
0435     int err;
0436 
0437     err = pm_runtime_resume_and_get(client->base.dev);
0438     if (err)
0439         return err;
0440 
0441     err = client->ops->open_channel(client, context);
0442     if (err < 0) {
0443         pm_runtime_put(client->base.dev);
0444         return err;
0445     }
0446 
0447     err = idr_alloc(&fpriv->legacy_contexts, context, 1, 0, GFP_KERNEL);
0448     if (err < 0) {
0449         client->ops->close_channel(context);
0450         pm_runtime_put(client->base.dev);
0451         return err;
0452     }
0453 
0454     context->client = client;
0455     context->id = err;
0456 
0457     return 0;
0458 }
0459 
0460 static int tegra_open_channel(struct drm_device *drm, void *data,
0461                   struct drm_file *file)
0462 {
0463     struct tegra_drm_file *fpriv = file->driver_priv;
0464     struct tegra_drm *tegra = drm->dev_private;
0465     struct drm_tegra_open_channel *args = data;
0466     struct tegra_drm_context *context;
0467     struct tegra_drm_client *client;
0468     int err = -ENODEV;
0469 
0470     context = kzalloc(sizeof(*context), GFP_KERNEL);
0471     if (!context)
0472         return -ENOMEM;
0473 
0474     mutex_lock(&fpriv->lock);
0475 
0476     list_for_each_entry(client, &tegra->clients, list)
0477         if (client->base.class == args->client) {
0478             err = tegra_client_open(fpriv, client, context);
0479             if (err < 0)
0480                 break;
0481 
0482             args->context = context->id;
0483             break;
0484         }
0485 
0486     if (err < 0)
0487         kfree(context);
0488 
0489     mutex_unlock(&fpriv->lock);
0490     return err;
0491 }
0492 
0493 static int tegra_close_channel(struct drm_device *drm, void *data,
0494                    struct drm_file *file)
0495 {
0496     struct tegra_drm_file *fpriv = file->driver_priv;
0497     struct drm_tegra_close_channel *args = data;
0498     struct tegra_drm_context *context;
0499     int err = 0;
0500 
0501     mutex_lock(&fpriv->lock);
0502 
0503     context = idr_find(&fpriv->legacy_contexts, args->context);
0504     if (!context) {
0505         err = -EINVAL;
0506         goto unlock;
0507     }
0508 
0509     idr_remove(&fpriv->legacy_contexts, context->id);
0510     tegra_drm_context_free(context);
0511 
0512 unlock:
0513     mutex_unlock(&fpriv->lock);
0514     return err;
0515 }
0516 
0517 static int tegra_get_syncpt(struct drm_device *drm, void *data,
0518                 struct drm_file *file)
0519 {
0520     struct tegra_drm_file *fpriv = file->driver_priv;
0521     struct drm_tegra_get_syncpt *args = data;
0522     struct tegra_drm_context *context;
0523     struct host1x_syncpt *syncpt;
0524     int err = 0;
0525 
0526     mutex_lock(&fpriv->lock);
0527 
0528     context = idr_find(&fpriv->legacy_contexts, args->context);
0529     if (!context) {
0530         err = -ENODEV;
0531         goto unlock;
0532     }
0533 
0534     if (args->index >= context->client->base.num_syncpts) {
0535         err = -EINVAL;
0536         goto unlock;
0537     }
0538 
0539     syncpt = context->client->base.syncpts[args->index];
0540     args->id = host1x_syncpt_id(syncpt);
0541 
0542 unlock:
0543     mutex_unlock(&fpriv->lock);
0544     return err;
0545 }
0546 
0547 static int tegra_submit(struct drm_device *drm, void *data,
0548             struct drm_file *file)
0549 {
0550     struct tegra_drm_file *fpriv = file->driver_priv;
0551     struct drm_tegra_submit *args = data;
0552     struct tegra_drm_context *context;
0553     int err;
0554 
0555     mutex_lock(&fpriv->lock);
0556 
0557     context = idr_find(&fpriv->legacy_contexts, args->context);
0558     if (!context) {
0559         err = -ENODEV;
0560         goto unlock;
0561     }
0562 
0563     err = context->client->ops->submit(context, args, drm, file);
0564 
0565 unlock:
0566     mutex_unlock(&fpriv->lock);
0567     return err;
0568 }
0569 
0570 static int tegra_get_syncpt_base(struct drm_device *drm, void *data,
0571                  struct drm_file *file)
0572 {
0573     struct tegra_drm_file *fpriv = file->driver_priv;
0574     struct drm_tegra_get_syncpt_base *args = data;
0575     struct tegra_drm_context *context;
0576     struct host1x_syncpt_base *base;
0577     struct host1x_syncpt *syncpt;
0578     int err = 0;
0579 
0580     mutex_lock(&fpriv->lock);
0581 
0582     context = idr_find(&fpriv->legacy_contexts, args->context);
0583     if (!context) {
0584         err = -ENODEV;
0585         goto unlock;
0586     }
0587 
0588     if (args->syncpt >= context->client->base.num_syncpts) {
0589         err = -EINVAL;
0590         goto unlock;
0591     }
0592 
0593     syncpt = context->client->base.syncpts[args->syncpt];
0594 
0595     base = host1x_syncpt_get_base(syncpt);
0596     if (!base) {
0597         err = -ENXIO;
0598         goto unlock;
0599     }
0600 
0601     args->id = host1x_syncpt_base_id(base);
0602 
0603 unlock:
0604     mutex_unlock(&fpriv->lock);
0605     return err;
0606 }
0607 
0608 static int tegra_gem_set_tiling(struct drm_device *drm, void *data,
0609                 struct drm_file *file)
0610 {
0611     struct drm_tegra_gem_set_tiling *args = data;
0612     enum tegra_bo_tiling_mode mode;
0613     struct drm_gem_object *gem;
0614     unsigned long value = 0;
0615     struct tegra_bo *bo;
0616 
0617     switch (args->mode) {
0618     case DRM_TEGRA_GEM_TILING_MODE_PITCH:
0619         mode = TEGRA_BO_TILING_MODE_PITCH;
0620 
0621         if (args->value != 0)
0622             return -EINVAL;
0623 
0624         break;
0625 
0626     case DRM_TEGRA_GEM_TILING_MODE_TILED:
0627         mode = TEGRA_BO_TILING_MODE_TILED;
0628 
0629         if (args->value != 0)
0630             return -EINVAL;
0631 
0632         break;
0633 
0634     case DRM_TEGRA_GEM_TILING_MODE_BLOCK:
0635         mode = TEGRA_BO_TILING_MODE_BLOCK;
0636 
0637         if (args->value > 5)
0638             return -EINVAL;
0639 
0640         value = args->value;
0641         break;
0642 
0643     default:
0644         return -EINVAL;
0645     }
0646 
0647     gem = drm_gem_object_lookup(file, args->handle);
0648     if (!gem)
0649         return -ENOENT;
0650 
0651     bo = to_tegra_bo(gem);
0652 
0653     bo->tiling.mode = mode;
0654     bo->tiling.value = value;
0655 
0656     drm_gem_object_put(gem);
0657 
0658     return 0;
0659 }
0660 
0661 static int tegra_gem_get_tiling(struct drm_device *drm, void *data,
0662                 struct drm_file *file)
0663 {
0664     struct drm_tegra_gem_get_tiling *args = data;
0665     struct drm_gem_object *gem;
0666     struct tegra_bo *bo;
0667     int err = 0;
0668 
0669     gem = drm_gem_object_lookup(file, args->handle);
0670     if (!gem)
0671         return -ENOENT;
0672 
0673     bo = to_tegra_bo(gem);
0674 
0675     switch (bo->tiling.mode) {
0676     case TEGRA_BO_TILING_MODE_PITCH:
0677         args->mode = DRM_TEGRA_GEM_TILING_MODE_PITCH;
0678         args->value = 0;
0679         break;
0680 
0681     case TEGRA_BO_TILING_MODE_TILED:
0682         args->mode = DRM_TEGRA_GEM_TILING_MODE_TILED;
0683         args->value = 0;
0684         break;
0685 
0686     case TEGRA_BO_TILING_MODE_BLOCK:
0687         args->mode = DRM_TEGRA_GEM_TILING_MODE_BLOCK;
0688         args->value = bo->tiling.value;
0689         break;
0690 
0691     default:
0692         err = -EINVAL;
0693         break;
0694     }
0695 
0696     drm_gem_object_put(gem);
0697 
0698     return err;
0699 }
0700 
0701 static int tegra_gem_set_flags(struct drm_device *drm, void *data,
0702                    struct drm_file *file)
0703 {
0704     struct drm_tegra_gem_set_flags *args = data;
0705     struct drm_gem_object *gem;
0706     struct tegra_bo *bo;
0707 
0708     if (args->flags & ~DRM_TEGRA_GEM_FLAGS)
0709         return -EINVAL;
0710 
0711     gem = drm_gem_object_lookup(file, args->handle);
0712     if (!gem)
0713         return -ENOENT;
0714 
0715     bo = to_tegra_bo(gem);
0716     bo->flags = 0;
0717 
0718     if (args->flags & DRM_TEGRA_GEM_BOTTOM_UP)
0719         bo->flags |= TEGRA_BO_BOTTOM_UP;
0720 
0721     drm_gem_object_put(gem);
0722 
0723     return 0;
0724 }
0725 
0726 static int tegra_gem_get_flags(struct drm_device *drm, void *data,
0727                    struct drm_file *file)
0728 {
0729     struct drm_tegra_gem_get_flags *args = data;
0730     struct drm_gem_object *gem;
0731     struct tegra_bo *bo;
0732 
0733     gem = drm_gem_object_lookup(file, args->handle);
0734     if (!gem)
0735         return -ENOENT;
0736 
0737     bo = to_tegra_bo(gem);
0738     args->flags = 0;
0739 
0740     if (bo->flags & TEGRA_BO_BOTTOM_UP)
0741         args->flags |= DRM_TEGRA_GEM_BOTTOM_UP;
0742 
0743     drm_gem_object_put(gem);
0744 
0745     return 0;
0746 }
0747 #endif
0748 
0749 static const struct drm_ioctl_desc tegra_drm_ioctls[] = {
0750 #ifdef CONFIG_DRM_TEGRA_STAGING
0751     DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_OPEN, tegra_drm_ioctl_channel_open,
0752               DRM_RENDER_ALLOW),
0753     DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_CLOSE, tegra_drm_ioctl_channel_close,
0754               DRM_RENDER_ALLOW),
0755     DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_MAP, tegra_drm_ioctl_channel_map,
0756               DRM_RENDER_ALLOW),
0757     DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_UNMAP, tegra_drm_ioctl_channel_unmap,
0758               DRM_RENDER_ALLOW),
0759     DRM_IOCTL_DEF_DRV(TEGRA_CHANNEL_SUBMIT, tegra_drm_ioctl_channel_submit,
0760               DRM_RENDER_ALLOW),
0761     DRM_IOCTL_DEF_DRV(TEGRA_SYNCPOINT_ALLOCATE, tegra_drm_ioctl_syncpoint_allocate,
0762               DRM_RENDER_ALLOW),
0763     DRM_IOCTL_DEF_DRV(TEGRA_SYNCPOINT_FREE, tegra_drm_ioctl_syncpoint_free,
0764               DRM_RENDER_ALLOW),
0765     DRM_IOCTL_DEF_DRV(TEGRA_SYNCPOINT_WAIT, tegra_drm_ioctl_syncpoint_wait,
0766               DRM_RENDER_ALLOW),
0767 
0768     DRM_IOCTL_DEF_DRV(TEGRA_GEM_CREATE, tegra_gem_create, DRM_RENDER_ALLOW),
0769     DRM_IOCTL_DEF_DRV(TEGRA_GEM_MMAP, tegra_gem_mmap, DRM_RENDER_ALLOW),
0770     DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_READ, tegra_syncpt_read,
0771               DRM_RENDER_ALLOW),
0772     DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_INCR, tegra_syncpt_incr,
0773               DRM_RENDER_ALLOW),
0774     DRM_IOCTL_DEF_DRV(TEGRA_SYNCPT_WAIT, tegra_syncpt_wait,
0775               DRM_RENDER_ALLOW),
0776     DRM_IOCTL_DEF_DRV(TEGRA_OPEN_CHANNEL, tegra_open_channel,
0777               DRM_RENDER_ALLOW),
0778     DRM_IOCTL_DEF_DRV(TEGRA_CLOSE_CHANNEL, tegra_close_channel,
0779               DRM_RENDER_ALLOW),
0780     DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT, tegra_get_syncpt,
0781               DRM_RENDER_ALLOW),
0782     DRM_IOCTL_DEF_DRV(TEGRA_SUBMIT, tegra_submit,
0783               DRM_RENDER_ALLOW),
0784     DRM_IOCTL_DEF_DRV(TEGRA_GET_SYNCPT_BASE, tegra_get_syncpt_base,
0785               DRM_RENDER_ALLOW),
0786     DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_TILING, tegra_gem_set_tiling,
0787               DRM_RENDER_ALLOW),
0788     DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_TILING, tegra_gem_get_tiling,
0789               DRM_RENDER_ALLOW),
0790     DRM_IOCTL_DEF_DRV(TEGRA_GEM_SET_FLAGS, tegra_gem_set_flags,
0791               DRM_RENDER_ALLOW),
0792     DRM_IOCTL_DEF_DRV(TEGRA_GEM_GET_FLAGS, tegra_gem_get_flags,
0793               DRM_RENDER_ALLOW),
0794 #endif
0795 };
0796 
0797 static const struct file_operations tegra_drm_fops = {
0798     .owner = THIS_MODULE,
0799     .open = drm_open,
0800     .release = drm_release,
0801     .unlocked_ioctl = drm_ioctl,
0802     .mmap = tegra_drm_mmap,
0803     .poll = drm_poll,
0804     .read = drm_read,
0805     .compat_ioctl = drm_compat_ioctl,
0806     .llseek = noop_llseek,
0807 };
0808 
0809 static int tegra_drm_context_cleanup(int id, void *p, void *data)
0810 {
0811     struct tegra_drm_context *context = p;
0812 
0813     tegra_drm_context_free(context);
0814 
0815     return 0;
0816 }
0817 
0818 static void tegra_drm_postclose(struct drm_device *drm, struct drm_file *file)
0819 {
0820     struct tegra_drm_file *fpriv = file->driver_priv;
0821 
0822     mutex_lock(&fpriv->lock);
0823     idr_for_each(&fpriv->legacy_contexts, tegra_drm_context_cleanup, NULL);
0824     tegra_drm_uapi_close_file(fpriv);
0825     mutex_unlock(&fpriv->lock);
0826 
0827     idr_destroy(&fpriv->legacy_contexts);
0828     mutex_destroy(&fpriv->lock);
0829     kfree(fpriv);
0830 }
0831 
0832 #ifdef CONFIG_DEBUG_FS
0833 static int tegra_debugfs_framebuffers(struct seq_file *s, void *data)
0834 {
0835     struct drm_info_node *node = (struct drm_info_node *)s->private;
0836     struct drm_device *drm = node->minor->dev;
0837     struct drm_framebuffer *fb;
0838 
0839     mutex_lock(&drm->mode_config.fb_lock);
0840 
0841     list_for_each_entry(fb, &drm->mode_config.fb_list, head) {
0842         seq_printf(s, "%3d: user size: %d x %d, depth %d, %d bpp, refcount %d\n",
0843                fb->base.id, fb->width, fb->height,
0844                fb->format->depth,
0845                fb->format->cpp[0] * 8,
0846                drm_framebuffer_read_refcount(fb));
0847     }
0848 
0849     mutex_unlock(&drm->mode_config.fb_lock);
0850 
0851     return 0;
0852 }
0853 
0854 static int tegra_debugfs_iova(struct seq_file *s, void *data)
0855 {
0856     struct drm_info_node *node = (struct drm_info_node *)s->private;
0857     struct drm_device *drm = node->minor->dev;
0858     struct tegra_drm *tegra = drm->dev_private;
0859     struct drm_printer p = drm_seq_file_printer(s);
0860 
0861     if (tegra->domain) {
0862         mutex_lock(&tegra->mm_lock);
0863         drm_mm_print(&tegra->mm, &p);
0864         mutex_unlock(&tegra->mm_lock);
0865     }
0866 
0867     return 0;
0868 }
0869 
0870 static struct drm_info_list tegra_debugfs_list[] = {
0871     { "framebuffers", tegra_debugfs_framebuffers, 0 },
0872     { "iova", tegra_debugfs_iova, 0 },
0873 };
0874 
0875 static void tegra_debugfs_init(struct drm_minor *minor)
0876 {
0877     drm_debugfs_create_files(tegra_debugfs_list,
0878                  ARRAY_SIZE(tegra_debugfs_list),
0879                  minor->debugfs_root, minor);
0880 }
0881 #endif
0882 
0883 static const struct drm_driver tegra_drm_driver = {
0884     .driver_features = DRIVER_MODESET | DRIVER_GEM |
0885                DRIVER_ATOMIC | DRIVER_RENDER | DRIVER_SYNCOBJ,
0886     .open = tegra_drm_open,
0887     .postclose = tegra_drm_postclose,
0888     .lastclose = drm_fb_helper_lastclose,
0889 
0890 #if defined(CONFIG_DEBUG_FS)
0891     .debugfs_init = tegra_debugfs_init,
0892 #endif
0893 
0894     .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
0895     .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
0896     .gem_prime_import = tegra_gem_prime_import,
0897 
0898     .dumb_create = tegra_bo_dumb_create,
0899 
0900     .ioctls = tegra_drm_ioctls,
0901     .num_ioctls = ARRAY_SIZE(tegra_drm_ioctls),
0902     .fops = &tegra_drm_fops,
0903 
0904     .name = DRIVER_NAME,
0905     .desc = DRIVER_DESC,
0906     .date = DRIVER_DATE,
0907     .major = DRIVER_MAJOR,
0908     .minor = DRIVER_MINOR,
0909     .patchlevel = DRIVER_PATCHLEVEL,
0910 };
0911 
0912 int tegra_drm_register_client(struct tegra_drm *tegra,
0913                   struct tegra_drm_client *client)
0914 {
0915     /*
0916      * When MLOCKs are implemented, change to allocate a shared channel
0917      * only when MLOCKs are disabled.
0918      */
0919     client->shared_channel = host1x_channel_request(&client->base);
0920     if (!client->shared_channel)
0921         return -EBUSY;
0922 
0923     mutex_lock(&tegra->clients_lock);
0924     list_add_tail(&client->list, &tegra->clients);
0925     client->drm = tegra;
0926     mutex_unlock(&tegra->clients_lock);
0927 
0928     return 0;
0929 }
0930 
0931 int tegra_drm_unregister_client(struct tegra_drm *tegra,
0932                 struct tegra_drm_client *client)
0933 {
0934     mutex_lock(&tegra->clients_lock);
0935     list_del_init(&client->list);
0936     client->drm = NULL;
0937     mutex_unlock(&tegra->clients_lock);
0938 
0939     if (client->shared_channel)
0940         host1x_channel_put(client->shared_channel);
0941 
0942     return 0;
0943 }
0944 
0945 int host1x_client_iommu_attach(struct host1x_client *client)
0946 {
0947     struct iommu_domain *domain = iommu_get_domain_for_dev(client->dev);
0948     struct drm_device *drm = dev_get_drvdata(client->host);
0949     struct tegra_drm *tegra = drm->dev_private;
0950     struct iommu_group *group = NULL;
0951     int err;
0952 
0953 #if IS_ENABLED(CONFIG_ARM_DMA_USE_IOMMU)
0954     if (client->dev->archdata.mapping) {
0955         struct dma_iommu_mapping *mapping =
0956                 to_dma_iommu_mapping(client->dev);
0957         arm_iommu_detach_device(client->dev);
0958         arm_iommu_release_mapping(mapping);
0959 
0960         domain = iommu_get_domain_for_dev(client->dev);
0961     }
0962 #endif
0963 
0964     /*
0965      * If the host1x client is already attached to an IOMMU domain that is
0966      * not the shared IOMMU domain, don't try to attach it to a different
0967      * domain. This allows using the IOMMU-backed DMA API.
0968      */
0969     if (domain && domain != tegra->domain)
0970         return 0;
0971 
0972     if (tegra->domain) {
0973         group = iommu_group_get(client->dev);
0974         if (!group)
0975             return -ENODEV;
0976 
0977         if (domain != tegra->domain) {
0978             err = iommu_attach_group(tegra->domain, group);
0979             if (err < 0) {
0980                 iommu_group_put(group);
0981                 return err;
0982             }
0983         }
0984 
0985         tegra->use_explicit_iommu = true;
0986     }
0987 
0988     client->group = group;
0989 
0990     return 0;
0991 }
0992 
0993 void host1x_client_iommu_detach(struct host1x_client *client)
0994 {
0995     struct drm_device *drm = dev_get_drvdata(client->host);
0996     struct tegra_drm *tegra = drm->dev_private;
0997     struct iommu_domain *domain;
0998 
0999     if (client->group) {
1000         /*
1001          * Devices that are part of the same group may no longer be
1002          * attached to a domain at this point because their group may
1003          * have been detached by an earlier client.
1004          */
1005         domain = iommu_get_domain_for_dev(client->dev);
1006         if (domain)
1007             iommu_detach_group(tegra->domain, client->group);
1008 
1009         iommu_group_put(client->group);
1010         client->group = NULL;
1011     }
1012 }
1013 
1014 void *tegra_drm_alloc(struct tegra_drm *tegra, size_t size, dma_addr_t *dma)
1015 {
1016     struct iova *alloc;
1017     void *virt;
1018     gfp_t gfp;
1019     int err;
1020 
1021     if (tegra->domain)
1022         size = iova_align(&tegra->carveout.domain, size);
1023     else
1024         size = PAGE_ALIGN(size);
1025 
1026     gfp = GFP_KERNEL | __GFP_ZERO;
1027     if (!tegra->domain) {
1028         /*
1029          * Many units only support 32-bit addresses, even on 64-bit
1030          * SoCs. If there is no IOMMU to translate into a 32-bit IO
1031          * virtual address space, force allocations to be in the
1032          * lower 32-bit range.
1033          */
1034         gfp |= GFP_DMA;
1035     }
1036 
1037     virt = (void *)__get_free_pages(gfp, get_order(size));
1038     if (!virt)
1039         return ERR_PTR(-ENOMEM);
1040 
1041     if (!tegra->domain) {
1042         /*
1043          * If IOMMU is disabled, devices address physical memory
1044          * directly.
1045          */
1046         *dma = virt_to_phys(virt);
1047         return virt;
1048     }
1049 
1050     alloc = alloc_iova(&tegra->carveout.domain,
1051                size >> tegra->carveout.shift,
1052                tegra->carveout.limit, true);
1053     if (!alloc) {
1054         err = -EBUSY;
1055         goto free_pages;
1056     }
1057 
1058     *dma = iova_dma_addr(&tegra->carveout.domain, alloc);
1059     err = iommu_map(tegra->domain, *dma, virt_to_phys(virt),
1060             size, IOMMU_READ | IOMMU_WRITE);
1061     if (err < 0)
1062         goto free_iova;
1063 
1064     return virt;
1065 
1066 free_iova:
1067     __free_iova(&tegra->carveout.domain, alloc);
1068 free_pages:
1069     free_pages((unsigned long)virt, get_order(size));
1070 
1071     return ERR_PTR(err);
1072 }
1073 
1074 void tegra_drm_free(struct tegra_drm *tegra, size_t size, void *virt,
1075             dma_addr_t dma)
1076 {
1077     if (tegra->domain)
1078         size = iova_align(&tegra->carveout.domain, size);
1079     else
1080         size = PAGE_ALIGN(size);
1081 
1082     if (tegra->domain) {
1083         iommu_unmap(tegra->domain, dma, size);
1084         free_iova(&tegra->carveout.domain,
1085               iova_pfn(&tegra->carveout.domain, dma));
1086     }
1087 
1088     free_pages((unsigned long)virt, get_order(size));
1089 }
1090 
1091 static bool host1x_drm_wants_iommu(struct host1x_device *dev)
1092 {
1093     struct host1x *host1x = dev_get_drvdata(dev->dev.parent);
1094     struct iommu_domain *domain;
1095 
1096     /*
1097      * If the Tegra DRM clients are backed by an IOMMU, push buffers are
1098      * likely to be allocated beyond the 32-bit boundary if sufficient
1099      * system memory is available. This is problematic on earlier Tegra
1100      * generations where host1x supports a maximum of 32 address bits in
1101      * the GATHER opcode. In this case, unless host1x is behind an IOMMU
1102      * as well it won't be able to process buffers allocated beyond the
1103      * 32-bit boundary.
1104      *
1105      * The DMA API will use bounce buffers in this case, so that could
1106      * perhaps still be made to work, even if less efficient, but there
1107      * is another catch: in order to perform cache maintenance on pages
1108      * allocated for discontiguous buffers we need to map and unmap the
1109      * SG table representing these buffers. This is fine for something
1110      * small like a push buffer, but it exhausts the bounce buffer pool
1111      * (typically on the order of a few MiB) for framebuffers (many MiB
1112      * for any modern resolution).
1113      *
1114      * Work around this by making sure that Tegra DRM clients only use
1115      * an IOMMU if the parent host1x also uses an IOMMU.
1116      *
1117      * Note that there's still a small gap here that we don't cover: if
1118      * the DMA API is backed by an IOMMU there's no way to control which
1119      * device is attached to an IOMMU and which isn't, except via wiring
1120      * up the device tree appropriately. This is considered an problem
1121      * of integration, so care must be taken for the DT to be consistent.
1122      */
1123     domain = iommu_get_domain_for_dev(dev->dev.parent);
1124 
1125     /*
1126      * Tegra20 and Tegra30 don't support addressing memory beyond the
1127      * 32-bit boundary, so the regular GATHER opcodes will always be
1128      * sufficient and whether or not the host1x is attached to an IOMMU
1129      * doesn't matter.
1130      */
1131     if (!domain && host1x_get_dma_mask(host1x) <= DMA_BIT_MASK(32))
1132         return true;
1133 
1134     return domain != NULL;
1135 }
1136 
1137 static int host1x_drm_probe(struct host1x_device *dev)
1138 {
1139     struct tegra_drm *tegra;
1140     struct drm_device *drm;
1141     int err;
1142 
1143     drm = drm_dev_alloc(&tegra_drm_driver, &dev->dev);
1144     if (IS_ERR(drm))
1145         return PTR_ERR(drm);
1146 
1147     tegra = kzalloc(sizeof(*tegra), GFP_KERNEL);
1148     if (!tegra) {
1149         err = -ENOMEM;
1150         goto put;
1151     }
1152 
1153     if (host1x_drm_wants_iommu(dev) && iommu_present(&platform_bus_type)) {
1154         tegra->domain = iommu_domain_alloc(&platform_bus_type);
1155         if (!tegra->domain) {
1156             err = -ENOMEM;
1157             goto free;
1158         }
1159 
1160         err = iova_cache_get();
1161         if (err < 0)
1162             goto domain;
1163     }
1164 
1165     mutex_init(&tegra->clients_lock);
1166     INIT_LIST_HEAD(&tegra->clients);
1167 
1168     dev_set_drvdata(&dev->dev, drm);
1169     drm->dev_private = tegra;
1170     tegra->drm = drm;
1171 
1172     drm_mode_config_init(drm);
1173 
1174     drm->mode_config.min_width = 0;
1175     drm->mode_config.min_height = 0;
1176     drm->mode_config.max_width = 0;
1177     drm->mode_config.max_height = 0;
1178 
1179     drm->mode_config.normalize_zpos = true;
1180 
1181     drm->mode_config.funcs = &tegra_drm_mode_config_funcs;
1182     drm->mode_config.helper_private = &tegra_drm_mode_config_helpers;
1183 
1184     err = tegra_drm_fb_prepare(drm);
1185     if (err < 0)
1186         goto config;
1187 
1188     drm_kms_helper_poll_init(drm);
1189 
1190     err = host1x_device_init(dev);
1191     if (err < 0)
1192         goto fbdev;
1193 
1194     /*
1195      * Now that all display controller have been initialized, the maximum
1196      * supported resolution is known and the bitmask for horizontal and
1197      * vertical bitfields can be computed.
1198      */
1199     tegra->hmask = drm->mode_config.max_width - 1;
1200     tegra->vmask = drm->mode_config.max_height - 1;
1201 
1202     if (tegra->use_explicit_iommu) {
1203         u64 carveout_start, carveout_end, gem_start, gem_end;
1204         u64 dma_mask = dma_get_mask(&dev->dev);
1205         dma_addr_t start, end;
1206         unsigned long order;
1207 
1208         start = tegra->domain->geometry.aperture_start & dma_mask;
1209         end = tegra->domain->geometry.aperture_end & dma_mask;
1210 
1211         gem_start = start;
1212         gem_end = end - CARVEOUT_SZ;
1213         carveout_start = gem_end + 1;
1214         carveout_end = end;
1215 
1216         order = __ffs(tegra->domain->pgsize_bitmap);
1217         init_iova_domain(&tegra->carveout.domain, 1UL << order,
1218                  carveout_start >> order);
1219 
1220         tegra->carveout.shift = iova_shift(&tegra->carveout.domain);
1221         tegra->carveout.limit = carveout_end >> tegra->carveout.shift;
1222 
1223         drm_mm_init(&tegra->mm, gem_start, gem_end - gem_start + 1);
1224         mutex_init(&tegra->mm_lock);
1225 
1226         DRM_DEBUG_DRIVER("IOMMU apertures:\n");
1227         DRM_DEBUG_DRIVER("  GEM: %#llx-%#llx\n", gem_start, gem_end);
1228         DRM_DEBUG_DRIVER("  Carveout: %#llx-%#llx\n", carveout_start,
1229                  carveout_end);
1230     } else if (tegra->domain) {
1231         iommu_domain_free(tegra->domain);
1232         tegra->domain = NULL;
1233         iova_cache_put();
1234     }
1235 
1236     if (tegra->hub) {
1237         err = tegra_display_hub_prepare(tegra->hub);
1238         if (err < 0)
1239             goto device;
1240     }
1241 
1242     /* syncpoints are used for full 32-bit hardware VBLANK counters */
1243     drm->max_vblank_count = 0xffffffff;
1244 
1245     err = drm_vblank_init(drm, drm->mode_config.num_crtc);
1246     if (err < 0)
1247         goto hub;
1248 
1249     drm_mode_config_reset(drm);
1250 
1251     err = drm_aperture_remove_framebuffers(false, &tegra_drm_driver);
1252     if (err < 0)
1253         goto hub;
1254 
1255     err = tegra_drm_fb_init(drm);
1256     if (err < 0)
1257         goto hub;
1258 
1259     err = drm_dev_register(drm, 0);
1260     if (err < 0)
1261         goto fb;
1262 
1263     return 0;
1264 
1265 fb:
1266     tegra_drm_fb_exit(drm);
1267 hub:
1268     if (tegra->hub)
1269         tegra_display_hub_cleanup(tegra->hub);
1270 device:
1271     if (tegra->domain) {
1272         mutex_destroy(&tegra->mm_lock);
1273         drm_mm_takedown(&tegra->mm);
1274         put_iova_domain(&tegra->carveout.domain);
1275         iova_cache_put();
1276     }
1277 
1278     host1x_device_exit(dev);
1279 fbdev:
1280     drm_kms_helper_poll_fini(drm);
1281     tegra_drm_fb_free(drm);
1282 config:
1283     drm_mode_config_cleanup(drm);
1284 domain:
1285     if (tegra->domain)
1286         iommu_domain_free(tegra->domain);
1287 free:
1288     kfree(tegra);
1289 put:
1290     drm_dev_put(drm);
1291     return err;
1292 }
1293 
1294 static int host1x_drm_remove(struct host1x_device *dev)
1295 {
1296     struct drm_device *drm = dev_get_drvdata(&dev->dev);
1297     struct tegra_drm *tegra = drm->dev_private;
1298     int err;
1299 
1300     drm_dev_unregister(drm);
1301 
1302     drm_kms_helper_poll_fini(drm);
1303     tegra_drm_fb_exit(drm);
1304     drm_atomic_helper_shutdown(drm);
1305     drm_mode_config_cleanup(drm);
1306 
1307     if (tegra->hub)
1308         tegra_display_hub_cleanup(tegra->hub);
1309 
1310     err = host1x_device_exit(dev);
1311     if (err < 0)
1312         dev_err(&dev->dev, "host1x device cleanup failed: %d\n", err);
1313 
1314     if (tegra->domain) {
1315         mutex_destroy(&tegra->mm_lock);
1316         drm_mm_takedown(&tegra->mm);
1317         put_iova_domain(&tegra->carveout.domain);
1318         iova_cache_put();
1319         iommu_domain_free(tegra->domain);
1320     }
1321 
1322     kfree(tegra);
1323     drm_dev_put(drm);
1324 
1325     return 0;
1326 }
1327 
1328 #ifdef CONFIG_PM_SLEEP
1329 static int host1x_drm_suspend(struct device *dev)
1330 {
1331     struct drm_device *drm = dev_get_drvdata(dev);
1332 
1333     return drm_mode_config_helper_suspend(drm);
1334 }
1335 
1336 static int host1x_drm_resume(struct device *dev)
1337 {
1338     struct drm_device *drm = dev_get_drvdata(dev);
1339 
1340     return drm_mode_config_helper_resume(drm);
1341 }
1342 #endif
1343 
1344 static SIMPLE_DEV_PM_OPS(host1x_drm_pm_ops, host1x_drm_suspend,
1345              host1x_drm_resume);
1346 
1347 static const struct of_device_id host1x_drm_subdevs[] = {
1348     { .compatible = "nvidia,tegra20-dc", },
1349     { .compatible = "nvidia,tegra20-hdmi", },
1350     { .compatible = "nvidia,tegra20-gr2d", },
1351     { .compatible = "nvidia,tegra20-gr3d", },
1352     { .compatible = "nvidia,tegra30-dc", },
1353     { .compatible = "nvidia,tegra30-hdmi", },
1354     { .compatible = "nvidia,tegra30-gr2d", },
1355     { .compatible = "nvidia,tegra30-gr3d", },
1356     { .compatible = "nvidia,tegra114-dc", },
1357     { .compatible = "nvidia,tegra114-dsi", },
1358     { .compatible = "nvidia,tegra114-hdmi", },
1359     { .compatible = "nvidia,tegra114-gr2d", },
1360     { .compatible = "nvidia,tegra114-gr3d", },
1361     { .compatible = "nvidia,tegra124-dc", },
1362     { .compatible = "nvidia,tegra124-sor", },
1363     { .compatible = "nvidia,tegra124-hdmi", },
1364     { .compatible = "nvidia,tegra124-dsi", },
1365     { .compatible = "nvidia,tegra124-vic", },
1366     { .compatible = "nvidia,tegra132-dsi", },
1367     { .compatible = "nvidia,tegra210-dc", },
1368     { .compatible = "nvidia,tegra210-dsi", },
1369     { .compatible = "nvidia,tegra210-sor", },
1370     { .compatible = "nvidia,tegra210-sor1", },
1371     { .compatible = "nvidia,tegra210-vic", },
1372     { .compatible = "nvidia,tegra210-nvdec", },
1373     { .compatible = "nvidia,tegra186-display", },
1374     { .compatible = "nvidia,tegra186-dc", },
1375     { .compatible = "nvidia,tegra186-sor", },
1376     { .compatible = "nvidia,tegra186-sor1", },
1377     { .compatible = "nvidia,tegra186-vic", },
1378     { .compatible = "nvidia,tegra186-nvdec", },
1379     { .compatible = "nvidia,tegra194-display", },
1380     { .compatible = "nvidia,tegra194-dc", },
1381     { .compatible = "nvidia,tegra194-sor", },
1382     { .compatible = "nvidia,tegra194-vic", },
1383     { .compatible = "nvidia,tegra194-nvdec", },
1384     { .compatible = "nvidia,tegra234-vic", },
1385     { /* sentinel */ }
1386 };
1387 
1388 static struct host1x_driver host1x_drm_driver = {
1389     .driver = {
1390         .name = "drm",
1391         .pm = &host1x_drm_pm_ops,
1392     },
1393     .probe = host1x_drm_probe,
1394     .remove = host1x_drm_remove,
1395     .subdevs = host1x_drm_subdevs,
1396 };
1397 
1398 static struct platform_driver * const drivers[] = {
1399     &tegra_display_hub_driver,
1400     &tegra_dc_driver,
1401     &tegra_hdmi_driver,
1402     &tegra_dsi_driver,
1403     &tegra_dpaux_driver,
1404     &tegra_sor_driver,
1405     &tegra_gr2d_driver,
1406     &tegra_gr3d_driver,
1407     &tegra_vic_driver,
1408     &tegra_nvdec_driver,
1409 };
1410 
1411 static int __init host1x_drm_init(void)
1412 {
1413     int err;
1414 
1415     if (drm_firmware_drivers_only())
1416         return -ENODEV;
1417 
1418     err = host1x_driver_register(&host1x_drm_driver);
1419     if (err < 0)
1420         return err;
1421 
1422     err = platform_register_drivers(drivers, ARRAY_SIZE(drivers));
1423     if (err < 0)
1424         goto unregister_host1x;
1425 
1426     return 0;
1427 
1428 unregister_host1x:
1429     host1x_driver_unregister(&host1x_drm_driver);
1430     return err;
1431 }
1432 module_init(host1x_drm_init);
1433 
1434 static void __exit host1x_drm_exit(void)
1435 {
1436     platform_unregister_drivers(drivers, ARRAY_SIZE(drivers));
1437     host1x_driver_unregister(&host1x_drm_driver);
1438 }
1439 module_exit(host1x_drm_exit);
1440 
1441 MODULE_AUTHOR("Thierry Reding <thierry.reding@avionic-design.de>");
1442 MODULE_DESCRIPTION("NVIDIA Tegra DRM driver");
1443 MODULE_LICENSE("GPL v2");
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