drm/tegra/dp.h

0001 /* SPDX-License-Identifier: MIT */
0002 /*
0003  * Copyright (C) 2013-2019 NVIDIA Corporation.
0004  * Copyright (C) 2015 Rob Clark
0005  */
0006
0007 #ifndef DRM_TEGRA_DP_H
0008 #define DRM_TEGRA_DP_H 1
0009
0010 #include <linux/types.h>
0011
0012 struct drm_display_info;
0013 struct drm_display_mode;
0014 struct drm_dp_aux;
0015 struct drm_dp_link;
0016
0017 /**
0018  * struct drm_dp_link_caps - DP link capabilities
0019  */
0020 struct drm_dp_link_caps {
0021     /**
0022      * @enhanced_framing:
0023      *
0024      * enhanced framing capability (mandatory as of DP 1.2)
0025      */
0026     bool enhanced_framing;
0027
0028     /**
0029      * tps3_supported:
0030      *
0031      * training pattern sequence 3 supported for equalization
0032      */
0033     bool tps3_supported;
0034
0035     /**
0036      * @fast_training:
0037      *
0038      * AUX CH handshake not required for link training
0039      */
0040     bool fast_training;
0041
0042     /**
0043      * @channel_coding:
0044      *
0045      * ANSI 8B/10B channel coding capability
0046      */
0047     bool channel_coding;
0048
0049     /**
0050      * @alternate_scrambler_reset:
0051      *
0052      * eDP alternate scrambler reset capability
0053      */
0054     bool alternate_scrambler_reset;
0055 };
0056
0057 void drm_dp_link_caps_copy(struct drm_dp_link_caps *dest,
0058                const struct drm_dp_link_caps *src);
0059
0060 /**
0061  * struct drm_dp_link_ops - DP link operations
0062  */
0063 struct drm_dp_link_ops {
0064     /**
0065      * @apply_training:
0066      */
0067     int (*apply_training)(struct drm_dp_link *link);
0068
0069     /**
0070      * @configure:
0071      */
0072     int (*configure)(struct drm_dp_link *link);
0073 };
0074
0075 #define DP_TRAIN_VOLTAGE_SWING_LEVEL(x) ((x) << 0)
0076 #define DP_TRAIN_PRE_EMPHASIS_LEVEL(x) ((x) << 3)
0077 #define DP_LANE_POST_CURSOR(i, x) (((x) & 0x3) << (((i) & 1) << 2))
0078
0079 /**
0080  * struct drm_dp_link_train_set - link training settings
0081  * @voltage_swing: per-lane voltage swing
0082  * @pre_emphasis: per-lane pre-emphasis
0083  * @post_cursor: per-lane post-cursor
0084  */
0085 struct drm_dp_link_train_set {
0086     unsigned int voltage_swing[4];
0087     unsigned int pre_emphasis[4];
0088     unsigned int post_cursor[4];
0089 };
0090
0091 /**
0092  * struct drm_dp_link_train - link training state information
0093  * @request: currently requested settings
0094  * @adjust: adjustments requested by sink
0095  * @pattern: currently requested training pattern
0096  * @clock_recovered: flag to track if clock recovery has completed
0097  * @channel_equalized: flag to track if channel equalization has completed
0098  */
0099 struct drm_dp_link_train {
0100     struct drm_dp_link_train_set request;
0101     struct drm_dp_link_train_set adjust;
0102
0103     unsigned int pattern;
0104
0105     bool clock_recovered;
0106     bool channel_equalized;
0107 };
0108
0109 /**
0110  * struct drm_dp_link - DP link capabilities and configuration
0111  * @revision: DP specification revision supported on the link
0112  * @max_rate: maximum clock rate supported on the link
0113  * @max_lanes: maximum number of lanes supported on the link
0114  * @caps: capabilities supported on the link (see &drm_dp_link_caps)
0115  * @aux_rd_interval: AUX read interval to use for training (in microseconds)
0116  * @edp: eDP revision (0x11: eDP 1.1, 0x12: eDP 1.2, ...)
0117  * @rate: currently configured link rate
0118  * @lanes: currently configured number of lanes
0119  * @rates: additional supported link rates in kHz (eDP 1.4)
0120  * @num_rates: number of additional supported link rates (eDP 1.4)
0121  */
0122 struct drm_dp_link {
0123     unsigned char revision;
0124     unsigned int max_rate;
0125     unsigned int max_lanes;
0126
0127     struct drm_dp_link_caps caps;
0128
0129     /**
0130      * @cr: clock recovery read interval
0131      * @ce: channel equalization read interval
0132      */
0133     struct {
0134         unsigned int cr;
0135         unsigned int ce;
0136     } aux_rd_interval;
0137
0138     unsigned char edp;
0139
0140     unsigned int rate;
0141     unsigned int lanes;
0142
0143     unsigned long rates[DP_MAX_SUPPORTED_RATES];
0144     unsigned int num_rates;
0145
0146     /**
0147      * @ops: DP link operations
0148      */
0149     const struct drm_dp_link_ops *ops;
0150
0151     /**
0152      * @aux: DP AUX channel
0153      */
0154     struct drm_dp_aux *aux;
0155
0156     /**
0157      * @train: DP link training state
0158      */
0159     struct drm_dp_link_train train;
0160 };
0161
0162 int drm_dp_link_add_rate(struct drm_dp_link *link, unsigned long rate);
0163 int drm_dp_link_remove_rate(struct drm_dp_link *link, unsigned long rate);
0164 void drm_dp_link_update_rates(struct drm_dp_link *link);
0165
0166 int drm_dp_link_probe(struct drm_dp_aux *aux, struct drm_dp_link *link);
0167 int drm_dp_link_power_up(struct drm_dp_aux *aux, struct drm_dp_link *link);
0168 int drm_dp_link_power_down(struct drm_dp_aux *aux, struct drm_dp_link *link);
0169 int drm_dp_link_configure(struct drm_dp_aux *aux, struct drm_dp_link *link);
0170 int drm_dp_link_choose(struct drm_dp_link *link,
0171                const struct drm_display_mode *mode,
0172                const struct drm_display_info *info);
0173
0174 void drm_dp_link_train_init(struct drm_dp_link_train *train);
0175 int drm_dp_link_train(struct drm_dp_link *link);
0176
0177 #endif