drm/sun4i/sun8i_tcon_top.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /* Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net> */
0003
0004 #ifndef _SUN8I_TCON_TOP_H_
0005 #define _SUN8I_TCON_TOP_H_
0006
0007 #include <linux/clk.h>
0008 #include <linux/clk-provider.h>
0009 #include <linux/reset.h>
0010 #include <linux/spinlock.h>
0011
0012 #define TCON_TOP_TCON_TV_SETUP_REG  0x00
0013
0014 #define TCON_TOP_PORT_SEL_REG       0x1C
0015 #define TCON_TOP_PORT_DE0_MSK           GENMASK(1, 0)
0016 #define TCON_TOP_PORT_DE1_MSK           GENMASK(5, 4)
0017
0018 #define TCON_TOP_GATE_SRC_REG       0x20
0019 #define TCON_TOP_HDMI_SRC_MSK           GENMASK(29, 28)
0020 #define TCON_TOP_TCON_TV1_GATE          24
0021 #define TCON_TOP_TCON_TV0_GATE          20
0022 #define TCON_TOP_TCON_DSI_GATE          16
0023
0024 #define CLK_NUM                 3
0025
0026 struct sun8i_tcon_top {
0027     struct clk          *bus;
0028     struct clk_hw_onecell_data  *clk_data;
0029     void __iomem            *regs;
0030     struct reset_control        *rst;
0031
0032     /*
0033      * spinlock is used to synchronize access to same
0034      * register where multiple clock gates can be set.
0035      */
0036     spinlock_t          reg_lock;
0037 };
0038
0039 extern const struct of_device_id sun8i_tcon_top_of_table[];
0040
0041 int sun8i_tcon_top_set_hdmi_src(struct device *dev, int tcon);
0042 int sun8i_tcon_top_de_config(struct device *dev, int mixer, int tcon);
0043
0044 #endif /* _SUN8I_TCON_TOP_H_ */