drm/sun4i/sun8i_mixer.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
0004  */
0005
0006 #ifndef _SUN8I_MIXER_H_
0007 #define _SUN8I_MIXER_H_
0008
0009 #include <linux/clk.h>
0010 #include <linux/regmap.h>
0011 #include <linux/reset.h>
0012
0013 #include "sunxi_engine.h"
0014
0015 #define SUN8I_MIXER_SIZE(w, h)          (((h) - 1) << 16 | ((w) - 1))
0016 #define SUN8I_MIXER_COORD(x, y)         ((y) << 16 | (x))
0017
0018 #define SUN8I_MIXER_GLOBAL_CTL          0x0
0019 #define SUN8I_MIXER_GLOBAL_STATUS       0x4
0020 #define SUN8I_MIXER_GLOBAL_DBUFF        0x8
0021 #define SUN8I_MIXER_GLOBAL_SIZE         0xc
0022
0023 #define SUN8I_MIXER_GLOBAL_CTL_RT_EN        BIT(0)
0024
0025 #define SUN8I_MIXER_GLOBAL_DBUFF_ENABLE     BIT(0)
0026
0027 #define DE2_MIXER_UNIT_SIZE         0x6000
0028 #define DE3_MIXER_UNIT_SIZE         0x3000
0029
0030 #define DE2_BLD_BASE                0x1000
0031 #define DE2_CH_BASE             0x2000
0032 #define DE2_CH_SIZE             0x1000
0033
0034 #define DE3_BLD_BASE                0x0800
0035 #define DE3_CH_BASE             0x1000
0036 #define DE3_CH_SIZE             0x0800
0037
0038 #define SUN8I_MIXER_BLEND_PIPE_CTL(base)    ((base) + 0)
0039 #define SUN8I_MIXER_BLEND_ATTR_FCOLOR(base, x)  ((base) + 0x4 + 0x10 * (x))
0040 #define SUN8I_MIXER_BLEND_ATTR_INSIZE(base, x)  ((base) + 0x8 + 0x10 * (x))
0041 #define SUN8I_MIXER_BLEND_ATTR_COORD(base, x)   ((base) + 0xc + 0x10 * (x))
0042 #define SUN8I_MIXER_BLEND_ROUTE(base)       ((base) + 0x80)
0043 #define SUN8I_MIXER_BLEND_PREMULTIPLY(base) ((base) + 0x84)
0044 #define SUN8I_MIXER_BLEND_BKCOLOR(base)     ((base) + 0x88)
0045 #define SUN8I_MIXER_BLEND_OUTSIZE(base)     ((base) + 0x8c)
0046 #define SUN8I_MIXER_BLEND_MODE(base, x)     ((base) + 0x90 + 0x04 * (x))
0047 #define SUN8I_MIXER_BLEND_CK_CTL(base)      ((base) + 0xb0)
0048 #define SUN8I_MIXER_BLEND_CK_CFG(base)      ((base) + 0xb4)
0049 #define SUN8I_MIXER_BLEND_CK_MAX(base, x)   ((base) + 0xc0 + 0x04 * (x))
0050 #define SUN8I_MIXER_BLEND_CK_MIN(base, x)   ((base) + 0xe0 + 0x04 * (x))
0051 #define SUN8I_MIXER_BLEND_OUTCTL(base)      ((base) + 0xfc)
0052 #define SUN50I_MIXER_BLEND_CSC_CTL(base)    ((base) + 0x100)
0053 #define SUN50I_MIXER_BLEND_CSC_COEFF(base, layer, x) \
0054     ((base) + 0x110 + (layer) * 0x30 +  (x) * 4)
0055
0056 #define SUN8I_MIXER_BLEND_PIPE_CTL_EN_MSK   GENMASK(12, 8)
0057 #define SUN8I_MIXER_BLEND_PIPE_CTL_EN(pipe) BIT(8 + pipe)
0058 #define SUN8I_MIXER_BLEND_PIPE_CTL_FC_EN(pipe)  BIT(pipe)
0059
0060 /* colors are always in AARRGGBB format */
0061 #define SUN8I_MIXER_BLEND_COLOR_BLACK       0xff000000
0062 /* The following numbers are some still unknown magic numbers */
0063 #define SUN8I_MIXER_BLEND_MODE_DEF      0x03010301
0064
0065 #define SUN8I_MIXER_BLEND_ROUTE_PIPE_MSK(n) (0xf << ((n) << 2))
0066 #define SUN8I_MIXER_BLEND_ROUTE_PIPE_SHIFT(n)   ((n) << 2)
0067
0068 #define SUN8I_MIXER_BLEND_OUTCTL_INTERLACED BIT(1)
0069
0070 #define SUN50I_MIXER_BLEND_CSC_CTL_EN(ch)   BIT(ch)
0071 #define SUN50I_MIXER_BLEND_CSC_CONST_VAL(d, c)  (((d) << 16) | ((c) & 0xffff))
0072
0073 #define SUN8I_MIXER_FBFMT_ARGB8888  0
0074 #define SUN8I_MIXER_FBFMT_ABGR8888  1
0075 #define SUN8I_MIXER_FBFMT_RGBA8888  2
0076 #define SUN8I_MIXER_FBFMT_BGRA8888  3
0077 #define SUN8I_MIXER_FBFMT_XRGB8888  4
0078 #define SUN8I_MIXER_FBFMT_XBGR8888  5
0079 #define SUN8I_MIXER_FBFMT_RGBX8888  6
0080 #define SUN8I_MIXER_FBFMT_BGRX8888  7
0081 #define SUN8I_MIXER_FBFMT_RGB888    8
0082 #define SUN8I_MIXER_FBFMT_BGR888    9
0083 #define SUN8I_MIXER_FBFMT_RGB565    10
0084 #define SUN8I_MIXER_FBFMT_BGR565    11
0085 #define SUN8I_MIXER_FBFMT_ARGB4444  12
0086 #define SUN8I_MIXER_FBFMT_ABGR4444  13
0087 #define SUN8I_MIXER_FBFMT_RGBA4444  14
0088 #define SUN8I_MIXER_FBFMT_BGRA4444  15
0089 #define SUN8I_MIXER_FBFMT_ARGB1555  16
0090 #define SUN8I_MIXER_FBFMT_ABGR1555  17
0091 #define SUN8I_MIXER_FBFMT_RGBA5551  18
0092 #define SUN8I_MIXER_FBFMT_BGRA5551  19
0093 #define SUN8I_MIXER_FBFMT_ARGB2101010   20
0094 #define SUN8I_MIXER_FBFMT_ABGR2101010   21
0095 #define SUN8I_MIXER_FBFMT_RGBA1010102   22
0096 #define SUN8I_MIXER_FBFMT_BGRA1010102   23
0097
0098 #define SUN8I_MIXER_FBFMT_YUYV      0
0099 #define SUN8I_MIXER_FBFMT_UYVY      1
0100 #define SUN8I_MIXER_FBFMT_YVYU      2
0101 #define SUN8I_MIXER_FBFMT_VYUY      3
0102 #define SUN8I_MIXER_FBFMT_NV16      4
0103 #define SUN8I_MIXER_FBFMT_NV61      5
0104 #define SUN8I_MIXER_FBFMT_YUV422    6
0105 /* format 7 doesn't exist */
0106 #define SUN8I_MIXER_FBFMT_NV12      8
0107 #define SUN8I_MIXER_FBFMT_NV21      9
0108 #define SUN8I_MIXER_FBFMT_YUV420    10
0109 /* format 11 doesn't exist */
0110 /* format 12 is semi-planar YUV411 UVUV */
0111 /* format 13 is semi-planar YUV411 VUVU */
0112 #define SUN8I_MIXER_FBFMT_YUV411    14
0113 /* format 15 doesn't exist */
0114 #define SUN8I_MIXER_FBFMT_P010_YUV  16
0115 /* format 17 is P010 YVU */
0116 #define SUN8I_MIXER_FBFMT_P210_YUV  18
0117 /* format 19 is P210 YVU */
0118 /* format 20 is packed YVU444 10-bit */
0119 /* format 21 is packed YUV444 10-bit */
0120
0121 /*
0122  * Sub-engines listed bellow are unused for now. The EN registers are here only
0123  * to be used to disable these sub-engines.
0124  */
0125 #define SUN8I_MIXER_FCE_EN          0xa0000
0126 #define SUN8I_MIXER_BWS_EN          0xa2000
0127 #define SUN8I_MIXER_LTI_EN          0xa4000
0128 #define SUN8I_MIXER_PEAK_EN         0xa6000
0129 #define SUN8I_MIXER_ASE_EN          0xa8000
0130 #define SUN8I_MIXER_FCC_EN          0xaa000
0131 #define SUN8I_MIXER_DCSC_EN         0xb0000
0132
0133 #define SUN50I_MIXER_FCE_EN         0x70000
0134 #define SUN50I_MIXER_PEAK_EN            0x70800
0135 #define SUN50I_MIXER_LCTI_EN            0x71000
0136 #define SUN50I_MIXER_BLS_EN         0x71800
0137 #define SUN50I_MIXER_FCC_EN         0x72000
0138 #define SUN50I_MIXER_DNS_EN         0x80000
0139 #define SUN50I_MIXER_DRC_EN         0xa0000
0140 #define SUN50I_MIXER_FMT_EN         0xa8000
0141 #define SUN50I_MIXER_CDC0_EN            0xd0000
0142 #define SUN50I_MIXER_CDC1_EN            0xd8000
0143
0144 enum {
0145     /* First mixer or second mixer with VEP support. */
0146     CCSC_MIXER0_LAYOUT,
0147     /* Second mixer without VEP support. */
0148     CCSC_MIXER1_LAYOUT,
0149     /* First mixer with the MMIO layout found in the D1 SoC. */
0150     CCSC_D1_MIXER0_LAYOUT,
0151 };
0152
0153 /**
0154  * struct sun8i_mixer_cfg - mixer HW configuration
0155  * @vi_num: number of VI channels
0156  * @ui_num: number of UI channels
0157  * @scaler_mask: bitmask which tells which channel supports scaling
0158  *  First, scaler supports for VI channels is defined and after that, scaler
0159  *  support for UI channels. For example, if mixer has 2 VI channels without
0160  *  scaler and 2 UI channels with scaler, bitmask would be 0xC.
0161  * @ccsc: select set of CCSC base addresses from the enumeration above.
0162  * @mod_rate: module clock rate that needs to be set in order to have
0163  *  a functional block.
0164  * @is_de3: true, if this is next gen display engine 3.0, false otherwise.
0165  * @scaline_yuv: size of a scanline for VI scaler for YUV formats.
0166  */
0167 struct sun8i_mixer_cfg {
0168     int     vi_num;
0169     int     ui_num;
0170     int     scaler_mask;
0171     int     ccsc;
0172     unsigned long   mod_rate;
0173     unsigned int    is_de3 : 1;
0174     unsigned int    scanline_yuv;
0175 };
0176
0177 struct sun8i_mixer {
0178     struct sunxi_engine     engine;
0179
0180     const struct sun8i_mixer_cfg    *cfg;
0181
0182     struct reset_control        *reset;
0183
0184     struct clk          *bus_clk;
0185     struct clk          *mod_clk;
0186 };
0187
0188 static inline struct sun8i_mixer *
0189 engine_to_sun8i_mixer(struct sunxi_engine *engine)
0190 {
0191     return container_of(engine, struct sun8i_mixer, engine);
0192 }
0193
0194 static inline u32
0195 sun8i_blender_base(struct sun8i_mixer *mixer)
0196 {
0197     return mixer->cfg->is_de3 ? DE3_BLD_BASE : DE2_BLD_BASE;
0198 }
0199
0200 static inline u32
0201 sun8i_channel_base(struct sun8i_mixer *mixer, int channel)
0202 {
0203     if (mixer->cfg->is_de3)
0204         return DE3_CH_BASE + channel * DE3_CH_SIZE;
0205     else
0206         return DE2_CH_BASE + channel * DE2_CH_SIZE;
0207 }
0208
0209 int sun8i_mixer_drm_format_to_hw(u32 format, u32 *hw_format);
0210 #endif /* _SUN8I_MIXER_H_ */