drm/sun4i/sun8i_hdmi_phy_clk.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright (C) 2018 Jernej Skrabec <jernej.skrabec@siol.net>
0004  */
0005
0006 #include <linux/clk-provider.h>
0007
0008 #include "sun8i_dw_hdmi.h"
0009
0010 struct sun8i_phy_clk {
0011     struct clk_hw       hw;
0012     struct sun8i_hdmi_phy   *phy;
0013 };
0014
0015 static inline struct sun8i_phy_clk *hw_to_phy_clk(struct clk_hw *hw)
0016 {
0017     return container_of(hw, struct sun8i_phy_clk, hw);
0018 }
0019
0020 static int sun8i_phy_clk_determine_rate(struct clk_hw *hw,
0021                     struct clk_rate_request *req)
0022 {
0023     unsigned long rate = req->rate;
0024     unsigned long best_rate = 0;
0025     struct clk_hw *best_parent = NULL;
0026     struct clk_hw *parent;
0027     int best_div = 1;
0028     int i, p;
0029
0030     for (p = 0; p < clk_hw_get_num_parents(hw); p++) {
0031         parent = clk_hw_get_parent_by_index(hw, p);
0032         if (!parent)
0033             continue;
0034
0035         for (i = 1; i <= 16; i++) {
0036             unsigned long ideal = rate * i;
0037             unsigned long rounded;
0038
0039             rounded = clk_hw_round_rate(parent, ideal);
0040
0041             if (rounded == ideal) {
0042                 best_rate = rounded;
0043                 best_div = i;
0044                 best_parent = parent;
0045                 break;
0046             }
0047
0048             if (!best_rate ||
0049                 abs(rate - rounded / i) <
0050                 abs(rate - best_rate / best_div)) {
0051                 best_rate = rounded;
0052                 best_div = i;
0053                 best_parent = parent;
0054             }
0055         }
0056
0057         if (best_rate / best_div == rate)
0058             break;
0059     }
0060
0061     req->rate = best_rate / best_div;
0062     req->best_parent_rate = best_rate;
0063     req->best_parent_hw = best_parent;
0064
0065     return 0;
0066 }
0067
0068 static unsigned long sun8i_phy_clk_recalc_rate(struct clk_hw *hw,
0069                            unsigned long parent_rate)
0070 {
0071     struct sun8i_phy_clk *priv = hw_to_phy_clk(hw);
0072     u32 reg;
0073
0074     regmap_read(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG, &reg);
0075     reg = ((reg >> SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_SHIFT) &
0076         SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK) + 1;
0077
0078     return parent_rate / reg;
0079 }
0080
0081 static int sun8i_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate,
0082                   unsigned long parent_rate)
0083 {
0084     struct sun8i_phy_clk *priv = hw_to_phy_clk(hw);
0085     unsigned long best_rate = 0;
0086     u8 best_m = 0, m;
0087
0088     for (m = 1; m <= 16; m++) {
0089         unsigned long tmp_rate = parent_rate / m;
0090
0091         if (tmp_rate > rate)
0092             continue;
0093
0094         if (!best_rate ||
0095             (rate - tmp_rate) < (rate - best_rate)) {
0096             best_rate = tmp_rate;
0097             best_m = m;
0098         }
0099     }
0100
0101     regmap_update_bits(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG2_REG,
0102                SUN8I_HDMI_PHY_PLL_CFG2_PREDIV_MSK,
0103                SUN8I_HDMI_PHY_PLL_CFG2_PREDIV(best_m));
0104
0105     return 0;
0106 }
0107
0108 static u8 sun8i_phy_clk_get_parent(struct clk_hw *hw)
0109 {
0110     struct sun8i_phy_clk *priv = hw_to_phy_clk(hw);
0111     u32 reg;
0112
0113     regmap_read(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG, &reg);
0114     reg = (reg & SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK) >>
0115           SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT;
0116
0117     return reg;
0118 }
0119
0120 static int sun8i_phy_clk_set_parent(struct clk_hw *hw, u8 index)
0121 {
0122     struct sun8i_phy_clk *priv = hw_to_phy_clk(hw);
0123
0124     if (index > 1)
0125         return -EINVAL;
0126
0127     regmap_update_bits(priv->phy->regs, SUN8I_HDMI_PHY_PLL_CFG1_REG,
0128                SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_MSK,
0129                index << SUN8I_HDMI_PHY_PLL_CFG1_CKIN_SEL_SHIFT);
0130
0131     return 0;
0132 }
0133
0134 static const struct clk_ops sun8i_phy_clk_ops = {
0135     .determine_rate = sun8i_phy_clk_determine_rate,
0136     .recalc_rate    = sun8i_phy_clk_recalc_rate,
0137     .set_rate   = sun8i_phy_clk_set_rate,
0138
0139     .get_parent = sun8i_phy_clk_get_parent,
0140     .set_parent = sun8i_phy_clk_set_parent,
0141 };
0142
0143 int sun8i_phy_clk_create(struct sun8i_hdmi_phy *phy, struct device *dev,
0144              bool second_parent)
0145 {
0146     struct clk_init_data init;
0147     struct sun8i_phy_clk *priv;
0148     const char *parents[2];
0149
0150     parents[0] = __clk_get_name(phy->clk_pll0);
0151     if (!parents[0])
0152         return -ENODEV;
0153
0154     if (second_parent) {
0155         parents[1] = __clk_get_name(phy->clk_pll1);
0156         if (!parents[1])
0157             return -ENODEV;
0158     }
0159
0160     priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
0161     if (!priv)
0162         return -ENOMEM;
0163
0164     init.name = "hdmi-phy-clk";
0165     init.ops = &sun8i_phy_clk_ops;
0166     init.parent_names = parents;
0167     init.num_parents = second_parent ? 2 : 1;
0168     init.flags = CLK_SET_RATE_PARENT;
0169
0170     priv->phy = phy;
0171     priv->hw.init = &init;
0172
0173     phy->clk_phy = devm_clk_register(dev, &priv->hw);
0174     if (IS_ERR(phy->clk_phy))
0175         return PTR_ERR(phy->clk_phy);
0176
0177     return 0;
0178 }