drm/sun4i/sun8i_dw_hdmi.c

0001 // SPDX-License-Identifier: GPL-2.0+
0002 /*
0003  * Copyright (c) 2018 Jernej Skrabec <jernej.skrabec@siol.net>
0004  */
0005
0006 #include <linux/component.h>
0007 #include <linux/module.h>
0008 #include <linux/of_device.h>
0009 #include <linux/platform_device.h>
0010
0011 #include <drm/drm_crtc_helper.h>
0012 #include <drm/drm_of.h>
0013 #include <drm/drm_simple_kms_helper.h>
0014
0015 #include "sun8i_dw_hdmi.h"
0016 #include "sun8i_tcon_top.h"
0017
0018 static void sun8i_dw_hdmi_encoder_mode_set(struct drm_encoder *encoder,
0019                        struct drm_display_mode *mode,
0020                        struct drm_display_mode *adj_mode)
0021 {
0022     struct sun8i_dw_hdmi *hdmi = encoder_to_sun8i_dw_hdmi(encoder);
0023
0024     clk_set_rate(hdmi->clk_tmds, mode->crtc_clock * 1000);
0025 }
0026
0027 static const struct drm_encoder_helper_funcs
0028 sun8i_dw_hdmi_encoder_helper_funcs = {
0029     .mode_set = sun8i_dw_hdmi_encoder_mode_set,
0030 };
0031
0032 static enum drm_mode_status
0033 sun8i_dw_hdmi_mode_valid_a83t(struct dw_hdmi *hdmi, void *data,
0034                   const struct drm_display_info *info,
0035                   const struct drm_display_mode *mode)
0036 {
0037     if (mode->clock > 297000)
0038         return MODE_CLOCK_HIGH;
0039
0040     return MODE_OK;
0041 }
0042
0043 static enum drm_mode_status
0044 sun8i_dw_hdmi_mode_valid_h6(struct dw_hdmi *hdmi, void *data,
0045                 const struct drm_display_info *info,
0046                 const struct drm_display_mode *mode)
0047 {
0048     /*
0049      * Controller support maximum of 594 MHz, which correlates to
0050      * 4K@60Hz 4:4:4 or RGB.
0051      */
0052     if (mode->clock > 594000)
0053         return MODE_CLOCK_HIGH;
0054
0055     return MODE_OK;
0056 }
0057
0058 static bool sun8i_dw_hdmi_node_is_tcon_top(struct device_node *node)
0059 {
0060     return IS_ENABLED(CONFIG_DRM_SUN8I_TCON_TOP) &&
0061         !!of_match_node(sun8i_tcon_top_of_table, node);
0062 }
0063
0064 static u32 sun8i_dw_hdmi_find_possible_crtcs(struct drm_device *drm,
0065                          struct device_node *node)
0066 {
0067     struct device_node *port, *ep, *remote, *remote_port;
0068     u32 crtcs = 0;
0069
0070     remote = of_graph_get_remote_node(node, 0, -1);
0071     if (!remote)
0072         return 0;
0073
0074     if (sun8i_dw_hdmi_node_is_tcon_top(remote)) {
0075         port = of_graph_get_port_by_id(remote, 4);
0076         if (!port)
0077             goto crtcs_exit;
0078
0079         for_each_child_of_node(port, ep) {
0080             remote_port = of_graph_get_remote_port(ep);
0081             if (remote_port) {
0082                 crtcs |= drm_of_crtc_port_mask(drm, remote_port);
0083                 of_node_put(remote_port);
0084             }
0085         }
0086     } else {
0087         crtcs = drm_of_find_possible_crtcs(drm, node);
0088     }
0089
0090 crtcs_exit:
0091     of_node_put(remote);
0092
0093     return crtcs;
0094 }
0095
0096 static int sun8i_dw_hdmi_bind(struct device *dev, struct device *master,
0097                   void *data)
0098 {
0099     struct platform_device *pdev = to_platform_device(dev);
0100     struct dw_hdmi_plat_data *plat_data;
0101     struct drm_device *drm = data;
0102     struct device_node *phy_node;
0103     struct drm_encoder *encoder;
0104     struct sun8i_dw_hdmi *hdmi;
0105     int ret;
0106
0107     if (!pdev->dev.of_node)
0108         return -ENODEV;
0109
0110     hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
0111     if (!hdmi)
0112         return -ENOMEM;
0113
0114     plat_data = &hdmi->plat_data;
0115     hdmi->dev = &pdev->dev;
0116     encoder = &hdmi->encoder;
0117
0118     hdmi->quirks = of_device_get_match_data(dev);
0119
0120     encoder->possible_crtcs =
0121         sun8i_dw_hdmi_find_possible_crtcs(drm, dev->of_node);
0122     /*
0123      * If we failed to find the CRTC(s) which this encoder is
0124      * supposed to be connected to, it's because the CRTC has
0125      * not been registered yet.  Defer probing, and hope that
0126      * the required CRTC is added later.
0127      */
0128     if (encoder->possible_crtcs == 0)
0129         return -EPROBE_DEFER;
0130
0131     hdmi->rst_ctrl = devm_reset_control_get(dev, "ctrl");
0132     if (IS_ERR(hdmi->rst_ctrl))
0133         return dev_err_probe(dev, PTR_ERR(hdmi->rst_ctrl),
0134                      "Could not get ctrl reset control\n");
0135
0136     hdmi->clk_tmds = devm_clk_get(dev, "tmds");
0137     if (IS_ERR(hdmi->clk_tmds))
0138         return dev_err_probe(dev, PTR_ERR(hdmi->clk_tmds),
0139                      "Couldn't get the tmds clock\n");
0140
0141     hdmi->regulator = devm_regulator_get(dev, "hvcc");
0142     if (IS_ERR(hdmi->regulator))
0143         return dev_err_probe(dev, PTR_ERR(hdmi->regulator),
0144                      "Couldn't get regulator\n");
0145
0146     ret = regulator_enable(hdmi->regulator);
0147     if (ret) {
0148         dev_err(dev, "Failed to enable regulator\n");
0149         return ret;
0150     }
0151
0152     ret = reset_control_deassert(hdmi->rst_ctrl);
0153     if (ret) {
0154         dev_err(dev, "Could not deassert ctrl reset control\n");
0155         goto err_disable_regulator;
0156     }
0157
0158     ret = clk_prepare_enable(hdmi->clk_tmds);
0159     if (ret) {
0160         dev_err(dev, "Could not enable tmds clock\n");
0161         goto err_assert_ctrl_reset;
0162     }
0163
0164     phy_node = of_parse_phandle(dev->of_node, "phys", 0);
0165     if (!phy_node) {
0166         dev_err(dev, "Can't found PHY phandle\n");
0167         ret = -EINVAL;
0168         goto err_disable_clk_tmds;
0169     }
0170
0171     ret = sun8i_hdmi_phy_get(hdmi, phy_node);
0172     of_node_put(phy_node);
0173     if (ret) {
0174         dev_err(dev, "Couldn't get the HDMI PHY\n");
0175         goto err_disable_clk_tmds;
0176     }
0177
0178     ret = sun8i_hdmi_phy_init(hdmi->phy);
0179     if (ret)
0180         goto err_disable_clk_tmds;
0181
0182     drm_encoder_helper_add(encoder, &sun8i_dw_hdmi_encoder_helper_funcs);
0183     drm_simple_encoder_init(drm, encoder, DRM_MODE_ENCODER_TMDS);
0184
0185     plat_data->mode_valid = hdmi->quirks->mode_valid;
0186     plat_data->use_drm_infoframe = hdmi->quirks->use_drm_infoframe;
0187     sun8i_hdmi_phy_set_ops(hdmi->phy, plat_data);
0188
0189     platform_set_drvdata(pdev, hdmi);
0190
0191     hdmi->hdmi = dw_hdmi_bind(pdev, encoder, plat_data);
0192
0193     /*
0194      * If dw_hdmi_bind() fails we'll never call dw_hdmi_unbind(),
0195      * which would have called the encoder cleanup.  Do it manually.
0196      */
0197     if (IS_ERR(hdmi->hdmi)) {
0198         ret = PTR_ERR(hdmi->hdmi);
0199         goto cleanup_encoder;
0200     }
0201
0202     return 0;
0203
0204 cleanup_encoder:
0205     drm_encoder_cleanup(encoder);
0206 err_disable_clk_tmds:
0207     clk_disable_unprepare(hdmi->clk_tmds);
0208 err_assert_ctrl_reset:
0209     reset_control_assert(hdmi->rst_ctrl);
0210 err_disable_regulator:
0211     regulator_disable(hdmi->regulator);
0212
0213     return ret;
0214 }
0215
0216 static void sun8i_dw_hdmi_unbind(struct device *dev, struct device *master,
0217                  void *data)
0218 {
0219     struct sun8i_dw_hdmi *hdmi = dev_get_drvdata(dev);
0220
0221     dw_hdmi_unbind(hdmi->hdmi);
0222     sun8i_hdmi_phy_deinit(hdmi->phy);
0223     clk_disable_unprepare(hdmi->clk_tmds);
0224     reset_control_assert(hdmi->rst_ctrl);
0225     regulator_disable(hdmi->regulator);
0226 }
0227
0228 static const struct component_ops sun8i_dw_hdmi_ops = {
0229     .bind   = sun8i_dw_hdmi_bind,
0230     .unbind = sun8i_dw_hdmi_unbind,
0231 };
0232
0233 static int sun8i_dw_hdmi_probe(struct platform_device *pdev)
0234 {
0235     return component_add(&pdev->dev, &sun8i_dw_hdmi_ops);
0236 }
0237
0238 static int sun8i_dw_hdmi_remove(struct platform_device *pdev)
0239 {
0240     component_del(&pdev->dev, &sun8i_dw_hdmi_ops);
0241
0242     return 0;
0243 }
0244
0245 static const struct sun8i_dw_hdmi_quirks sun8i_a83t_quirks = {
0246     .mode_valid = sun8i_dw_hdmi_mode_valid_a83t,
0247 };
0248
0249 static const struct sun8i_dw_hdmi_quirks sun50i_h6_quirks = {
0250     .mode_valid = sun8i_dw_hdmi_mode_valid_h6,
0251     .use_drm_infoframe = true,
0252 };
0253
0254 static const struct of_device_id sun8i_dw_hdmi_dt_ids[] = {
0255     {
0256         .compatible = "allwinner,sun8i-a83t-dw-hdmi",
0257         .data = &sun8i_a83t_quirks,
0258     },
0259     {
0260         .compatible = "allwinner,sun50i-h6-dw-hdmi",
0261         .data = &sun50i_h6_quirks,
0262     },
0263     { /* sentinel */ },
0264 };
0265 MODULE_DEVICE_TABLE(of, sun8i_dw_hdmi_dt_ids);
0266
0267 static struct platform_driver sun8i_dw_hdmi_pltfm_driver = {
0268     .probe  = sun8i_dw_hdmi_probe,
0269     .remove = sun8i_dw_hdmi_remove,
0270     .driver = {
0271         .name = "sun8i-dw-hdmi",
0272         .of_match_table = sun8i_dw_hdmi_dt_ids,
0273     },
0274 };
0275
0276 static int __init sun8i_dw_hdmi_init(void)
0277 {
0278     int ret;
0279
0280     ret = platform_driver_register(&sun8i_dw_hdmi_pltfm_driver);
0281     if (ret)
0282         return ret;
0283
0284     ret = platform_driver_register(&sun8i_hdmi_phy_driver);
0285     if (ret) {
0286         platform_driver_unregister(&sun8i_dw_hdmi_pltfm_driver);
0287         return ret;
0288     }
0289
0290     return ret;
0291 }
0292
0293 static void __exit sun8i_dw_hdmi_exit(void)
0294 {
0295     platform_driver_unregister(&sun8i_dw_hdmi_pltfm_driver);
0296     platform_driver_unregister(&sun8i_hdmi_phy_driver);
0297 }
0298
0299 module_init(sun8i_dw_hdmi_init);
0300 module_exit(sun8i_dw_hdmi_exit);
0301
0302 MODULE_AUTHOR("Jernej Skrabec <jernej.skrabec@siol.net>");
0303 MODULE_DESCRIPTION("Allwinner DW HDMI bridge");
0304 MODULE_LICENSE("GPL");