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0009 #include <linux/clk.h>
0010 #include <linux/component.h>
0011 #include <linux/module.h>
0012 #include <linux/of_address.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/regmap.h>
0015 #include <linux/reset.h>
0016
0017 #include <drm/drm_atomic_helper.h>
0018 #include <drm/drm_of.h>
0019 #include <drm/drm_panel.h>
0020 #include <drm/drm_print.h>
0021 #include <drm/drm_probe_helper.h>
0022 #include <drm/drm_simple_kms_helper.h>
0023
0024 #include "sun4i_crtc.h"
0025 #include "sun4i_drv.h"
0026 #include "sunxi_engine.h"
0027
0028 #define SUN4I_TVE_EN_REG 0x000
0029 #define SUN4I_TVE_EN_DAC_MAP_MASK GENMASK(19, 4)
0030 #define SUN4I_TVE_EN_DAC_MAP(dac, out) (((out) & 0xf) << (dac + 1) * 4)
0031 #define SUN4I_TVE_EN_ENABLE BIT(0)
0032
0033 #define SUN4I_TVE_CFG0_REG 0x004
0034 #define SUN4I_TVE_CFG0_DAC_CONTROL_54M BIT(26)
0035 #define SUN4I_TVE_CFG0_CORE_DATAPATH_54M BIT(25)
0036 #define SUN4I_TVE_CFG0_CORE_CONTROL_54M BIT(24)
0037 #define SUN4I_TVE_CFG0_YC_EN BIT(17)
0038 #define SUN4I_TVE_CFG0_COMP_EN BIT(16)
0039 #define SUN4I_TVE_CFG0_RES(x) ((x) & 0xf)
0040 #define SUN4I_TVE_CFG0_RES_480i SUN4I_TVE_CFG0_RES(0)
0041 #define SUN4I_TVE_CFG0_RES_576i SUN4I_TVE_CFG0_RES(1)
0042
0043 #define SUN4I_TVE_DAC0_REG 0x008
0044 #define SUN4I_TVE_DAC0_CLOCK_INVERT BIT(24)
0045 #define SUN4I_TVE_DAC0_LUMA(x) (((x) & 3) << 20)
0046 #define SUN4I_TVE_DAC0_LUMA_0_4 SUN4I_TVE_DAC0_LUMA(3)
0047 #define SUN4I_TVE_DAC0_CHROMA(x) (((x) & 3) << 18)
0048 #define SUN4I_TVE_DAC0_CHROMA_0_75 SUN4I_TVE_DAC0_CHROMA(3)
0049 #define SUN4I_TVE_DAC0_INTERNAL_DAC(x) (((x) & 3) << 16)
0050 #define SUN4I_TVE_DAC0_INTERNAL_DAC_37_5_OHMS SUN4I_TVE_DAC0_INTERNAL_DAC(3)
0051 #define SUN4I_TVE_DAC0_DAC_EN(dac) BIT(dac)
0052
0053 #define SUN4I_TVE_NOTCH_REG 0x00c
0054 #define SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(dac, x) ((4 - (x)) << (dac * 3))
0055
0056 #define SUN4I_TVE_CHROMA_FREQ_REG 0x010
0057
0058 #define SUN4I_TVE_PORCH_REG 0x014
0059 #define SUN4I_TVE_PORCH_BACK(x) ((x) << 16)
0060 #define SUN4I_TVE_PORCH_FRONT(x) (x)
0061
0062 #define SUN4I_TVE_LINE_REG 0x01c
0063 #define SUN4I_TVE_LINE_FIRST(x) ((x) << 16)
0064 #define SUN4I_TVE_LINE_NUMBER(x) (x)
0065
0066 #define SUN4I_TVE_LEVEL_REG 0x020
0067 #define SUN4I_TVE_LEVEL_BLANK(x) ((x) << 16)
0068 #define SUN4I_TVE_LEVEL_BLACK(x) (x)
0069
0070 #define SUN4I_TVE_DAC1_REG 0x024
0071 #define SUN4I_TVE_DAC1_AMPLITUDE(dac, x) ((x) << (dac * 8))
0072
0073 #define SUN4I_TVE_DETECT_STA_REG 0x038
0074 #define SUN4I_TVE_DETECT_STA_DAC(dac) BIT((dac * 8))
0075 #define SUN4I_TVE_DETECT_STA_UNCONNECTED 0
0076 #define SUN4I_TVE_DETECT_STA_CONNECTED 1
0077 #define SUN4I_TVE_DETECT_STA_GROUND 2
0078
0079 #define SUN4I_TVE_CB_CR_LVL_REG 0x10c
0080 #define SUN4I_TVE_CB_CR_LVL_CR_BURST(x) ((x) << 8)
0081 #define SUN4I_TVE_CB_CR_LVL_CB_BURST(x) (x)
0082
0083 #define SUN4I_TVE_TINT_BURST_PHASE_REG 0x110
0084 #define SUN4I_TVE_TINT_BURST_PHASE_CHROMA(x) (x)
0085
0086 #define SUN4I_TVE_BURST_WIDTH_REG 0x114
0087 #define SUN4I_TVE_BURST_WIDTH_BREEZEWAY(x) ((x) << 16)
0088 #define SUN4I_TVE_BURST_WIDTH_BURST_WIDTH(x) ((x) << 8)
0089 #define SUN4I_TVE_BURST_WIDTH_HSYNC_WIDTH(x) (x)
0090
0091 #define SUN4I_TVE_CB_CR_GAIN_REG 0x118
0092 #define SUN4I_TVE_CB_CR_GAIN_CR(x) ((x) << 8)
0093 #define SUN4I_TVE_CB_CR_GAIN_CB(x) (x)
0094
0095 #define SUN4I_TVE_SYNC_VBI_REG 0x11c
0096 #define SUN4I_TVE_SYNC_VBI_SYNC(x) ((x) << 16)
0097 #define SUN4I_TVE_SYNC_VBI_VBLANK(x) (x)
0098
0099 #define SUN4I_TVE_ACTIVE_LINE_REG 0x124
0100 #define SUN4I_TVE_ACTIVE_LINE(x) (x)
0101
0102 #define SUN4I_TVE_CHROMA_REG 0x128
0103 #define SUN4I_TVE_CHROMA_COMP_GAIN(x) ((x) & 3)
0104 #define SUN4I_TVE_CHROMA_COMP_GAIN_50 SUN4I_TVE_CHROMA_COMP_GAIN(2)
0105
0106 #define SUN4I_TVE_12C_REG 0x12c
0107 #define SUN4I_TVE_12C_NOTCH_WIDTH_WIDE BIT(8)
0108 #define SUN4I_TVE_12C_COMP_YUV_EN BIT(0)
0109
0110 #define SUN4I_TVE_RESYNC_REG 0x130
0111 #define SUN4I_TVE_RESYNC_FIELD BIT(31)
0112 #define SUN4I_TVE_RESYNC_LINE(x) ((x) << 16)
0113 #define SUN4I_TVE_RESYNC_PIXEL(x) (x)
0114
0115 #define SUN4I_TVE_SLAVE_REG 0x134
0116
0117 #define SUN4I_TVE_WSS_DATA2_REG 0x244
0118
0119 struct color_gains {
0120 u16 cb;
0121 u16 cr;
0122 };
0123
0124 struct burst_levels {
0125 u16 cb;
0126 u16 cr;
0127 };
0128
0129 struct video_levels {
0130 u16 black;
0131 u16 blank;
0132 };
0133
0134 struct resync_parameters {
0135 bool field;
0136 u16 line;
0137 u16 pixel;
0138 };
0139
0140 struct tv_mode {
0141 char *name;
0142
0143 u32 mode;
0144 u32 chroma_freq;
0145 u16 back_porch;
0146 u16 front_porch;
0147 u16 line_number;
0148 u16 vblank_level;
0149
0150 u32 hdisplay;
0151 u16 hfront_porch;
0152 u16 hsync_len;
0153 u16 hback_porch;
0154
0155 u32 vdisplay;
0156 u16 vfront_porch;
0157 u16 vsync_len;
0158 u16 vback_porch;
0159
0160 bool yc_en;
0161 bool dac3_en;
0162 bool dac_bit25_en;
0163
0164 const struct color_gains *color_gains;
0165 const struct burst_levels *burst_levels;
0166 const struct video_levels *video_levels;
0167 const struct resync_parameters *resync_params;
0168 };
0169
0170 struct sun4i_tv {
0171 struct drm_connector connector;
0172 struct drm_encoder encoder;
0173
0174 struct clk *clk;
0175 struct regmap *regs;
0176 struct reset_control *reset;
0177
0178 struct sun4i_drv *drv;
0179 };
0180
0181 static const struct video_levels ntsc_video_levels = {
0182 .black = 282, .blank = 240,
0183 };
0184
0185 static const struct video_levels pal_video_levels = {
0186 .black = 252, .blank = 252,
0187 };
0188
0189 static const struct burst_levels ntsc_burst_levels = {
0190 .cb = 79, .cr = 0,
0191 };
0192
0193 static const struct burst_levels pal_burst_levels = {
0194 .cb = 40, .cr = 40,
0195 };
0196
0197 static const struct color_gains ntsc_color_gains = {
0198 .cb = 160, .cr = 160,
0199 };
0200
0201 static const struct color_gains pal_color_gains = {
0202 .cb = 224, .cr = 224,
0203 };
0204
0205 static const struct resync_parameters ntsc_resync_parameters = {
0206 .field = false, .line = 14, .pixel = 12,
0207 };
0208
0209 static const struct resync_parameters pal_resync_parameters = {
0210 .field = true, .line = 13, .pixel = 12,
0211 };
0212
0213 static const struct tv_mode tv_modes[] = {
0214 {
0215 .name = "NTSC",
0216 .mode = SUN4I_TVE_CFG0_RES_480i,
0217 .chroma_freq = 0x21f07c1f,
0218 .yc_en = true,
0219 .dac3_en = true,
0220 .dac_bit25_en = true,
0221
0222 .back_porch = 118,
0223 .front_porch = 32,
0224 .line_number = 525,
0225
0226 .hdisplay = 720,
0227 .hfront_porch = 18,
0228 .hsync_len = 2,
0229 .hback_porch = 118,
0230
0231 .vdisplay = 480,
0232 .vfront_porch = 26,
0233 .vsync_len = 2,
0234 .vback_porch = 17,
0235
0236 .vblank_level = 240,
0237
0238 .color_gains = &ntsc_color_gains,
0239 .burst_levels = &ntsc_burst_levels,
0240 .video_levels = &ntsc_video_levels,
0241 .resync_params = &ntsc_resync_parameters,
0242 },
0243 {
0244 .name = "PAL",
0245 .mode = SUN4I_TVE_CFG0_RES_576i,
0246 .chroma_freq = 0x2a098acb,
0247
0248 .back_porch = 138,
0249 .front_porch = 24,
0250 .line_number = 625,
0251
0252 .hdisplay = 720,
0253 .hfront_porch = 3,
0254 .hsync_len = 2,
0255 .hback_porch = 139,
0256
0257 .vdisplay = 576,
0258 .vfront_porch = 28,
0259 .vsync_len = 2,
0260 .vback_porch = 19,
0261
0262 .vblank_level = 252,
0263
0264 .color_gains = &pal_color_gains,
0265 .burst_levels = &pal_burst_levels,
0266 .video_levels = &pal_video_levels,
0267 .resync_params = &pal_resync_parameters,
0268 },
0269 };
0270
0271 static inline struct sun4i_tv *
0272 drm_encoder_to_sun4i_tv(struct drm_encoder *encoder)
0273 {
0274 return container_of(encoder, struct sun4i_tv,
0275 encoder);
0276 }
0277
0278 static inline struct sun4i_tv *
0279 drm_connector_to_sun4i_tv(struct drm_connector *connector)
0280 {
0281 return container_of(connector, struct sun4i_tv,
0282 connector);
0283 }
0284
0285
0286
0287
0288
0289
0290
0291
0292 static const struct tv_mode *sun4i_tv_find_tv_by_mode(const struct drm_display_mode *mode)
0293 {
0294 int i;
0295
0296
0297 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
0298 const struct tv_mode *tv_mode = &tv_modes[i];
0299
0300 DRM_DEBUG_DRIVER("Comparing mode %s vs %s",
0301 mode->name, tv_mode->name);
0302
0303 if (!strcmp(mode->name, tv_mode->name))
0304 return tv_mode;
0305 }
0306
0307
0308 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
0309 const struct tv_mode *tv_mode = &tv_modes[i];
0310
0311 DRM_DEBUG_DRIVER("Comparing mode %s vs %s (X: %d vs %d)",
0312 mode->name, tv_mode->name,
0313 mode->vdisplay, tv_mode->vdisplay);
0314
0315 if (mode->vdisplay == tv_mode->vdisplay)
0316 return tv_mode;
0317 }
0318
0319 return NULL;
0320 }
0321
0322 static void sun4i_tv_mode_to_drm_mode(const struct tv_mode *tv_mode,
0323 struct drm_display_mode *mode)
0324 {
0325 DRM_DEBUG_DRIVER("Creating mode %s\n", mode->name);
0326
0327 mode->type = DRM_MODE_TYPE_DRIVER;
0328 mode->clock = 13500;
0329 mode->flags = DRM_MODE_FLAG_INTERLACE;
0330
0331 mode->hdisplay = tv_mode->hdisplay;
0332 mode->hsync_start = mode->hdisplay + tv_mode->hfront_porch;
0333 mode->hsync_end = mode->hsync_start + tv_mode->hsync_len;
0334 mode->htotal = mode->hsync_end + tv_mode->hback_porch;
0335
0336 mode->vdisplay = tv_mode->vdisplay;
0337 mode->vsync_start = mode->vdisplay + tv_mode->vfront_porch;
0338 mode->vsync_end = mode->vsync_start + tv_mode->vsync_len;
0339 mode->vtotal = mode->vsync_end + tv_mode->vback_porch;
0340 }
0341
0342 static void sun4i_tv_disable(struct drm_encoder *encoder)
0343 {
0344 struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
0345 struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
0346
0347 DRM_DEBUG_DRIVER("Disabling the TV Output\n");
0348
0349 regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
0350 SUN4I_TVE_EN_ENABLE,
0351 0);
0352
0353 sunxi_engine_disable_color_correction(crtc->engine);
0354 }
0355
0356 static void sun4i_tv_enable(struct drm_encoder *encoder)
0357 {
0358 struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
0359 struct sun4i_crtc *crtc = drm_crtc_to_sun4i_crtc(encoder->crtc);
0360
0361 DRM_DEBUG_DRIVER("Enabling the TV Output\n");
0362
0363 sunxi_engine_apply_color_correction(crtc->engine);
0364
0365 regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
0366 SUN4I_TVE_EN_ENABLE,
0367 SUN4I_TVE_EN_ENABLE);
0368 }
0369
0370 static void sun4i_tv_mode_set(struct drm_encoder *encoder,
0371 struct drm_display_mode *mode,
0372 struct drm_display_mode *adjusted_mode)
0373 {
0374 struct sun4i_tv *tv = drm_encoder_to_sun4i_tv(encoder);
0375 const struct tv_mode *tv_mode = sun4i_tv_find_tv_by_mode(mode);
0376
0377
0378 regmap_update_bits(tv->regs, SUN4I_TVE_EN_REG,
0379 SUN4I_TVE_EN_DAC_MAP_MASK,
0380 SUN4I_TVE_EN_DAC_MAP(0, 1) |
0381 SUN4I_TVE_EN_DAC_MAP(1, 2) |
0382 SUN4I_TVE_EN_DAC_MAP(2, 3) |
0383 SUN4I_TVE_EN_DAC_MAP(3, 4));
0384
0385
0386 regmap_write(tv->regs, SUN4I_TVE_CFG0_REG,
0387 tv_mode->mode |
0388 (tv_mode->yc_en ? SUN4I_TVE_CFG0_YC_EN : 0) |
0389 SUN4I_TVE_CFG0_COMP_EN |
0390 SUN4I_TVE_CFG0_DAC_CONTROL_54M |
0391 SUN4I_TVE_CFG0_CORE_DATAPATH_54M |
0392 SUN4I_TVE_CFG0_CORE_CONTROL_54M);
0393
0394
0395 regmap_write(tv->regs, SUN4I_TVE_DAC0_REG,
0396 SUN4I_TVE_DAC0_DAC_EN(0) |
0397 (tv_mode->dac3_en ? SUN4I_TVE_DAC0_DAC_EN(3) : 0) |
0398 SUN4I_TVE_DAC0_INTERNAL_DAC_37_5_OHMS |
0399 SUN4I_TVE_DAC0_CHROMA_0_75 |
0400 SUN4I_TVE_DAC0_LUMA_0_4 |
0401 SUN4I_TVE_DAC0_CLOCK_INVERT |
0402 (tv_mode->dac_bit25_en ? BIT(25) : 0) |
0403 BIT(30));
0404
0405
0406 regmap_write(tv->regs, SUN4I_TVE_NOTCH_REG,
0407 SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(1, 0) |
0408 SUN4I_TVE_NOTCH_DAC0_TO_DAC_DLY(2, 0));
0409
0410 regmap_write(tv->regs, SUN4I_TVE_CHROMA_FREQ_REG,
0411 tv_mode->chroma_freq);
0412
0413
0414 regmap_write(tv->regs, SUN4I_TVE_PORCH_REG,
0415 SUN4I_TVE_PORCH_BACK(tv_mode->back_porch) |
0416 SUN4I_TVE_PORCH_FRONT(tv_mode->front_porch));
0417
0418
0419 regmap_write(tv->regs, SUN4I_TVE_LINE_REG,
0420 SUN4I_TVE_LINE_FIRST(22) |
0421 SUN4I_TVE_LINE_NUMBER(tv_mode->line_number));
0422
0423 regmap_write(tv->regs, SUN4I_TVE_LEVEL_REG,
0424 SUN4I_TVE_LEVEL_BLANK(tv_mode->video_levels->blank) |
0425 SUN4I_TVE_LEVEL_BLACK(tv_mode->video_levels->black));
0426
0427 regmap_write(tv->regs, SUN4I_TVE_DAC1_REG,
0428 SUN4I_TVE_DAC1_AMPLITUDE(0, 0x18) |
0429 SUN4I_TVE_DAC1_AMPLITUDE(1, 0x18) |
0430 SUN4I_TVE_DAC1_AMPLITUDE(2, 0x18) |
0431 SUN4I_TVE_DAC1_AMPLITUDE(3, 0x18));
0432
0433 regmap_write(tv->regs, SUN4I_TVE_CB_CR_LVL_REG,
0434 SUN4I_TVE_CB_CR_LVL_CB_BURST(tv_mode->burst_levels->cb) |
0435 SUN4I_TVE_CB_CR_LVL_CR_BURST(tv_mode->burst_levels->cr));
0436
0437
0438 regmap_write(tv->regs, SUN4I_TVE_BURST_WIDTH_REG,
0439 SUN4I_TVE_BURST_WIDTH_HSYNC_WIDTH(126) |
0440 SUN4I_TVE_BURST_WIDTH_BURST_WIDTH(68) |
0441 SUN4I_TVE_BURST_WIDTH_BREEZEWAY(22));
0442
0443 regmap_write(tv->regs, SUN4I_TVE_CB_CR_GAIN_REG,
0444 SUN4I_TVE_CB_CR_GAIN_CB(tv_mode->color_gains->cb) |
0445 SUN4I_TVE_CB_CR_GAIN_CR(tv_mode->color_gains->cr));
0446
0447 regmap_write(tv->regs, SUN4I_TVE_SYNC_VBI_REG,
0448 SUN4I_TVE_SYNC_VBI_SYNC(0x10) |
0449 SUN4I_TVE_SYNC_VBI_VBLANK(tv_mode->vblank_level));
0450
0451 regmap_write(tv->regs, SUN4I_TVE_ACTIVE_LINE_REG,
0452 SUN4I_TVE_ACTIVE_LINE(1440));
0453
0454
0455 regmap_write(tv->regs, SUN4I_TVE_CHROMA_REG,
0456 SUN4I_TVE_CHROMA_COMP_GAIN_50);
0457
0458 regmap_write(tv->regs, SUN4I_TVE_12C_REG,
0459 SUN4I_TVE_12C_COMP_YUV_EN |
0460 SUN4I_TVE_12C_NOTCH_WIDTH_WIDE);
0461
0462 regmap_write(tv->regs, SUN4I_TVE_RESYNC_REG,
0463 SUN4I_TVE_RESYNC_PIXEL(tv_mode->resync_params->pixel) |
0464 SUN4I_TVE_RESYNC_LINE(tv_mode->resync_params->line) |
0465 (tv_mode->resync_params->field ?
0466 SUN4I_TVE_RESYNC_FIELD : 0));
0467
0468 regmap_write(tv->regs, SUN4I_TVE_SLAVE_REG, 0);
0469 }
0470
0471 static const struct drm_encoder_helper_funcs sun4i_tv_helper_funcs = {
0472 .disable = sun4i_tv_disable,
0473 .enable = sun4i_tv_enable,
0474 .mode_set = sun4i_tv_mode_set,
0475 };
0476
0477 static int sun4i_tv_comp_get_modes(struct drm_connector *connector)
0478 {
0479 int i;
0480
0481 for (i = 0; i < ARRAY_SIZE(tv_modes); i++) {
0482 struct drm_display_mode *mode;
0483 const struct tv_mode *tv_mode = &tv_modes[i];
0484
0485 mode = drm_mode_create(connector->dev);
0486 if (!mode) {
0487 DRM_ERROR("Failed to create a new display mode\n");
0488 return 0;
0489 }
0490
0491 strcpy(mode->name, tv_mode->name);
0492
0493 sun4i_tv_mode_to_drm_mode(tv_mode, mode);
0494 drm_mode_probed_add(connector, mode);
0495 }
0496
0497 return i;
0498 }
0499
0500 static int sun4i_tv_comp_mode_valid(struct drm_connector *connector,
0501 struct drm_display_mode *mode)
0502 {
0503
0504 return MODE_OK;
0505 }
0506
0507 static const struct drm_connector_helper_funcs sun4i_tv_comp_connector_helper_funcs = {
0508 .get_modes = sun4i_tv_comp_get_modes,
0509 .mode_valid = sun4i_tv_comp_mode_valid,
0510 };
0511
0512 static void
0513 sun4i_tv_comp_connector_destroy(struct drm_connector *connector)
0514 {
0515 drm_connector_cleanup(connector);
0516 }
0517
0518 static const struct drm_connector_funcs sun4i_tv_comp_connector_funcs = {
0519 .fill_modes = drm_helper_probe_single_connector_modes,
0520 .destroy = sun4i_tv_comp_connector_destroy,
0521 .reset = drm_atomic_helper_connector_reset,
0522 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
0523 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
0524 };
0525
0526 static const struct regmap_config sun4i_tv_regmap_config = {
0527 .reg_bits = 32,
0528 .val_bits = 32,
0529 .reg_stride = 4,
0530 .max_register = SUN4I_TVE_WSS_DATA2_REG,
0531 .name = "tv-encoder",
0532 };
0533
0534 static int sun4i_tv_bind(struct device *dev, struct device *master,
0535 void *data)
0536 {
0537 struct platform_device *pdev = to_platform_device(dev);
0538 struct drm_device *drm = data;
0539 struct sun4i_drv *drv = drm->dev_private;
0540 struct sun4i_tv *tv;
0541 void __iomem *regs;
0542 int ret;
0543
0544 tv = devm_kzalloc(dev, sizeof(*tv), GFP_KERNEL);
0545 if (!tv)
0546 return -ENOMEM;
0547 tv->drv = drv;
0548 dev_set_drvdata(dev, tv);
0549
0550 regs = devm_platform_ioremap_resource(pdev, 0);
0551 if (IS_ERR(regs)) {
0552 dev_err(dev, "Couldn't map the TV encoder registers\n");
0553 return PTR_ERR(regs);
0554 }
0555
0556 tv->regs = devm_regmap_init_mmio(dev, regs,
0557 &sun4i_tv_regmap_config);
0558 if (IS_ERR(tv->regs)) {
0559 dev_err(dev, "Couldn't create the TV encoder regmap\n");
0560 return PTR_ERR(tv->regs);
0561 }
0562
0563 tv->reset = devm_reset_control_get(dev, NULL);
0564 if (IS_ERR(tv->reset)) {
0565 dev_err(dev, "Couldn't get our reset line\n");
0566 return PTR_ERR(tv->reset);
0567 }
0568
0569 ret = reset_control_deassert(tv->reset);
0570 if (ret) {
0571 dev_err(dev, "Couldn't deassert our reset line\n");
0572 return ret;
0573 }
0574
0575 tv->clk = devm_clk_get(dev, NULL);
0576 if (IS_ERR(tv->clk)) {
0577 dev_err(dev, "Couldn't get the TV encoder clock\n");
0578 ret = PTR_ERR(tv->clk);
0579 goto err_assert_reset;
0580 }
0581 clk_prepare_enable(tv->clk);
0582
0583 drm_encoder_helper_add(&tv->encoder,
0584 &sun4i_tv_helper_funcs);
0585 ret = drm_simple_encoder_init(drm, &tv->encoder,
0586 DRM_MODE_ENCODER_TVDAC);
0587 if (ret) {
0588 dev_err(dev, "Couldn't initialise the TV encoder\n");
0589 goto err_disable_clk;
0590 }
0591
0592 tv->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
0593 dev->of_node);
0594 if (!tv->encoder.possible_crtcs) {
0595 ret = -EPROBE_DEFER;
0596 goto err_disable_clk;
0597 }
0598
0599 drm_connector_helper_add(&tv->connector,
0600 &sun4i_tv_comp_connector_helper_funcs);
0601 ret = drm_connector_init(drm, &tv->connector,
0602 &sun4i_tv_comp_connector_funcs,
0603 DRM_MODE_CONNECTOR_Composite);
0604 if (ret) {
0605 dev_err(dev,
0606 "Couldn't initialise the Composite connector\n");
0607 goto err_cleanup_connector;
0608 }
0609 tv->connector.interlace_allowed = true;
0610
0611 drm_connector_attach_encoder(&tv->connector, &tv->encoder);
0612
0613 return 0;
0614
0615 err_cleanup_connector:
0616 drm_encoder_cleanup(&tv->encoder);
0617 err_disable_clk:
0618 clk_disable_unprepare(tv->clk);
0619 err_assert_reset:
0620 reset_control_assert(tv->reset);
0621 return ret;
0622 }
0623
0624 static void sun4i_tv_unbind(struct device *dev, struct device *master,
0625 void *data)
0626 {
0627 struct sun4i_tv *tv = dev_get_drvdata(dev);
0628
0629 drm_connector_cleanup(&tv->connector);
0630 drm_encoder_cleanup(&tv->encoder);
0631 clk_disable_unprepare(tv->clk);
0632 }
0633
0634 static const struct component_ops sun4i_tv_ops = {
0635 .bind = sun4i_tv_bind,
0636 .unbind = sun4i_tv_unbind,
0637 };
0638
0639 static int sun4i_tv_probe(struct platform_device *pdev)
0640 {
0641 return component_add(&pdev->dev, &sun4i_tv_ops);
0642 }
0643
0644 static int sun4i_tv_remove(struct platform_device *pdev)
0645 {
0646 component_del(&pdev->dev, &sun4i_tv_ops);
0647
0648 return 0;
0649 }
0650
0651 static const struct of_device_id sun4i_tv_of_table[] = {
0652 { .compatible = "allwinner,sun4i-a10-tv-encoder" },
0653 { }
0654 };
0655 MODULE_DEVICE_TABLE(of, sun4i_tv_of_table);
0656
0657 static struct platform_driver sun4i_tv_platform_driver = {
0658 .probe = sun4i_tv_probe,
0659 .remove = sun4i_tv_remove,
0660 .driver = {
0661 .name = "sun4i-tve",
0662 .of_match_table = sun4i_tv_of_table,
0663 },
0664 };
0665 module_platform_driver(sun4i_tv_platform_driver);
0666
0667 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
0668 MODULE_DESCRIPTION("Allwinner A10 TV Encoder Driver");
0669 MODULE_LICENSE("GPL");
