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0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2016 Maxime Ripard
0004  *
0005  * Maxime Ripard <maxime.ripard@free-electrons.com>
0006  */
0007 
0008 #include <linux/clk.h>
0009 #include <linux/component.h>
0010 #include <linux/i2c.h>
0011 #include <linux/iopoll.h>
0012 #include <linux/module.h>
0013 #include <linux/of_device.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/pm_runtime.h>
0016 #include <linux/regmap.h>
0017 #include <linux/reset.h>
0018 
0019 #include <drm/drm_atomic_helper.h>
0020 #include <drm/drm_edid.h>
0021 #include <drm/drm_encoder.h>
0022 #include <drm/drm_of.h>
0023 #include <drm/drm_panel.h>
0024 #include <drm/drm_print.h>
0025 #include <drm/drm_probe_helper.h>
0026 #include <drm/drm_simple_kms_helper.h>
0027 
0028 #include "sun4i_backend.h"
0029 #include "sun4i_crtc.h"
0030 #include "sun4i_drv.h"
0031 #include "sun4i_hdmi.h"
0032 
0033 static inline struct sun4i_hdmi *
0034 drm_encoder_to_sun4i_hdmi(struct drm_encoder *encoder)
0035 {
0036     return container_of(encoder, struct sun4i_hdmi,
0037                 encoder);
0038 }
0039 
0040 static inline struct sun4i_hdmi *
0041 drm_connector_to_sun4i_hdmi(struct drm_connector *connector)
0042 {
0043     return container_of(connector, struct sun4i_hdmi,
0044                 connector);
0045 }
0046 
0047 static int sun4i_hdmi_setup_avi_infoframes(struct sun4i_hdmi *hdmi,
0048                        struct drm_display_mode *mode)
0049 {
0050     struct hdmi_avi_infoframe frame;
0051     u8 buffer[17];
0052     int i, ret;
0053 
0054     ret = drm_hdmi_avi_infoframe_from_display_mode(&frame,
0055                                &hdmi->connector, mode);
0056     if (ret < 0) {
0057         DRM_ERROR("Failed to get infoframes from mode\n");
0058         return ret;
0059     }
0060 
0061     ret = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
0062     if (ret < 0) {
0063         DRM_ERROR("Failed to pack infoframes\n");
0064         return ret;
0065     }
0066 
0067     for (i = 0; i < sizeof(buffer); i++)
0068         writeb(buffer[i], hdmi->base + SUN4I_HDMI_AVI_INFOFRAME_REG(i));
0069 
0070     return 0;
0071 }
0072 
0073 static int sun4i_hdmi_atomic_check(struct drm_encoder *encoder,
0074                    struct drm_crtc_state *crtc_state,
0075                    struct drm_connector_state *conn_state)
0076 {
0077     struct drm_display_mode *mode = &crtc_state->mode;
0078 
0079     if (mode->flags & DRM_MODE_FLAG_DBLCLK)
0080         return -EINVAL;
0081 
0082     return 0;
0083 }
0084 
0085 static void sun4i_hdmi_disable(struct drm_encoder *encoder)
0086 {
0087     struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
0088     u32 val;
0089 
0090     DRM_DEBUG_DRIVER("Disabling the HDMI Output\n");
0091 
0092     val = readl(hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
0093     val &= ~SUN4I_HDMI_VID_CTRL_ENABLE;
0094     writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
0095 
0096     clk_disable_unprepare(hdmi->tmds_clk);
0097 }
0098 
0099 static void sun4i_hdmi_enable(struct drm_encoder *encoder)
0100 {
0101     struct drm_display_mode *mode = &encoder->crtc->state->adjusted_mode;
0102     struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
0103     struct drm_display_info *display = &hdmi->connector.display_info;
0104     u32 val = 0;
0105 
0106     DRM_DEBUG_DRIVER("Enabling the HDMI Output\n");
0107 
0108     clk_prepare_enable(hdmi->tmds_clk);
0109 
0110     sun4i_hdmi_setup_avi_infoframes(hdmi, mode);
0111     val |= SUN4I_HDMI_PKT_CTRL_TYPE(0, SUN4I_HDMI_PKT_AVI);
0112     val |= SUN4I_HDMI_PKT_CTRL_TYPE(1, SUN4I_HDMI_PKT_END);
0113     writel(val, hdmi->base + SUN4I_HDMI_PKT_CTRL_REG(0));
0114 
0115     val = SUN4I_HDMI_VID_CTRL_ENABLE;
0116     if (display->is_hdmi)
0117         val |= SUN4I_HDMI_VID_CTRL_HDMI_MODE;
0118 
0119     writel(val, hdmi->base + SUN4I_HDMI_VID_CTRL_REG);
0120 }
0121 
0122 static void sun4i_hdmi_mode_set(struct drm_encoder *encoder,
0123                 struct drm_display_mode *mode,
0124                 struct drm_display_mode *adjusted_mode)
0125 {
0126     struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
0127     unsigned int x, y;
0128     u32 val;
0129 
0130     clk_set_rate(hdmi->mod_clk, mode->crtc_clock * 1000);
0131     clk_set_rate(hdmi->tmds_clk, mode->crtc_clock * 1000);
0132 
0133     /* Set input sync enable */
0134     writel(SUN4I_HDMI_UNKNOWN_INPUT_SYNC,
0135            hdmi->base + SUN4I_HDMI_UNKNOWN_REG);
0136 
0137     /*
0138      * Setup output pad (?) controls
0139      *
0140      * This is done here instead of at probe/bind time because
0141      * the controller seems to toggle some of the bits on its own.
0142      *
0143      * We can't just initialize the register there, we need to
0144      * protect the clock bits that have already been read out and
0145      * cached by the clock framework.
0146      */
0147     val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
0148     val &= SUN4I_HDMI_PAD_CTRL1_HALVE_CLK;
0149     val |= hdmi->variant->pad_ctrl1_init_val;
0150     writel(val, hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
0151     val = readl(hdmi->base + SUN4I_HDMI_PAD_CTRL1_REG);
0152 
0153     /* Setup timing registers */
0154     writel(SUN4I_HDMI_VID_TIMING_X(mode->hdisplay) |
0155            SUN4I_HDMI_VID_TIMING_Y(mode->vdisplay),
0156            hdmi->base + SUN4I_HDMI_VID_TIMING_ACT_REG);
0157 
0158     x = mode->htotal - mode->hsync_start;
0159     y = mode->vtotal - mode->vsync_start;
0160     writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
0161            hdmi->base + SUN4I_HDMI_VID_TIMING_BP_REG);
0162 
0163     x = mode->hsync_start - mode->hdisplay;
0164     y = mode->vsync_start - mode->vdisplay;
0165     writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
0166            hdmi->base + SUN4I_HDMI_VID_TIMING_FP_REG);
0167 
0168     x = mode->hsync_end - mode->hsync_start;
0169     y = mode->vsync_end - mode->vsync_start;
0170     writel(SUN4I_HDMI_VID_TIMING_X(x) | SUN4I_HDMI_VID_TIMING_Y(y),
0171            hdmi->base + SUN4I_HDMI_VID_TIMING_SPW_REG);
0172 
0173     val = SUN4I_HDMI_VID_TIMING_POL_TX_CLK;
0174     if (mode->flags & DRM_MODE_FLAG_PHSYNC)
0175         val |= SUN4I_HDMI_VID_TIMING_POL_HSYNC;
0176 
0177     if (mode->flags & DRM_MODE_FLAG_PVSYNC)
0178         val |= SUN4I_HDMI_VID_TIMING_POL_VSYNC;
0179 
0180     writel(val, hdmi->base + SUN4I_HDMI_VID_TIMING_POL_REG);
0181 }
0182 
0183 static enum drm_mode_status sun4i_hdmi_mode_valid(struct drm_encoder *encoder,
0184                     const struct drm_display_mode *mode)
0185 {
0186     struct sun4i_hdmi *hdmi = drm_encoder_to_sun4i_hdmi(encoder);
0187     unsigned long rate = mode->clock * 1000;
0188     unsigned long diff = rate / 200; /* +-0.5% allowed by HDMI spec */
0189     long rounded_rate;
0190 
0191     /* 165 MHz is the typical max pixelclock frequency for HDMI <= 1.2 */
0192     if (rate > 165000000)
0193         return MODE_CLOCK_HIGH;
0194     rounded_rate = clk_round_rate(hdmi->tmds_clk, rate);
0195     if (rounded_rate > 0 &&
0196         max_t(unsigned long, rounded_rate, rate) -
0197         min_t(unsigned long, rounded_rate, rate) < diff)
0198         return MODE_OK;
0199     return MODE_NOCLOCK;
0200 }
0201 
0202 static const struct drm_encoder_helper_funcs sun4i_hdmi_helper_funcs = {
0203     .atomic_check   = sun4i_hdmi_atomic_check,
0204     .disable    = sun4i_hdmi_disable,
0205     .enable     = sun4i_hdmi_enable,
0206     .mode_set   = sun4i_hdmi_mode_set,
0207     .mode_valid = sun4i_hdmi_mode_valid,
0208 };
0209 
0210 static int sun4i_hdmi_get_modes(struct drm_connector *connector)
0211 {
0212     struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
0213     struct edid *edid;
0214     int ret;
0215 
0216     edid = drm_get_edid(connector, hdmi->ddc_i2c ?: hdmi->i2c);
0217     if (!edid)
0218         return 0;
0219 
0220     DRM_DEBUG_DRIVER("Monitor is %s monitor\n",
0221              connector->display_info.is_hdmi ? "an HDMI" : "a DVI");
0222 
0223     drm_connector_update_edid_property(connector, edid);
0224     cec_s_phys_addr_from_edid(hdmi->cec_adap, edid);
0225     ret = drm_add_edid_modes(connector, edid);
0226     kfree(edid);
0227 
0228     return ret;
0229 }
0230 
0231 static struct i2c_adapter *sun4i_hdmi_get_ddc(struct device *dev)
0232 {
0233     struct device_node *phandle, *remote;
0234     struct i2c_adapter *ddc;
0235 
0236     remote = of_graph_get_remote_node(dev->of_node, 1, -1);
0237     if (!remote)
0238         return ERR_PTR(-EINVAL);
0239 
0240     phandle = of_parse_phandle(remote, "ddc-i2c-bus", 0);
0241     of_node_put(remote);
0242     if (!phandle)
0243         return ERR_PTR(-ENODEV);
0244 
0245     ddc = of_get_i2c_adapter_by_node(phandle);
0246     of_node_put(phandle);
0247     if (!ddc)
0248         return ERR_PTR(-EPROBE_DEFER);
0249 
0250     return ddc;
0251 }
0252 
0253 static const struct drm_connector_helper_funcs sun4i_hdmi_connector_helper_funcs = {
0254     .get_modes  = sun4i_hdmi_get_modes,
0255 };
0256 
0257 static enum drm_connector_status
0258 sun4i_hdmi_connector_detect(struct drm_connector *connector, bool force)
0259 {
0260     struct sun4i_hdmi *hdmi = drm_connector_to_sun4i_hdmi(connector);
0261     unsigned long reg;
0262 
0263     reg = readl(hdmi->base + SUN4I_HDMI_HPD_REG);
0264     if (!(reg & SUN4I_HDMI_HPD_HIGH)) {
0265         cec_phys_addr_invalidate(hdmi->cec_adap);
0266         return connector_status_disconnected;
0267     }
0268 
0269     return connector_status_connected;
0270 }
0271 
0272 static const struct drm_connector_funcs sun4i_hdmi_connector_funcs = {
0273     .detect         = sun4i_hdmi_connector_detect,
0274     .fill_modes     = drm_helper_probe_single_connector_modes,
0275     .destroy        = drm_connector_cleanup,
0276     .reset          = drm_atomic_helper_connector_reset,
0277     .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
0278     .atomic_destroy_state   = drm_atomic_helper_connector_destroy_state,
0279 };
0280 
0281 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC
0282 static int sun4i_hdmi_cec_pin_read(struct cec_adapter *adap)
0283 {
0284     struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
0285 
0286     return readl(hdmi->base + SUN4I_HDMI_CEC) & SUN4I_HDMI_CEC_RX;
0287 }
0288 
0289 static void sun4i_hdmi_cec_pin_low(struct cec_adapter *adap)
0290 {
0291     struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
0292 
0293     /* Start driving the CEC pin low */
0294     writel(SUN4I_HDMI_CEC_ENABLE, hdmi->base + SUN4I_HDMI_CEC);
0295 }
0296 
0297 static void sun4i_hdmi_cec_pin_high(struct cec_adapter *adap)
0298 {
0299     struct sun4i_hdmi *hdmi = cec_get_drvdata(adap);
0300 
0301     /*
0302      * Stop driving the CEC pin, the pull up will take over
0303      * unless another CEC device is driving the pin low.
0304      */
0305     writel(0, hdmi->base + SUN4I_HDMI_CEC);
0306 }
0307 
0308 static const struct cec_pin_ops sun4i_hdmi_cec_pin_ops = {
0309     .read = sun4i_hdmi_cec_pin_read,
0310     .low = sun4i_hdmi_cec_pin_low,
0311     .high = sun4i_hdmi_cec_pin_high,
0312 };
0313 #endif
0314 
0315 #define SUN4I_HDMI_PAD_CTRL1_MASK   (GENMASK(24, 7) | GENMASK(5, 0))
0316 #define SUN4I_HDMI_PLL_CTRL_MASK    (GENMASK(31, 8) | GENMASK(3, 0))
0317 
0318 /* Only difference from sun5i is AMP is 4 instead of 6 */
0319 static const struct sun4i_hdmi_variant sun4i_variant = {
0320     .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN |
0321                   SUN4I_HDMI_PAD_CTRL0_CKEN |
0322                   SUN4I_HDMI_PAD_CTRL0_PWENG |
0323                   SUN4I_HDMI_PAD_CTRL0_PWEND |
0324                   SUN4I_HDMI_PAD_CTRL0_PWENC |
0325                   SUN4I_HDMI_PAD_CTRL0_LDODEN |
0326                   SUN4I_HDMI_PAD_CTRL0_LDOCEN |
0327                   SUN4I_HDMI_PAD_CTRL0_BIASEN,
0328     .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(4) |
0329                   SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
0330                   SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
0331                   SUN4I_HDMI_PAD_CTRL1_REG_DEN |
0332                   SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
0333                   SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
0334                   SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
0335                   SUN4I_HDMI_PAD_CTRL1_AMP_OPT,
0336     .pll_ctrl_init_val  = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
0337                   SUN4I_HDMI_PLL_CTRL_CS(7) |
0338                   SUN4I_HDMI_PLL_CTRL_CP_S(15) |
0339                   SUN4I_HDMI_PLL_CTRL_S(7) |
0340                   SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
0341                   SUN4I_HDMI_PLL_CTRL_SDIV2 |
0342                   SUN4I_HDMI_PLL_CTRL_LDO2_EN |
0343                   SUN4I_HDMI_PLL_CTRL_LDO1_EN |
0344                   SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
0345                   SUN4I_HDMI_PLL_CTRL_BWS |
0346                   SUN4I_HDMI_PLL_CTRL_PLL_EN,
0347 
0348     .ddc_clk_reg        = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6),
0349     .ddc_clk_pre_divider    = 2,
0350     .ddc_clk_m_offset   = 1,
0351 
0352     .field_ddc_en       = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31),
0353     .field_ddc_start    = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30),
0354     .field_ddc_reset    = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0),
0355     .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31),
0356     .field_ddc_slave_addr   = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6),
0357     .field_ddc_int_status   = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8),
0358     .field_ddc_fifo_clear   = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31),
0359     .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
0360     .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
0361     .field_ddc_byte_count   = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9),
0362     .field_ddc_cmd      = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2),
0363     .field_ddc_sda_en   = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9),
0364     .field_ddc_sck_en   = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8),
0365 
0366     .ddc_fifo_reg       = SUN4I_HDMI_DDC_FIFO_DATA_REG,
0367     .ddc_fifo_has_dir   = true,
0368 };
0369 
0370 static const struct sun4i_hdmi_variant sun5i_variant = {
0371     .pad_ctrl0_init_val = SUN4I_HDMI_PAD_CTRL0_TXEN |
0372                   SUN4I_HDMI_PAD_CTRL0_CKEN |
0373                   SUN4I_HDMI_PAD_CTRL0_PWENG |
0374                   SUN4I_HDMI_PAD_CTRL0_PWEND |
0375                   SUN4I_HDMI_PAD_CTRL0_PWENC |
0376                   SUN4I_HDMI_PAD_CTRL0_LDODEN |
0377                   SUN4I_HDMI_PAD_CTRL0_LDOCEN |
0378                   SUN4I_HDMI_PAD_CTRL0_BIASEN,
0379     .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
0380                   SUN4I_HDMI_PAD_CTRL1_REG_EMP(2) |
0381                   SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
0382                   SUN4I_HDMI_PAD_CTRL1_REG_DEN |
0383                   SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
0384                   SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
0385                   SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
0386                   SUN4I_HDMI_PAD_CTRL1_AMP_OPT,
0387     .pll_ctrl_init_val  = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
0388                   SUN4I_HDMI_PLL_CTRL_CS(7) |
0389                   SUN4I_HDMI_PLL_CTRL_CP_S(15) |
0390                   SUN4I_HDMI_PLL_CTRL_S(7) |
0391                   SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
0392                   SUN4I_HDMI_PLL_CTRL_SDIV2 |
0393                   SUN4I_HDMI_PLL_CTRL_LDO2_EN |
0394                   SUN4I_HDMI_PLL_CTRL_LDO1_EN |
0395                   SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
0396                   SUN4I_HDMI_PLL_CTRL_BWS |
0397                   SUN4I_HDMI_PLL_CTRL_PLL_EN,
0398 
0399     .ddc_clk_reg        = REG_FIELD(SUN4I_HDMI_DDC_CLK_REG, 0, 6),
0400     .ddc_clk_pre_divider    = 2,
0401     .ddc_clk_m_offset   = 1,
0402 
0403     .field_ddc_en       = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 31, 31),
0404     .field_ddc_start    = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 30, 30),
0405     .field_ddc_reset    = REG_FIELD(SUN4I_HDMI_DDC_CTRL_REG, 0, 0),
0406     .field_ddc_addr_reg = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 31),
0407     .field_ddc_slave_addr   = REG_FIELD(SUN4I_HDMI_DDC_ADDR_REG, 0, 6),
0408     .field_ddc_int_status   = REG_FIELD(SUN4I_HDMI_DDC_INT_STATUS_REG, 0, 8),
0409     .field_ddc_fifo_clear   = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 31, 31),
0410     .field_ddc_fifo_rx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
0411     .field_ddc_fifo_tx_thres = REG_FIELD(SUN4I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
0412     .field_ddc_byte_count   = REG_FIELD(SUN4I_HDMI_DDC_BYTE_COUNT_REG, 0, 9),
0413     .field_ddc_cmd      = REG_FIELD(SUN4I_HDMI_DDC_CMD_REG, 0, 2),
0414     .field_ddc_sda_en   = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 9, 9),
0415     .field_ddc_sck_en   = REG_FIELD(SUN4I_HDMI_DDC_LINE_CTRL_REG, 8, 8),
0416 
0417     .ddc_fifo_reg       = SUN4I_HDMI_DDC_FIFO_DATA_REG,
0418     .ddc_fifo_has_dir   = true,
0419 };
0420 
0421 static const struct sun4i_hdmi_variant sun6i_variant = {
0422     .has_ddc_parent_clk = true,
0423     .has_reset_control  = true,
0424     .pad_ctrl0_init_val = 0xff |
0425                   SUN4I_HDMI_PAD_CTRL0_TXEN |
0426                   SUN4I_HDMI_PAD_CTRL0_CKEN |
0427                   SUN4I_HDMI_PAD_CTRL0_PWENG |
0428                   SUN4I_HDMI_PAD_CTRL0_PWEND |
0429                   SUN4I_HDMI_PAD_CTRL0_PWENC |
0430                   SUN4I_HDMI_PAD_CTRL0_LDODEN |
0431                   SUN4I_HDMI_PAD_CTRL0_LDOCEN,
0432     .pad_ctrl1_init_val = SUN4I_HDMI_PAD_CTRL1_REG_AMP(6) |
0433                   SUN4I_HDMI_PAD_CTRL1_REG_EMP(4) |
0434                   SUN4I_HDMI_PAD_CTRL1_REG_DENCK |
0435                   SUN4I_HDMI_PAD_CTRL1_REG_DEN |
0436                   SUN4I_HDMI_PAD_CTRL1_EMPCK_OPT |
0437                   SUN4I_HDMI_PAD_CTRL1_EMP_OPT |
0438                   SUN4I_HDMI_PAD_CTRL1_PWSDT |
0439                   SUN4I_HDMI_PAD_CTRL1_PWSCK |
0440                   SUN4I_HDMI_PAD_CTRL1_AMPCK_OPT |
0441                   SUN4I_HDMI_PAD_CTRL1_AMP_OPT |
0442                   SUN4I_HDMI_PAD_CTRL1_UNKNOWN,
0443     .pll_ctrl_init_val  = SUN4I_HDMI_PLL_CTRL_VCO_S(8) |
0444                   SUN4I_HDMI_PLL_CTRL_CS(3) |
0445                   SUN4I_HDMI_PLL_CTRL_CP_S(10) |
0446                   SUN4I_HDMI_PLL_CTRL_S(4) |
0447                   SUN4I_HDMI_PLL_CTRL_VCO_GAIN(4) |
0448                   SUN4I_HDMI_PLL_CTRL_SDIV2 |
0449                   SUN4I_HDMI_PLL_CTRL_LDO2_EN |
0450                   SUN4I_HDMI_PLL_CTRL_LDO1_EN |
0451                   SUN4I_HDMI_PLL_CTRL_HV_IS_33 |
0452                   SUN4I_HDMI_PLL_CTRL_PLL_EN,
0453 
0454     .ddc_clk_reg        = REG_FIELD(SUN6I_HDMI_DDC_CLK_REG, 0, 6),
0455     .ddc_clk_pre_divider    = 1,
0456     .ddc_clk_m_offset   = 2,
0457 
0458     .tmds_clk_div_offset    = 1,
0459 
0460     .field_ddc_en       = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 0, 0),
0461     .field_ddc_start    = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 27, 27),
0462     .field_ddc_reset    = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 31, 31),
0463     .field_ddc_addr_reg = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 31),
0464     .field_ddc_slave_addr   = REG_FIELD(SUN6I_HDMI_DDC_ADDR_REG, 1, 7),
0465     .field_ddc_int_status   = REG_FIELD(SUN6I_HDMI_DDC_INT_STATUS_REG, 0, 8),
0466     .field_ddc_fifo_clear   = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 18, 18),
0467     .field_ddc_fifo_rx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 4, 7),
0468     .field_ddc_fifo_tx_thres = REG_FIELD(SUN6I_HDMI_DDC_FIFO_CTRL_REG, 0, 3),
0469     .field_ddc_byte_count   = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 16, 25),
0470     .field_ddc_cmd      = REG_FIELD(SUN6I_HDMI_DDC_CMD_REG, 0, 2),
0471     .field_ddc_sda_en   = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 6, 6),
0472     .field_ddc_sck_en   = REG_FIELD(SUN6I_HDMI_DDC_CTRL_REG, 4, 4),
0473 
0474     .ddc_fifo_reg       = SUN6I_HDMI_DDC_FIFO_DATA_REG,
0475     .ddc_fifo_thres_incl    = true,
0476 };
0477 
0478 static const struct regmap_config sun4i_hdmi_regmap_config = {
0479     .reg_bits   = 32,
0480     .val_bits   = 32,
0481     .reg_stride = 4,
0482     .max_register   = 0x580,
0483 };
0484 
0485 static int sun4i_hdmi_bind(struct device *dev, struct device *master,
0486                void *data)
0487 {
0488     struct platform_device *pdev = to_platform_device(dev);
0489     struct drm_device *drm = data;
0490     struct cec_connector_info conn_info;
0491     struct sun4i_drv *drv = drm->dev_private;
0492     struct sun4i_hdmi *hdmi;
0493     u32 reg;
0494     int ret;
0495 
0496     hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
0497     if (!hdmi)
0498         return -ENOMEM;
0499     dev_set_drvdata(dev, hdmi);
0500     hdmi->dev = dev;
0501     hdmi->drv = drv;
0502 
0503     hdmi->variant = of_device_get_match_data(dev);
0504     if (!hdmi->variant)
0505         return -EINVAL;
0506 
0507     hdmi->base = devm_platform_ioremap_resource(pdev, 0);
0508     if (IS_ERR(hdmi->base)) {
0509         dev_err(dev, "Couldn't map the HDMI encoder registers\n");
0510         return PTR_ERR(hdmi->base);
0511     }
0512 
0513     if (hdmi->variant->has_reset_control) {
0514         hdmi->reset = devm_reset_control_get(dev, NULL);
0515         if (IS_ERR(hdmi->reset)) {
0516             dev_err(dev, "Couldn't get the HDMI reset control\n");
0517             return PTR_ERR(hdmi->reset);
0518         }
0519 
0520         ret = reset_control_deassert(hdmi->reset);
0521         if (ret) {
0522             dev_err(dev, "Couldn't deassert HDMI reset\n");
0523             return ret;
0524         }
0525     }
0526 
0527     hdmi->bus_clk = devm_clk_get(dev, "ahb");
0528     if (IS_ERR(hdmi->bus_clk)) {
0529         dev_err(dev, "Couldn't get the HDMI bus clock\n");
0530         ret = PTR_ERR(hdmi->bus_clk);
0531         goto err_assert_reset;
0532     }
0533     clk_prepare_enable(hdmi->bus_clk);
0534 
0535     hdmi->mod_clk = devm_clk_get(dev, "mod");
0536     if (IS_ERR(hdmi->mod_clk)) {
0537         dev_err(dev, "Couldn't get the HDMI mod clock\n");
0538         ret = PTR_ERR(hdmi->mod_clk);
0539         goto err_disable_bus_clk;
0540     }
0541     clk_prepare_enable(hdmi->mod_clk);
0542 
0543     hdmi->pll0_clk = devm_clk_get(dev, "pll-0");
0544     if (IS_ERR(hdmi->pll0_clk)) {
0545         dev_err(dev, "Couldn't get the HDMI PLL 0 clock\n");
0546         ret = PTR_ERR(hdmi->pll0_clk);
0547         goto err_disable_mod_clk;
0548     }
0549 
0550     hdmi->pll1_clk = devm_clk_get(dev, "pll-1");
0551     if (IS_ERR(hdmi->pll1_clk)) {
0552         dev_err(dev, "Couldn't get the HDMI PLL 1 clock\n");
0553         ret = PTR_ERR(hdmi->pll1_clk);
0554         goto err_disable_mod_clk;
0555     }
0556 
0557     hdmi->regmap = devm_regmap_init_mmio(dev, hdmi->base,
0558                          &sun4i_hdmi_regmap_config);
0559     if (IS_ERR(hdmi->regmap)) {
0560         dev_err(dev, "Couldn't create HDMI encoder regmap\n");
0561         ret = PTR_ERR(hdmi->regmap);
0562         goto err_disable_mod_clk;
0563     }
0564 
0565     ret = sun4i_tmds_create(hdmi);
0566     if (ret) {
0567         dev_err(dev, "Couldn't create the TMDS clock\n");
0568         goto err_disable_mod_clk;
0569     }
0570 
0571     if (hdmi->variant->has_ddc_parent_clk) {
0572         hdmi->ddc_parent_clk = devm_clk_get(dev, "ddc");
0573         if (IS_ERR(hdmi->ddc_parent_clk)) {
0574             dev_err(dev, "Couldn't get the HDMI DDC clock\n");
0575             ret = PTR_ERR(hdmi->ddc_parent_clk);
0576             goto err_disable_mod_clk;
0577         }
0578     } else {
0579         hdmi->ddc_parent_clk = hdmi->tmds_clk;
0580     }
0581 
0582     writel(SUN4I_HDMI_CTRL_ENABLE, hdmi->base + SUN4I_HDMI_CTRL_REG);
0583 
0584     writel(hdmi->variant->pad_ctrl0_init_val,
0585            hdmi->base + SUN4I_HDMI_PAD_CTRL0_REG);
0586 
0587     reg = readl(hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
0588     reg &= SUN4I_HDMI_PLL_CTRL_DIV_MASK;
0589     reg |= hdmi->variant->pll_ctrl_init_val;
0590     writel(reg, hdmi->base + SUN4I_HDMI_PLL_CTRL_REG);
0591 
0592     ret = sun4i_hdmi_i2c_create(dev, hdmi);
0593     if (ret) {
0594         dev_err(dev, "Couldn't create the HDMI I2C adapter\n");
0595         goto err_disable_mod_clk;
0596     }
0597 
0598     hdmi->ddc_i2c = sun4i_hdmi_get_ddc(dev);
0599     if (IS_ERR(hdmi->ddc_i2c)) {
0600         ret = PTR_ERR(hdmi->ddc_i2c);
0601         if (ret == -ENODEV)
0602             hdmi->ddc_i2c = NULL;
0603         else
0604             goto err_del_i2c_adapter;
0605     }
0606 
0607     drm_encoder_helper_add(&hdmi->encoder,
0608                    &sun4i_hdmi_helper_funcs);
0609     ret = drm_simple_encoder_init(drm, &hdmi->encoder,
0610                       DRM_MODE_ENCODER_TMDS);
0611     if (ret) {
0612         dev_err(dev, "Couldn't initialise the HDMI encoder\n");
0613         goto err_put_ddc_i2c;
0614     }
0615 
0616     hdmi->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm,
0617                                   dev->of_node);
0618     if (!hdmi->encoder.possible_crtcs) {
0619         ret = -EPROBE_DEFER;
0620         goto err_put_ddc_i2c;
0621     }
0622 
0623 #ifdef CONFIG_DRM_SUN4I_HDMI_CEC
0624     hdmi->cec_adap = cec_pin_allocate_adapter(&sun4i_hdmi_cec_pin_ops,
0625         hdmi, "sun4i", CEC_CAP_DEFAULTS | CEC_CAP_CONNECTOR_INFO);
0626     ret = PTR_ERR_OR_ZERO(hdmi->cec_adap);
0627     if (ret < 0)
0628         goto err_cleanup_connector;
0629     writel(readl(hdmi->base + SUN4I_HDMI_CEC) & ~SUN4I_HDMI_CEC_TX,
0630            hdmi->base + SUN4I_HDMI_CEC);
0631 #endif
0632 
0633     drm_connector_helper_add(&hdmi->connector,
0634                  &sun4i_hdmi_connector_helper_funcs);
0635     ret = drm_connector_init_with_ddc(drm, &hdmi->connector,
0636                       &sun4i_hdmi_connector_funcs,
0637                       DRM_MODE_CONNECTOR_HDMIA,
0638                       hdmi->ddc_i2c);
0639     if (ret) {
0640         dev_err(dev,
0641             "Couldn't initialise the HDMI connector\n");
0642         goto err_cleanup_connector;
0643     }
0644     cec_fill_conn_info_from_drm(&conn_info, &hdmi->connector);
0645     cec_s_conn_info(hdmi->cec_adap, &conn_info);
0646 
0647     /* There is no HPD interrupt, so we need to poll the controller */
0648     hdmi->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
0649         DRM_CONNECTOR_POLL_DISCONNECT;
0650 
0651     ret = cec_register_adapter(hdmi->cec_adap, dev);
0652     if (ret < 0)
0653         goto err_cleanup_connector;
0654     drm_connector_attach_encoder(&hdmi->connector, &hdmi->encoder);
0655 
0656     return 0;
0657 
0658 err_cleanup_connector:
0659     cec_delete_adapter(hdmi->cec_adap);
0660     drm_encoder_cleanup(&hdmi->encoder);
0661 err_put_ddc_i2c:
0662     i2c_put_adapter(hdmi->ddc_i2c);
0663 err_del_i2c_adapter:
0664     i2c_del_adapter(hdmi->i2c);
0665 err_disable_mod_clk:
0666     clk_disable_unprepare(hdmi->mod_clk);
0667 err_disable_bus_clk:
0668     clk_disable_unprepare(hdmi->bus_clk);
0669 err_assert_reset:
0670     reset_control_assert(hdmi->reset);
0671     return ret;
0672 }
0673 
0674 static void sun4i_hdmi_unbind(struct device *dev, struct device *master,
0675                 void *data)
0676 {
0677     struct sun4i_hdmi *hdmi = dev_get_drvdata(dev);
0678 
0679     cec_unregister_adapter(hdmi->cec_adap);
0680     i2c_del_adapter(hdmi->i2c);
0681     i2c_put_adapter(hdmi->ddc_i2c);
0682     clk_disable_unprepare(hdmi->mod_clk);
0683     clk_disable_unprepare(hdmi->bus_clk);
0684 }
0685 
0686 static const struct component_ops sun4i_hdmi_ops = {
0687     .bind   = sun4i_hdmi_bind,
0688     .unbind = sun4i_hdmi_unbind,
0689 };
0690 
0691 static int sun4i_hdmi_probe(struct platform_device *pdev)
0692 {
0693     return component_add(&pdev->dev, &sun4i_hdmi_ops);
0694 }
0695 
0696 static int sun4i_hdmi_remove(struct platform_device *pdev)
0697 {
0698     component_del(&pdev->dev, &sun4i_hdmi_ops);
0699 
0700     return 0;
0701 }
0702 
0703 static const struct of_device_id sun4i_hdmi_of_table[] = {
0704     { .compatible = "allwinner,sun4i-a10-hdmi", .data = &sun4i_variant, },
0705     { .compatible = "allwinner,sun5i-a10s-hdmi", .data = &sun5i_variant, },
0706     { .compatible = "allwinner,sun6i-a31-hdmi", .data = &sun6i_variant, },
0707     { }
0708 };
0709 MODULE_DEVICE_TABLE(of, sun4i_hdmi_of_table);
0710 
0711 static struct platform_driver sun4i_hdmi_driver = {
0712     .probe      = sun4i_hdmi_probe,
0713     .remove     = sun4i_hdmi_remove,
0714     .driver     = {
0715         .name       = "sun4i-hdmi",
0716         .of_match_table = sun4i_hdmi_of_table,
0717     },
0718 };
0719 module_platform_driver(sun4i_hdmi_driver);
0720 
0721 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
0722 MODULE_DESCRIPTION("Allwinner A10 HDMI Driver");
0723 MODULE_LICENSE("GPL");
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