drm/sun4i/sun4i_hdmi_ddc_clk.c

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2016 Free Electrons
0004  * Copyright (C) 2016 NextThing Co
0005  *
0006  * Maxime Ripard <maxime.ripard@free-electrons.com>
0007  */
0008
0009 #include <linux/clk-provider.h>
0010 #include <linux/regmap.h>
0011
0012 #include "sun4i_hdmi.h"
0013
0014 struct sun4i_ddc {
0015     struct clk_hw       hw;
0016     struct sun4i_hdmi   *hdmi;
0017     struct regmap_field *reg;
0018     u8          pre_div;
0019     u8          m_offset;
0020 };
0021
0022 static inline struct sun4i_ddc *hw_to_ddc(struct clk_hw *hw)
0023 {
0024     return container_of(hw, struct sun4i_ddc, hw);
0025 }
0026
0027 static unsigned long sun4i_ddc_calc_divider(unsigned long rate,
0028                         unsigned long parent_rate,
0029                         const u8 pre_div,
0030                         const u8 m_offset,
0031                         u8 *m, u8 *n)
0032 {
0033     unsigned long best_rate = 0;
0034     u8 best_m = 0, best_n = 0, _m, _n;
0035
0036     for (_m = 0; _m < 16; _m++) {
0037         for (_n = 0; _n < 8; _n++) {
0038             unsigned long tmp_rate;
0039
0040             tmp_rate = (((parent_rate / pre_div) / 10) >> _n) /
0041                 (_m + m_offset);
0042
0043             if (tmp_rate > rate)
0044                 continue;
0045
0046             if (abs(rate - tmp_rate) < abs(rate - best_rate)) {
0047                 best_rate = tmp_rate;
0048                 best_m = _m;
0049                 best_n = _n;
0050             }
0051         }
0052     }
0053
0054     if (m && n) {
0055         *m = best_m;
0056         *n = best_n;
0057     }
0058
0059     return best_rate;
0060 }
0061
0062 static long sun4i_ddc_round_rate(struct clk_hw *hw, unsigned long rate,
0063                  unsigned long *prate)
0064 {
0065     struct sun4i_ddc *ddc = hw_to_ddc(hw);
0066
0067     return sun4i_ddc_calc_divider(rate, *prate, ddc->pre_div,
0068                       ddc->m_offset, NULL, NULL);
0069 }
0070
0071 static unsigned long sun4i_ddc_recalc_rate(struct clk_hw *hw,
0072                         unsigned long parent_rate)
0073 {
0074     struct sun4i_ddc *ddc = hw_to_ddc(hw);
0075     unsigned int reg;
0076     u8 m, n;
0077
0078     regmap_field_read(ddc->reg, &reg);
0079     m = (reg >> 3) & 0xf;
0080     n = reg & 0x7;
0081
0082     return (((parent_rate / ddc->pre_div) / 10) >> n) /
0083            (m + ddc->m_offset);
0084 }
0085
0086 static int sun4i_ddc_set_rate(struct clk_hw *hw, unsigned long rate,
0087                   unsigned long parent_rate)
0088 {
0089     struct sun4i_ddc *ddc = hw_to_ddc(hw);
0090     u8 div_m, div_n;
0091
0092     sun4i_ddc_calc_divider(rate, parent_rate, ddc->pre_div,
0093                    ddc->m_offset, &div_m, &div_n);
0094
0095     regmap_field_write(ddc->reg,
0096                SUN4I_HDMI_DDC_CLK_M(div_m) |
0097                SUN4I_HDMI_DDC_CLK_N(div_n));
0098
0099     return 0;
0100 }
0101
0102 static const struct clk_ops sun4i_ddc_ops = {
0103     .recalc_rate    = sun4i_ddc_recalc_rate,
0104     .round_rate = sun4i_ddc_round_rate,
0105     .set_rate   = sun4i_ddc_set_rate,
0106 };
0107
0108 int sun4i_ddc_create(struct sun4i_hdmi *hdmi, struct clk *parent)
0109 {
0110     struct clk_init_data init;
0111     struct sun4i_ddc *ddc;
0112     const char *parent_name;
0113
0114     parent_name = __clk_get_name(parent);
0115     if (!parent_name)
0116         return -ENODEV;
0117
0118     ddc = devm_kzalloc(hdmi->dev, sizeof(*ddc), GFP_KERNEL);
0119     if (!ddc)
0120         return -ENOMEM;
0121
0122     ddc->reg = devm_regmap_field_alloc(hdmi->dev, hdmi->regmap,
0123                        hdmi->variant->ddc_clk_reg);
0124     if (IS_ERR(ddc->reg))
0125         return PTR_ERR(ddc->reg);
0126
0127     init.name = "hdmi-ddc";
0128     init.ops = &sun4i_ddc_ops;
0129     init.parent_names = &parent_name;
0130     init.num_parents = 1;
0131
0132     ddc->hdmi = hdmi;
0133     ddc->hw.init = &init;
0134     ddc->pre_div = hdmi->variant->ddc_clk_pre_divider;
0135     ddc->m_offset = hdmi->variant->ddc_clk_m_offset;
0136
0137     hdmi->ddc_clk = devm_clk_register(hdmi->dev, &ddc->hw);
0138     if (IS_ERR(hdmi->ddc_clk))
0139         return PTR_ERR(hdmi->ddc_clk);
0140
0141     return 0;
0142 }