Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0-or-later
0002 /*
0003  * Copyright (C) 2015 Free Electrons
0004  * Copyright (C) 2015 NextThing Co
0005  *
0006  * Maxime Ripard <maxime.ripard@free-electrons.com>
0007  */
0008 
0009 #include <linux/component.h>
0010 #include <linux/list.h>
0011 #include <linux/module.h>
0012 #include <linux/of_device.h>
0013 #include <linux/of_graph.h>
0014 #include <linux/dma-mapping.h>
0015 #include <linux/platform_device.h>
0016 #include <linux/reset.h>
0017 
0018 #include <drm/drm_atomic.h>
0019 #include <drm/drm_atomic_helper.h>
0020 #include <drm/drm_blend.h>
0021 #include <drm/drm_crtc.h>
0022 #include <drm/drm_fb_cma_helper.h>
0023 #include <drm/drm_fourcc.h>
0024 #include <drm/drm_framebuffer.h>
0025 #include <drm/drm_gem_cma_helper.h>
0026 #include <drm/drm_plane_helper.h>
0027 #include <drm/drm_probe_helper.h>
0028 
0029 #include "sun4i_backend.h"
0030 #include "sun4i_drv.h"
0031 #include "sun4i_frontend.h"
0032 #include "sun4i_layer.h"
0033 #include "sunxi_engine.h"
0034 
0035 struct sun4i_backend_quirks {
0036     /* backend <-> TCON muxing selection done in backend */
0037     bool needs_output_muxing;
0038 
0039     /* alpha at the lowest z position is not always supported */
0040     bool supports_lowest_plane_alpha;
0041 };
0042 
0043 static const u32 sunxi_rgb2yuv_coef[12] = {
0044     0x00000107, 0x00000204, 0x00000064, 0x00000108,
0045     0x00003f69, 0x00003ed6, 0x000001c1, 0x00000808,
0046     0x000001c1, 0x00003e88, 0x00003fb8, 0x00000808
0047 };
0048 
0049 static void sun4i_backend_apply_color_correction(struct sunxi_engine *engine)
0050 {
0051     int i;
0052 
0053     DRM_DEBUG_DRIVER("Applying RGB to YUV color correction\n");
0054 
0055     /* Set color correction */
0056     regmap_write(engine->regs, SUN4I_BACKEND_OCCTL_REG,
0057              SUN4I_BACKEND_OCCTL_ENABLE);
0058 
0059     for (i = 0; i < 12; i++)
0060         regmap_write(engine->regs, SUN4I_BACKEND_OCRCOEF_REG(i),
0061                  sunxi_rgb2yuv_coef[i]);
0062 }
0063 
0064 static void sun4i_backend_disable_color_correction(struct sunxi_engine *engine)
0065 {
0066     DRM_DEBUG_DRIVER("Disabling color correction\n");
0067 
0068     /* Disable color correction */
0069     regmap_update_bits(engine->regs, SUN4I_BACKEND_OCCTL_REG,
0070                SUN4I_BACKEND_OCCTL_ENABLE, 0);
0071 }
0072 
0073 static void sun4i_backend_commit(struct sunxi_engine *engine)
0074 {
0075     DRM_DEBUG_DRIVER("Committing changes\n");
0076 
0077     regmap_write(engine->regs, SUN4I_BACKEND_REGBUFFCTL_REG,
0078              SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS |
0079              SUN4I_BACKEND_REGBUFFCTL_LOADCTL);
0080 }
0081 
0082 void sun4i_backend_layer_enable(struct sun4i_backend *backend,
0083                 int layer, bool enable)
0084 {
0085     u32 val;
0086 
0087     DRM_DEBUG_DRIVER("%sabling layer %d\n", enable ? "En" : "Dis",
0088              layer);
0089 
0090     if (enable)
0091         val = SUN4I_BACKEND_MODCTL_LAY_EN(layer);
0092     else
0093         val = 0;
0094 
0095     regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
0096                SUN4I_BACKEND_MODCTL_LAY_EN(layer), val);
0097 }
0098 
0099 static int sun4i_backend_drm_format_to_layer(u32 format, u32 *mode)
0100 {
0101     switch (format) {
0102     case DRM_FORMAT_ARGB8888:
0103         *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB8888;
0104         break;
0105 
0106     case DRM_FORMAT_ARGB4444:
0107         *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB4444;
0108         break;
0109 
0110     case DRM_FORMAT_ARGB1555:
0111         *mode = SUN4I_BACKEND_LAY_FBFMT_ARGB1555;
0112         break;
0113 
0114     case DRM_FORMAT_RGBA5551:
0115         *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA5551;
0116         break;
0117 
0118     case DRM_FORMAT_RGBA4444:
0119         *mode = SUN4I_BACKEND_LAY_FBFMT_RGBA4444;
0120         break;
0121 
0122     case DRM_FORMAT_XRGB8888:
0123         *mode = SUN4I_BACKEND_LAY_FBFMT_XRGB8888;
0124         break;
0125 
0126     case DRM_FORMAT_RGB888:
0127         *mode = SUN4I_BACKEND_LAY_FBFMT_RGB888;
0128         break;
0129 
0130     case DRM_FORMAT_RGB565:
0131         *mode = SUN4I_BACKEND_LAY_FBFMT_RGB565;
0132         break;
0133 
0134     default:
0135         return -EINVAL;
0136     }
0137 
0138     return 0;
0139 }
0140 
0141 static const uint32_t sun4i_backend_formats[] = {
0142     DRM_FORMAT_ARGB1555,
0143     DRM_FORMAT_ARGB4444,
0144     DRM_FORMAT_ARGB8888,
0145     DRM_FORMAT_RGB565,
0146     DRM_FORMAT_RGB888,
0147     DRM_FORMAT_RGBA4444,
0148     DRM_FORMAT_RGBA5551,
0149     DRM_FORMAT_UYVY,
0150     DRM_FORMAT_VYUY,
0151     DRM_FORMAT_XRGB8888,
0152     DRM_FORMAT_YUYV,
0153     DRM_FORMAT_YVYU,
0154 };
0155 
0156 bool sun4i_backend_format_is_supported(uint32_t fmt, uint64_t modifier)
0157 {
0158     unsigned int i;
0159 
0160     if (modifier != DRM_FORMAT_MOD_LINEAR)
0161         return false;
0162 
0163     for (i = 0; i < ARRAY_SIZE(sun4i_backend_formats); i++)
0164         if (sun4i_backend_formats[i] == fmt)
0165             return true;
0166 
0167     return false;
0168 }
0169 
0170 int sun4i_backend_update_layer_coord(struct sun4i_backend *backend,
0171                      int layer, struct drm_plane *plane)
0172 {
0173     struct drm_plane_state *state = plane->state;
0174 
0175     DRM_DEBUG_DRIVER("Updating layer %d\n", layer);
0176 
0177     /* Set height and width */
0178     DRM_DEBUG_DRIVER("Layer size W: %u H: %u\n",
0179              state->crtc_w, state->crtc_h);
0180     regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYSIZE_REG(layer),
0181              SUN4I_BACKEND_LAYSIZE(state->crtc_w,
0182                        state->crtc_h));
0183 
0184     /* Set base coordinates */
0185     DRM_DEBUG_DRIVER("Layer coordinates X: %d Y: %d\n",
0186              state->crtc_x, state->crtc_y);
0187     regmap_write(backend->engine.regs, SUN4I_BACKEND_LAYCOOR_REG(layer),
0188              SUN4I_BACKEND_LAYCOOR(state->crtc_x,
0189                        state->crtc_y));
0190 
0191     return 0;
0192 }
0193 
0194 static int sun4i_backend_update_yuv_format(struct sun4i_backend *backend,
0195                        int layer, struct drm_plane *plane)
0196 {
0197     struct drm_plane_state *state = plane->state;
0198     struct drm_framebuffer *fb = state->fb;
0199     const struct drm_format_info *format = fb->format;
0200     const uint32_t fmt = format->format;
0201     u32 val = SUN4I_BACKEND_IYUVCTL_EN;
0202     int i;
0203 
0204     for (i = 0; i < ARRAY_SIZE(sunxi_bt601_yuv2rgb_coef); i++)
0205         regmap_write(backend->engine.regs,
0206                  SUN4I_BACKEND_YGCOEF_REG(i),
0207                  sunxi_bt601_yuv2rgb_coef[i]);
0208 
0209     /*
0210      * We should do that only for a single plane, but the
0211      * framebuffer's atomic_check has our back on this.
0212      */
0213     regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
0214                SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN,
0215                SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN);
0216 
0217     /* TODO: Add support for the multi-planar YUV formats */
0218     if (drm_format_info_is_yuv_packed(format) &&
0219         drm_format_info_is_yuv_sampling_422(format))
0220         val |= SUN4I_BACKEND_IYUVCTL_FBFMT_PACKED_YUV422;
0221     else
0222         DRM_DEBUG_DRIVER("Unsupported YUV format (0x%x)\n", fmt);
0223 
0224     /*
0225      * Allwinner seems to list the pixel sequence from right to left, while
0226      * DRM lists it from left to right.
0227      */
0228     switch (fmt) {
0229     case DRM_FORMAT_YUYV:
0230         val |= SUN4I_BACKEND_IYUVCTL_FBPS_VYUY;
0231         break;
0232     case DRM_FORMAT_YVYU:
0233         val |= SUN4I_BACKEND_IYUVCTL_FBPS_UYVY;
0234         break;
0235     case DRM_FORMAT_UYVY:
0236         val |= SUN4I_BACKEND_IYUVCTL_FBPS_YVYU;
0237         break;
0238     case DRM_FORMAT_VYUY:
0239         val |= SUN4I_BACKEND_IYUVCTL_FBPS_YUYV;
0240         break;
0241     default:
0242         DRM_DEBUG_DRIVER("Unsupported YUV pixel sequence (0x%x)\n",
0243                  fmt);
0244     }
0245 
0246     regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVCTL_REG, val);
0247 
0248     return 0;
0249 }
0250 
0251 int sun4i_backend_update_layer_formats(struct sun4i_backend *backend,
0252                        int layer, struct drm_plane *plane)
0253 {
0254     struct drm_plane_state *state = plane->state;
0255     struct drm_framebuffer *fb = state->fb;
0256     u32 val;
0257     int ret;
0258 
0259     /* Clear the YUV mode */
0260     regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
0261                SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0);
0262 
0263     val = SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA(state->alpha >> 8);
0264     if (state->alpha != DRM_BLEND_ALPHA_OPAQUE)
0265         val |= SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN;
0266     regmap_update_bits(backend->engine.regs,
0267                SUN4I_BACKEND_ATTCTL_REG0(layer),
0268                SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_MASK |
0269                SUN4I_BACKEND_ATTCTL_REG0_LAY_GLBALPHA_EN,
0270                val);
0271 
0272     if (fb->format->is_yuv)
0273         return sun4i_backend_update_yuv_format(backend, layer, plane);
0274 
0275     ret = sun4i_backend_drm_format_to_layer(fb->format->format, &val);
0276     if (ret) {
0277         DRM_DEBUG_DRIVER("Invalid format\n");
0278         return ret;
0279     }
0280 
0281     regmap_update_bits(backend->engine.regs,
0282                SUN4I_BACKEND_ATTCTL_REG1(layer),
0283                SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
0284 
0285     return 0;
0286 }
0287 
0288 int sun4i_backend_update_layer_frontend(struct sun4i_backend *backend,
0289                     int layer, uint32_t fmt)
0290 {
0291     u32 val;
0292     int ret;
0293 
0294     ret = sun4i_backend_drm_format_to_layer(fmt, &val);
0295     if (ret) {
0296         DRM_DEBUG_DRIVER("Invalid format\n");
0297         return ret;
0298     }
0299 
0300     regmap_update_bits(backend->engine.regs,
0301                SUN4I_BACKEND_ATTCTL_REG0(layer),
0302                SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN,
0303                SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN);
0304 
0305     regmap_update_bits(backend->engine.regs,
0306                SUN4I_BACKEND_ATTCTL_REG1(layer),
0307                SUN4I_BACKEND_ATTCTL_REG1_LAY_FBFMT, val);
0308 
0309     return 0;
0310 }
0311 
0312 static int sun4i_backend_update_yuv_buffer(struct sun4i_backend *backend,
0313                        struct drm_framebuffer *fb,
0314                        dma_addr_t paddr)
0315 {
0316     /* TODO: Add support for the multi-planar YUV formats */
0317     DRM_DEBUG_DRIVER("Setting packed YUV buffer address to %pad\n", &paddr);
0318     regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVADD_REG(0), paddr);
0319 
0320     DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
0321     regmap_write(backend->engine.regs, SUN4I_BACKEND_IYUVLINEWIDTH_REG(0),
0322              fb->pitches[0] * 8);
0323 
0324     return 0;
0325 }
0326 
0327 int sun4i_backend_update_layer_buffer(struct sun4i_backend *backend,
0328                       int layer, struct drm_plane *plane)
0329 {
0330     struct drm_plane_state *state = plane->state;
0331     struct drm_framebuffer *fb = state->fb;
0332     u32 lo_paddr, hi_paddr;
0333     dma_addr_t paddr;
0334 
0335     /* Set the line width */
0336     DRM_DEBUG_DRIVER("Layer line width: %d bits\n", fb->pitches[0] * 8);
0337     regmap_write(backend->engine.regs,
0338              SUN4I_BACKEND_LAYLINEWIDTH_REG(layer),
0339              fb->pitches[0] * 8);
0340 
0341     /* Get the start of the displayed memory */
0342     paddr = drm_fb_cma_get_gem_addr(fb, state, 0);
0343     DRM_DEBUG_DRIVER("Setting buffer address to %pad\n", &paddr);
0344 
0345     if (fb->format->is_yuv)
0346         return sun4i_backend_update_yuv_buffer(backend, fb, paddr);
0347 
0348     /* Write the 32 lower bits of the address (in bits) */
0349     lo_paddr = paddr << 3;
0350     DRM_DEBUG_DRIVER("Setting address lower bits to 0x%x\n", lo_paddr);
0351     regmap_write(backend->engine.regs,
0352              SUN4I_BACKEND_LAYFB_L32ADD_REG(layer),
0353              lo_paddr);
0354 
0355     /* And the upper bits */
0356     hi_paddr = paddr >> 29;
0357     DRM_DEBUG_DRIVER("Setting address high bits to 0x%x\n", hi_paddr);
0358     regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_LAYFB_H4ADD_REG,
0359                SUN4I_BACKEND_LAYFB_H4ADD_MSK(layer),
0360                SUN4I_BACKEND_LAYFB_H4ADD(layer, hi_paddr));
0361 
0362     return 0;
0363 }
0364 
0365 int sun4i_backend_update_layer_zpos(struct sun4i_backend *backend, int layer,
0366                     struct drm_plane *plane)
0367 {
0368     struct drm_plane_state *state = plane->state;
0369     struct sun4i_layer_state *p_state = state_to_sun4i_layer_state(state);
0370     unsigned int priority = state->normalized_zpos;
0371     unsigned int pipe = p_state->pipe;
0372 
0373     DRM_DEBUG_DRIVER("Setting layer %d's priority to %d and pipe %d\n",
0374              layer, priority, pipe);
0375     regmap_update_bits(backend->engine.regs, SUN4I_BACKEND_ATTCTL_REG0(layer),
0376                SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL_MASK |
0377                SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL_MASK,
0378                SUN4I_BACKEND_ATTCTL_REG0_LAY_PIPESEL(p_state->pipe) |
0379                SUN4I_BACKEND_ATTCTL_REG0_LAY_PRISEL(priority));
0380 
0381     return 0;
0382 }
0383 
0384 void sun4i_backend_cleanup_layer(struct sun4i_backend *backend,
0385                  int layer)
0386 {
0387     regmap_update_bits(backend->engine.regs,
0388                SUN4I_BACKEND_ATTCTL_REG0(layer),
0389                SUN4I_BACKEND_ATTCTL_REG0_LAY_VDOEN |
0390                SUN4I_BACKEND_ATTCTL_REG0_LAY_YUVEN, 0);
0391 }
0392 
0393 static bool sun4i_backend_plane_uses_scaler(struct drm_plane_state *state)
0394 {
0395     u16 src_h = state->src_h >> 16;
0396     u16 src_w = state->src_w >> 16;
0397 
0398     DRM_DEBUG_DRIVER("Input size %dx%d, output size %dx%d\n",
0399              src_w, src_h, state->crtc_w, state->crtc_h);
0400 
0401     if ((state->crtc_h != src_h) || (state->crtc_w != src_w))
0402         return true;
0403 
0404     return false;
0405 }
0406 
0407 static bool sun4i_backend_plane_uses_frontend(struct drm_plane_state *state)
0408 {
0409     struct sun4i_layer *layer = plane_to_sun4i_layer(state->plane);
0410     struct sun4i_backend *backend = layer->backend;
0411     uint32_t format = state->fb->format->format;
0412     uint64_t modifier = state->fb->modifier;
0413 
0414     if (IS_ERR(backend->frontend))
0415         return false;
0416 
0417     if (!sun4i_frontend_format_is_supported(format, modifier))
0418         return false;
0419 
0420     if (!sun4i_backend_format_is_supported(format, modifier))
0421         return true;
0422 
0423     /*
0424      * TODO: The backend alone allows 2x and 4x integer scaling, including
0425      * support for an alpha component (which the frontend doesn't support).
0426      * Use the backend directly instead of the frontend in this case, with
0427      * another test to return false.
0428      */
0429 
0430     if (sun4i_backend_plane_uses_scaler(state))
0431         return true;
0432 
0433     /*
0434      * Here the format is supported by both the frontend and the backend
0435      * and no frontend scaling is required, so use the backend directly.
0436      */
0437     return false;
0438 }
0439 
0440 static bool sun4i_backend_plane_is_supported(struct drm_plane_state *state,
0441                          bool *uses_frontend)
0442 {
0443     if (sun4i_backend_plane_uses_frontend(state)) {
0444         *uses_frontend = true;
0445         return true;
0446     }
0447 
0448     *uses_frontend = false;
0449 
0450     /* Scaling is not supported without the frontend. */
0451     if (sun4i_backend_plane_uses_scaler(state))
0452         return false;
0453 
0454     return true;
0455 }
0456 
0457 static void sun4i_backend_atomic_begin(struct sunxi_engine *engine,
0458                        struct drm_crtc_state *old_state)
0459 {
0460     u32 val;
0461 
0462     WARN_ON(regmap_read_poll_timeout(engine->regs,
0463                      SUN4I_BACKEND_REGBUFFCTL_REG,
0464                      val, !(val & SUN4I_BACKEND_REGBUFFCTL_LOADCTL),
0465                      100, 50000));
0466 }
0467 
0468 static int sun4i_backend_atomic_check(struct sunxi_engine *engine,
0469                       struct drm_crtc_state *crtc_state)
0470 {
0471     struct drm_plane_state *plane_states[SUN4I_BACKEND_NUM_LAYERS] = { 0 };
0472     struct sun4i_backend *backend = engine_to_sun4i_backend(engine);
0473     struct drm_atomic_state *state = crtc_state->state;
0474     struct drm_device *drm = state->dev;
0475     struct drm_plane *plane;
0476     unsigned int num_planes = 0;
0477     unsigned int num_alpha_planes = 0;
0478     unsigned int num_frontend_planes = 0;
0479     unsigned int num_alpha_planes_max = 1;
0480     unsigned int num_yuv_planes = 0;
0481     unsigned int current_pipe = 0;
0482     unsigned int i;
0483 
0484     DRM_DEBUG_DRIVER("Starting checking our planes\n");
0485 
0486     if (!crtc_state->planes_changed)
0487         return 0;
0488 
0489     drm_for_each_plane_mask(plane, drm, crtc_state->plane_mask) {
0490         struct drm_plane_state *plane_state =
0491             drm_atomic_get_plane_state(state, plane);
0492         struct sun4i_layer_state *layer_state =
0493             state_to_sun4i_layer_state(plane_state);
0494         struct drm_framebuffer *fb = plane_state->fb;
0495 
0496         if (!sun4i_backend_plane_is_supported(plane_state,
0497                               &layer_state->uses_frontend))
0498             return -EINVAL;
0499 
0500         if (layer_state->uses_frontend) {
0501             DRM_DEBUG_DRIVER("Using the frontend for plane %d\n",
0502                      plane->index);
0503             num_frontend_planes++;
0504         } else {
0505             if (fb->format->is_yuv) {
0506                 DRM_DEBUG_DRIVER("Plane FB format is YUV\n");
0507                 num_yuv_planes++;
0508             }
0509         }
0510 
0511         DRM_DEBUG_DRIVER("Plane FB format is %p4cc\n",
0512                  &fb->format->format);
0513         if (fb->format->has_alpha || (plane_state->alpha != DRM_BLEND_ALPHA_OPAQUE))
0514             num_alpha_planes++;
0515 
0516         DRM_DEBUG_DRIVER("Plane zpos is %d\n",
0517                  plane_state->normalized_zpos);
0518 
0519         /* Sort our planes by Zpos */
0520         plane_states[plane_state->normalized_zpos] = plane_state;
0521 
0522         num_planes++;
0523     }
0524 
0525     /* All our planes were disabled, bail out */
0526     if (!num_planes)
0527         return 0;
0528 
0529     /*
0530      * The hardware is a bit unusual here.
0531      *
0532      * Even though it supports 4 layers, it does the composition
0533      * in two separate steps.
0534      *
0535      * The first one is assigning a layer to one of its two
0536      * pipes. If more that 1 layer is assigned to the same pipe,
0537      * and if pixels overlaps, the pipe will take the pixel from
0538      * the layer with the highest priority.
0539      *
0540      * The second step is the actual alpha blending, that takes
0541      * the two pipes as input, and uses the potential alpha
0542      * component to do the transparency between the two.
0543      *
0544      * This two-step scenario makes us unable to guarantee a
0545      * robust alpha blending between the 4 layers in all
0546      * situations, since this means that we need to have one layer
0547      * with alpha at the lowest position of our two pipes.
0548      *
0549      * However, we cannot even do that on every platform, since
0550      * the hardware has a bug where the lowest plane of the lowest
0551      * pipe (pipe 0, priority 0), if it has any alpha, will
0552      * discard the pixel data entirely and just display the pixels
0553      * in the background color (black by default).
0554      *
0555      * This means that on the affected platforms, we effectively
0556      * have only three valid configurations with alpha, all of
0557      * them with the alpha being on pipe1 with the lowest
0558      * position, which can be 1, 2 or 3 depending on the number of
0559      * planes and their zpos.
0560      */
0561 
0562     /* For platforms that are not affected by the issue described above. */
0563     if (backend->quirks->supports_lowest_plane_alpha)
0564         num_alpha_planes_max++;
0565 
0566     if (num_alpha_planes > num_alpha_planes_max) {
0567         DRM_DEBUG_DRIVER("Too many planes with alpha, rejecting...\n");
0568         return -EINVAL;
0569     }
0570 
0571     /* We can't have an alpha plane at the lowest position */
0572     if (!backend->quirks->supports_lowest_plane_alpha &&
0573         (plane_states[0]->alpha != DRM_BLEND_ALPHA_OPAQUE))
0574         return -EINVAL;
0575 
0576     for (i = 1; i < num_planes; i++) {
0577         struct drm_plane_state *p_state = plane_states[i];
0578         struct drm_framebuffer *fb = p_state->fb;
0579         struct sun4i_layer_state *s_state = state_to_sun4i_layer_state(p_state);
0580 
0581         /*
0582          * The only alpha position is the lowest plane of the
0583          * second pipe.
0584          */
0585         if (fb->format->has_alpha || (p_state->alpha != DRM_BLEND_ALPHA_OPAQUE))
0586             current_pipe++;
0587 
0588         s_state->pipe = current_pipe;
0589     }
0590 
0591     /* We can only have a single YUV plane at a time */
0592     if (num_yuv_planes > SUN4I_BACKEND_NUM_YUV_PLANES) {
0593         DRM_DEBUG_DRIVER("Too many planes with YUV, rejecting...\n");
0594         return -EINVAL;
0595     }
0596 
0597     if (num_frontend_planes > SUN4I_BACKEND_NUM_FRONTEND_LAYERS) {
0598         DRM_DEBUG_DRIVER("Too many planes going through the frontend, rejecting\n");
0599         return -EINVAL;
0600     }
0601 
0602     DRM_DEBUG_DRIVER("State valid with %u planes, %u alpha, %u video, %u YUV\n",
0603              num_planes, num_alpha_planes, num_frontend_planes,
0604              num_yuv_planes);
0605 
0606     return 0;
0607 }
0608 
0609 static void sun4i_backend_vblank_quirk(struct sunxi_engine *engine)
0610 {
0611     struct sun4i_backend *backend = engine_to_sun4i_backend(engine);
0612     struct sun4i_frontend *frontend = backend->frontend;
0613 
0614     if (!frontend)
0615         return;
0616 
0617     /*
0618      * In a teardown scenario with the frontend involved, we have
0619      * to keep the frontend enabled until the next vblank, and
0620      * only then disable it.
0621      *
0622      * This is due to the fact that the backend will not take into
0623      * account the new configuration (with the plane that used to
0624      * be fed by the frontend now disabled) until we write to the
0625      * commit bit and the hardware fetches the new configuration
0626      * during the next vblank.
0627      *
0628      * So we keep the frontend around in order to prevent any
0629      * visual artifacts.
0630      */
0631     spin_lock(&backend->frontend_lock);
0632     if (backend->frontend_teardown) {
0633         sun4i_frontend_exit(frontend);
0634         backend->frontend_teardown = false;
0635     }
0636     spin_unlock(&backend->frontend_lock);
0637 };
0638 
0639 static void sun4i_backend_mode_set(struct sunxi_engine *engine,
0640                    const struct drm_display_mode *mode)
0641 {
0642     bool interlaced = !!(mode->flags & DRM_MODE_FLAG_INTERLACE);
0643 
0644     DRM_DEBUG_DRIVER("Updating global size W: %u H: %u\n",
0645              mode->hdisplay, mode->vdisplay);
0646 
0647     regmap_write(engine->regs, SUN4I_BACKEND_DISSIZE_REG,
0648              SUN4I_BACKEND_DISSIZE(mode->hdisplay, mode->vdisplay));
0649 
0650     regmap_update_bits(engine->regs, SUN4I_BACKEND_MODCTL_REG,
0651                SUN4I_BACKEND_MODCTL_ITLMOD_EN,
0652                interlaced ? SUN4I_BACKEND_MODCTL_ITLMOD_EN : 0);
0653 
0654     DRM_DEBUG_DRIVER("Switching display backend interlaced mode %s\n",
0655              interlaced ? "on" : "off");
0656 }
0657 
0658 static int sun4i_backend_init_sat(struct device *dev) {
0659     struct sun4i_backend *backend = dev_get_drvdata(dev);
0660     int ret;
0661 
0662     backend->sat_reset = devm_reset_control_get(dev, "sat");
0663     if (IS_ERR(backend->sat_reset)) {
0664         dev_err(dev, "Couldn't get the SAT reset line\n");
0665         return PTR_ERR(backend->sat_reset);
0666     }
0667 
0668     ret = reset_control_deassert(backend->sat_reset);
0669     if (ret) {
0670         dev_err(dev, "Couldn't deassert the SAT reset line\n");
0671         return ret;
0672     }
0673 
0674     backend->sat_clk = devm_clk_get(dev, "sat");
0675     if (IS_ERR(backend->sat_clk)) {
0676         dev_err(dev, "Couldn't get our SAT clock\n");
0677         ret = PTR_ERR(backend->sat_clk);
0678         goto err_assert_reset;
0679     }
0680 
0681     ret = clk_prepare_enable(backend->sat_clk);
0682     if (ret) {
0683         dev_err(dev, "Couldn't enable the SAT clock\n");
0684         return ret;
0685     }
0686 
0687     return 0;
0688 
0689 err_assert_reset:
0690     reset_control_assert(backend->sat_reset);
0691     return ret;
0692 }
0693 
0694 static int sun4i_backend_free_sat(struct device *dev) {
0695     struct sun4i_backend *backend = dev_get_drvdata(dev);
0696 
0697     clk_disable_unprepare(backend->sat_clk);
0698     reset_control_assert(backend->sat_reset);
0699 
0700     return 0;
0701 }
0702 
0703 /*
0704  * The display backend can take video output from the display frontend, or
0705  * the display enhancement unit on the A80, as input for one it its layers.
0706  * This relationship within the display pipeline is encoded in the device
0707  * tree with of_graph, and we use it here to figure out which backend, if
0708  * there are 2 or more, we are currently probing. The number would be in
0709  * the "reg" property of the upstream output port endpoint.
0710  */
0711 static int sun4i_backend_of_get_id(struct device_node *node)
0712 {
0713     struct device_node *ep, *remote;
0714     struct of_endpoint of_ep;
0715 
0716     /* Input port is 0, and we want the first endpoint. */
0717     ep = of_graph_get_endpoint_by_regs(node, 0, -1);
0718     if (!ep)
0719         return -EINVAL;
0720 
0721     remote = of_graph_get_remote_endpoint(ep);
0722     of_node_put(ep);
0723     if (!remote)
0724         return -EINVAL;
0725 
0726     of_graph_parse_endpoint(remote, &of_ep);
0727     of_node_put(remote);
0728     return of_ep.id;
0729 }
0730 
0731 /* TODO: This needs to take multiple pipelines into account */
0732 static struct sun4i_frontend *sun4i_backend_find_frontend(struct sun4i_drv *drv,
0733                               struct device_node *node)
0734 {
0735     struct device_node *port, *ep, *remote;
0736     struct sun4i_frontend *frontend;
0737 
0738     port = of_graph_get_port_by_id(node, 0);
0739     if (!port)
0740         return ERR_PTR(-EINVAL);
0741 
0742     for_each_available_child_of_node(port, ep) {
0743         remote = of_graph_get_remote_port_parent(ep);
0744         if (!remote)
0745             continue;
0746         of_node_put(remote);
0747 
0748         /* does this node match any registered engines? */
0749         list_for_each_entry(frontend, &drv->frontend_list, list) {
0750             if (remote == frontend->node) {
0751                 of_node_put(port);
0752                 of_node_put(ep);
0753                 return frontend;
0754             }
0755         }
0756     }
0757     of_node_put(port);
0758     return ERR_PTR(-EINVAL);
0759 }
0760 
0761 static const struct sunxi_engine_ops sun4i_backend_engine_ops = {
0762     .atomic_begin           = sun4i_backend_atomic_begin,
0763     .atomic_check           = sun4i_backend_atomic_check,
0764     .commit             = sun4i_backend_commit,
0765     .layers_init            = sun4i_layers_init,
0766     .apply_color_correction     = sun4i_backend_apply_color_correction,
0767     .disable_color_correction   = sun4i_backend_disable_color_correction,
0768     .vblank_quirk           = sun4i_backend_vblank_quirk,
0769     .mode_set           = sun4i_backend_mode_set,
0770 };
0771 
0772 static const struct regmap_config sun4i_backend_regmap_config = {
0773     .reg_bits   = 32,
0774     .val_bits   = 32,
0775     .reg_stride = 4,
0776     .max_register   = 0x5800,
0777 };
0778 
0779 static int sun4i_backend_bind(struct device *dev, struct device *master,
0780                   void *data)
0781 {
0782     struct platform_device *pdev = to_platform_device(dev);
0783     struct drm_device *drm = data;
0784     struct sun4i_drv *drv = drm->dev_private;
0785     struct sun4i_backend *backend;
0786     const struct sun4i_backend_quirks *quirks;
0787     void __iomem *regs;
0788     int i, ret;
0789 
0790     backend = devm_kzalloc(dev, sizeof(*backend), GFP_KERNEL);
0791     if (!backend)
0792         return -ENOMEM;
0793     dev_set_drvdata(dev, backend);
0794     spin_lock_init(&backend->frontend_lock);
0795 
0796     if (of_find_property(dev->of_node, "interconnects", NULL)) {
0797         /*
0798          * This assume we have the same DMA constraints for all our the
0799          * devices in our pipeline (all the backends, but also the
0800          * frontends). This sounds bad, but it has always been the case
0801          * for us, and DRM doesn't do per-device allocation either, so
0802          * we would need to fix DRM first...
0803          */
0804         ret = of_dma_configure(drm->dev, dev->of_node, true);
0805         if (ret)
0806             return ret;
0807     }
0808 
0809     backend->engine.node = dev->of_node;
0810     backend->engine.ops = &sun4i_backend_engine_ops;
0811     backend->engine.id = sun4i_backend_of_get_id(dev->of_node);
0812     if (backend->engine.id < 0)
0813         return backend->engine.id;
0814 
0815     backend->frontend = sun4i_backend_find_frontend(drv, dev->of_node);
0816     if (IS_ERR(backend->frontend))
0817         dev_warn(dev, "Couldn't find matching frontend, frontend features disabled\n");
0818 
0819     regs = devm_platform_ioremap_resource(pdev, 0);
0820     if (IS_ERR(regs))
0821         return PTR_ERR(regs);
0822 
0823     backend->reset = devm_reset_control_get(dev, NULL);
0824     if (IS_ERR(backend->reset)) {
0825         dev_err(dev, "Couldn't get our reset line\n");
0826         return PTR_ERR(backend->reset);
0827     }
0828 
0829     ret = reset_control_deassert(backend->reset);
0830     if (ret) {
0831         dev_err(dev, "Couldn't deassert our reset line\n");
0832         return ret;
0833     }
0834 
0835     backend->bus_clk = devm_clk_get(dev, "ahb");
0836     if (IS_ERR(backend->bus_clk)) {
0837         dev_err(dev, "Couldn't get the backend bus clock\n");
0838         ret = PTR_ERR(backend->bus_clk);
0839         goto err_assert_reset;
0840     }
0841     clk_prepare_enable(backend->bus_clk);
0842 
0843     backend->mod_clk = devm_clk_get(dev, "mod");
0844     if (IS_ERR(backend->mod_clk)) {
0845         dev_err(dev, "Couldn't get the backend module clock\n");
0846         ret = PTR_ERR(backend->mod_clk);
0847         goto err_disable_bus_clk;
0848     }
0849 
0850     ret = clk_set_rate_exclusive(backend->mod_clk, 300000000);
0851     if (ret) {
0852         dev_err(dev, "Couldn't set the module clock frequency\n");
0853         goto err_disable_bus_clk;
0854     }
0855 
0856     clk_prepare_enable(backend->mod_clk);
0857 
0858     backend->ram_clk = devm_clk_get(dev, "ram");
0859     if (IS_ERR(backend->ram_clk)) {
0860         dev_err(dev, "Couldn't get the backend RAM clock\n");
0861         ret = PTR_ERR(backend->ram_clk);
0862         goto err_disable_mod_clk;
0863     }
0864     clk_prepare_enable(backend->ram_clk);
0865 
0866     if (of_device_is_compatible(dev->of_node,
0867                     "allwinner,sun8i-a33-display-backend")) {
0868         ret = sun4i_backend_init_sat(dev);
0869         if (ret) {
0870             dev_err(dev, "Couldn't init SAT resources\n");
0871             goto err_disable_ram_clk;
0872         }
0873     }
0874 
0875     backend->engine.regs = devm_regmap_init_mmio(dev, regs,
0876                              &sun4i_backend_regmap_config);
0877     if (IS_ERR(backend->engine.regs)) {
0878         dev_err(dev, "Couldn't create the backend regmap\n");
0879         return PTR_ERR(backend->engine.regs);
0880     }
0881 
0882     list_add_tail(&backend->engine.list, &drv->engine_list);
0883 
0884     /*
0885      * Many of the backend's layer configuration registers have
0886      * undefined default values. This poses a risk as we use
0887      * regmap_update_bits in some places, and don't overwrite
0888      * the whole register.
0889      *
0890      * Clear the registers here to have something predictable.
0891      */
0892     for (i = 0x800; i < 0x1000; i += 4)
0893         regmap_write(backend->engine.regs, i, 0);
0894 
0895     /* Disable registers autoloading */
0896     regmap_write(backend->engine.regs, SUN4I_BACKEND_REGBUFFCTL_REG,
0897              SUN4I_BACKEND_REGBUFFCTL_AUTOLOAD_DIS);
0898 
0899     /* Enable the backend */
0900     regmap_write(backend->engine.regs, SUN4I_BACKEND_MODCTL_REG,
0901              SUN4I_BACKEND_MODCTL_DEBE_EN |
0902              SUN4I_BACKEND_MODCTL_START_CTL);
0903 
0904     /* Set output selection if needed */
0905     quirks = of_device_get_match_data(dev);
0906     if (quirks->needs_output_muxing) {
0907         /*
0908          * We assume there is no dynamic muxing of backends
0909          * and TCONs, so we select the backend with same ID.
0910          *
0911          * While dynamic selection might be interesting, since
0912          * the CRTC is tied to the TCON, while the layers are
0913          * tied to the backends, this means, we will need to
0914          * switch between groups of layers. There might not be
0915          * a way to represent this constraint in DRM.
0916          */
0917         regmap_update_bits(backend->engine.regs,
0918                    SUN4I_BACKEND_MODCTL_REG,
0919                    SUN4I_BACKEND_MODCTL_OUT_SEL,
0920                    (backend->engine.id
0921                     ? SUN4I_BACKEND_MODCTL_OUT_LCD1
0922                     : SUN4I_BACKEND_MODCTL_OUT_LCD0));
0923     }
0924 
0925     backend->quirks = quirks;
0926 
0927     return 0;
0928 
0929 err_disable_ram_clk:
0930     clk_disable_unprepare(backend->ram_clk);
0931 err_disable_mod_clk:
0932     clk_rate_exclusive_put(backend->mod_clk);
0933     clk_disable_unprepare(backend->mod_clk);
0934 err_disable_bus_clk:
0935     clk_disable_unprepare(backend->bus_clk);
0936 err_assert_reset:
0937     reset_control_assert(backend->reset);
0938     return ret;
0939 }
0940 
0941 static void sun4i_backend_unbind(struct device *dev, struct device *master,
0942                  void *data)
0943 {
0944     struct sun4i_backend *backend = dev_get_drvdata(dev);
0945 
0946     list_del(&backend->engine.list);
0947 
0948     if (of_device_is_compatible(dev->of_node,
0949                     "allwinner,sun8i-a33-display-backend"))
0950         sun4i_backend_free_sat(dev);
0951 
0952     clk_disable_unprepare(backend->ram_clk);
0953     clk_rate_exclusive_put(backend->mod_clk);
0954     clk_disable_unprepare(backend->mod_clk);
0955     clk_disable_unprepare(backend->bus_clk);
0956     reset_control_assert(backend->reset);
0957 }
0958 
0959 static const struct component_ops sun4i_backend_ops = {
0960     .bind   = sun4i_backend_bind,
0961     .unbind = sun4i_backend_unbind,
0962 };
0963 
0964 static int sun4i_backend_probe(struct platform_device *pdev)
0965 {
0966     return component_add(&pdev->dev, &sun4i_backend_ops);
0967 }
0968 
0969 static int sun4i_backend_remove(struct platform_device *pdev)
0970 {
0971     component_del(&pdev->dev, &sun4i_backend_ops);
0972 
0973     return 0;
0974 }
0975 
0976 static const struct sun4i_backend_quirks sun4i_backend_quirks = {
0977     .needs_output_muxing = true,
0978 };
0979 
0980 static const struct sun4i_backend_quirks sun5i_backend_quirks = {
0981 };
0982 
0983 static const struct sun4i_backend_quirks sun6i_backend_quirks = {
0984 };
0985 
0986 static const struct sun4i_backend_quirks sun7i_backend_quirks = {
0987     .needs_output_muxing = true,
0988 };
0989 
0990 static const struct sun4i_backend_quirks sun8i_a33_backend_quirks = {
0991     .supports_lowest_plane_alpha = true,
0992 };
0993 
0994 static const struct sun4i_backend_quirks sun9i_backend_quirks = {
0995 };
0996 
0997 static const struct of_device_id sun4i_backend_of_table[] = {
0998     {
0999         .compatible = "allwinner,sun4i-a10-display-backend",
1000         .data = &sun4i_backend_quirks,
1001     },
1002     {
1003         .compatible = "allwinner,sun5i-a13-display-backend",
1004         .data = &sun5i_backend_quirks,
1005     },
1006     {
1007         .compatible = "allwinner,sun6i-a31-display-backend",
1008         .data = &sun6i_backend_quirks,
1009     },
1010     {
1011         .compatible = "allwinner,sun7i-a20-display-backend",
1012         .data = &sun7i_backend_quirks,
1013     },
1014     {
1015         .compatible = "allwinner,sun8i-a23-display-backend",
1016         .data = &sun8i_a33_backend_quirks,
1017     },
1018     {
1019         .compatible = "allwinner,sun8i-a33-display-backend",
1020         .data = &sun8i_a33_backend_quirks,
1021     },
1022     {
1023         .compatible = "allwinner,sun9i-a80-display-backend",
1024         .data = &sun9i_backend_quirks,
1025     },
1026     { }
1027 };
1028 MODULE_DEVICE_TABLE(of, sun4i_backend_of_table);
1029 
1030 static struct platform_driver sun4i_backend_platform_driver = {
1031     .probe      = sun4i_backend_probe,
1032     .remove     = sun4i_backend_remove,
1033     .driver     = {
1034         .name       = "sun4i-backend",
1035         .of_match_table = sun4i_backend_of_table,
1036     },
1037 };
1038 module_platform_driver(sun4i_backend_platform_driver);
1039 
1040 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>");
1041 MODULE_DESCRIPTION("Allwinner A10 Display Backend Driver");
1042 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!