drm/stm/ltdc.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) STMicroelectronics SA 2017
0004  *
0005  * Authors: Philippe Cornu <philippe.cornu@st.com>
0006  *          Yannick Fertre <yannick.fertre@st.com>
0007  *          Fabien Dessenne <fabien.dessenne@st.com>
0008  *          Mickael Reulier <mickael.reulier@st.com>
0009  */
0010
0011 #ifndef _LTDC_H_
0012 #define _LTDC_H_
0013
0014 struct ltdc_caps {
0015     u32 hw_version;     /* hardware version */
0016     u32 nb_layers;      /* number of supported layers */
0017     u32 layer_ofs;      /* layer offset for applicable regs */
0018     const u32 *layer_regs;  /* layer register offset */
0019     u32 bus_width;      /* bus width (32 or 64 bits) */
0020     const u32 *pix_fmt_hw;  /* supported hw pixel formats */
0021     const u32 *pix_fmt_drm; /* supported drm pixel formats */
0022     int pix_fmt_nb;     /* number of pixel format */
0023     bool pix_fmt_flex;  /* pixel format flexibility supported */
0024     bool non_alpha_only_l1; /* non-native no-alpha formats on layer 1 */
0025     int pad_max_freq_hz;    /* max frequency supported by pad */
0026     int nb_irq;     /* number of hardware interrupts */
0027     bool ycbcr_input;   /* ycbcr input converter supported */
0028     bool ycbcr_output;  /* ycbcr output converter supported */
0029     bool plane_reg_shadow;  /* plane shadow registers ability */
0030     bool crc;       /* cyclic redundancy check supported */
0031     bool dynamic_zorder;    /* dynamic z-order */
0032     bool plane_rotation;    /* plane rotation */
0033     bool fifo_threshold;    /* fifo underrun threshold supported */
0034 };
0035
0036 #define LTDC_MAX_LAYER  4
0037
0038 struct fps_info {
0039     unsigned int counter;
0040     ktime_t last_timestamp;
0041 };
0042
0043 struct ltdc_device {
0044     void __iomem *regs;
0045     struct regmap *regmap;
0046     struct clk *pixel_clk;  /* lcd pixel clock */
0047     struct mutex err_lock;  /* protecting error_status */
0048     struct ltdc_caps caps;
0049     u32 irq_status;
0050     u32 fifo_err;       /* fifo underrun error counter */
0051     u32 fifo_warn;      /* fifo underrun warning counter */
0052     u32 fifo_threshold; /* fifo underrun threshold */
0053     u32 transfer_err;   /* transfer error counter */
0054     struct fps_info plane_fpsi[LTDC_MAX_LAYER];
0055     struct drm_atomic_state *suspend_state;
0056     int crc_skip_count;
0057     bool crc_active;
0058 };
0059
0060 int ltdc_load(struct drm_device *ddev);
0061 void ltdc_unload(struct drm_device *ddev);
0062 void ltdc_suspend(struct drm_device *ddev);
0063 int ltdc_resume(struct drm_device *ddev);
0064
0065 #endif