drm/sti/sti_vtg.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) STMicroelectronics SA 2014
0004  * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
0005  *          Fabien Dessenne <fabien.dessenne@st.com>
0006  *          Vincent Abriou <vincent.abriou@st.com>
0007  *          for STMicroelectronics.
0008  */
0009
0010 #include <linux/module.h>
0011 #include <linux/io.h>
0012 #include <linux/notifier.h>
0013 #include <linux/of_platform.h>
0014 #include <linux/platform_device.h>
0015
0016 #include <drm/drm_modes.h>
0017 #include <drm/drm_print.h>
0018
0019 #include "sti_drv.h"
0020 #include "sti_vtg.h"
0021
0022 #define VTG_MODE_MASTER         0
0023
0024 /* registers offset */
0025 #define VTG_MODE            0x0000
0026 #define VTG_CLKLN           0x0008
0027 #define VTG_HLFLN           0x000C
0028 #define VTG_DRST_AUTOC      0x0010
0029 #define VTG_VID_TFO         0x0040
0030 #define VTG_VID_TFS         0x0044
0031 #define VTG_VID_BFO         0x0048
0032 #define VTG_VID_BFS         0x004C
0033
0034 #define VTG_HOST_ITS        0x0078
0035 #define VTG_HOST_ITS_BCLR   0x007C
0036 #define VTG_HOST_ITM_BCLR   0x0088
0037 #define VTG_HOST_ITM_BSET   0x008C
0038
0039 #define VTG_H_HD_1          0x00C0
0040 #define VTG_TOP_V_VD_1      0x00C4
0041 #define VTG_BOT_V_VD_1      0x00C8
0042 #define VTG_TOP_V_HD_1      0x00CC
0043 #define VTG_BOT_V_HD_1      0x00D0
0044
0045 #define VTG_H_HD_2          0x00E0
0046 #define VTG_TOP_V_VD_2      0x00E4
0047 #define VTG_BOT_V_VD_2      0x00E8
0048 #define VTG_TOP_V_HD_2      0x00EC
0049 #define VTG_BOT_V_HD_2      0x00F0
0050
0051 #define VTG_H_HD_3          0x0100
0052 #define VTG_TOP_V_VD_3      0x0104
0053 #define VTG_BOT_V_VD_3      0x0108
0054 #define VTG_TOP_V_HD_3      0x010C
0055 #define VTG_BOT_V_HD_3      0x0110
0056
0057 #define VTG_H_HD_4          0x0120
0058 #define VTG_TOP_V_VD_4      0x0124
0059 #define VTG_BOT_V_VD_4      0x0128
0060 #define VTG_TOP_V_HD_4      0x012c
0061 #define VTG_BOT_V_HD_4      0x0130
0062
0063 #define VTG_IRQ_BOTTOM      BIT(0)
0064 #define VTG_IRQ_TOP         BIT(1)
0065 #define VTG_IRQ_MASK        (VTG_IRQ_TOP | VTG_IRQ_BOTTOM)
0066
0067 /* Delay introduced by the HDMI in nb of pixel */
0068 #define HDMI_DELAY          (5)
0069
0070 /* Delay introduced by the DVO in nb of pixel */
0071 #define DVO_DELAY           (7)
0072
0073 /* delay introduced by the Arbitrary Waveform Generator in nb of pixels */
0074 #define AWG_DELAY_HD        (-9)
0075 #define AWG_DELAY_ED        (-8)
0076 #define AWG_DELAY_SD        (-7)
0077
0078 /*
0079  * STI VTG register offset structure
0080  *
0081  *@h_hd:     stores the VTG_H_HD_x     register offset
0082  *@top_v_vd: stores the VTG_TOP_V_VD_x register offset
0083  *@bot_v_vd: stores the VTG_BOT_V_VD_x register offset
0084  *@top_v_hd: stores the VTG_TOP_V_HD_x register offset
0085  *@bot_v_hd: stores the VTG_BOT_V_HD_x register offset
0086  */
0087 struct sti_vtg_regs_offs {
0088     u32 h_hd;
0089     u32 top_v_vd;
0090     u32 bot_v_vd;
0091     u32 top_v_hd;
0092     u32 bot_v_hd;
0093 };
0094
0095 #define VTG_MAX_SYNC_OUTPUT 4
0096 static const struct sti_vtg_regs_offs vtg_regs_offs[VTG_MAX_SYNC_OUTPUT] = {
0097     { VTG_H_HD_1,
0098       VTG_TOP_V_VD_1, VTG_BOT_V_VD_1, VTG_TOP_V_HD_1, VTG_BOT_V_HD_1 },
0099     { VTG_H_HD_2,
0100       VTG_TOP_V_VD_2, VTG_BOT_V_VD_2, VTG_TOP_V_HD_2, VTG_BOT_V_HD_2 },
0101     { VTG_H_HD_3,
0102       VTG_TOP_V_VD_3, VTG_BOT_V_VD_3, VTG_TOP_V_HD_3, VTG_BOT_V_HD_3 },
0103     { VTG_H_HD_4,
0104       VTG_TOP_V_VD_4, VTG_BOT_V_VD_4, VTG_TOP_V_HD_4, VTG_BOT_V_HD_4 }
0105 };
0106
0107 /*
0108  * STI VTG synchronisation parameters structure
0109  *
0110  *@hsync: sample number falling and rising edge
0111  *@vsync_line_top: vertical top field line number falling and rising edge
0112  *@vsync_line_bot: vertical bottom field line number falling and rising edge
0113  *@vsync_off_top: vertical top field sample number rising and falling edge
0114  *@vsync_off_bot: vertical bottom field sample number rising and falling edge
0115  */
0116 struct sti_vtg_sync_params {
0117     u32 hsync;
0118     u32 vsync_line_top;
0119     u32 vsync_line_bot;
0120     u32 vsync_off_top;
0121     u32 vsync_off_bot;
0122 };
0123
0124 /*
0125  * STI VTG structure
0126  *
0127  * @regs: register mapping
0128  * @sync_params: synchronisation parameters used to generate timings
0129  * @irq: VTG irq
0130  * @irq_status: store the IRQ status value
0131  * @notifier_list: notifier callback
0132  * @crtc: the CRTC for vblank event
0133  */
0134 struct sti_vtg {
0135     void __iomem *regs;
0136     struct sti_vtg_sync_params sync_params[VTG_MAX_SYNC_OUTPUT];
0137     int irq;
0138     u32 irq_status;
0139     struct raw_notifier_head notifier_list;
0140     struct drm_crtc *crtc;
0141 };
0142
0143 struct sti_vtg *of_vtg_find(struct device_node *np)
0144 {
0145     struct platform_device *pdev;
0146
0147     pdev = of_find_device_by_node(np);
0148     if (!pdev)
0149         return NULL;
0150
0151     return (struct sti_vtg *)platform_get_drvdata(pdev);
0152 }
0153
0154 static void vtg_reset(struct sti_vtg *vtg)
0155 {
0156     writel(1, vtg->regs + VTG_DRST_AUTOC);
0157 }
0158
0159 static void vtg_set_output_window(void __iomem *regs,
0160                   const struct drm_display_mode *mode)
0161 {
0162     u32 video_top_field_start;
0163     u32 video_top_field_stop;
0164     u32 video_bottom_field_start;
0165     u32 video_bottom_field_stop;
0166     u32 xstart = sti_vtg_get_pixel_number(*mode, 0);
0167     u32 ystart = sti_vtg_get_line_number(*mode, 0);
0168     u32 xstop = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
0169     u32 ystop = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
0170
0171     /* Set output window to fit the display mode selected */
0172     video_top_field_start = (ystart << 16) | xstart;
0173     video_top_field_stop = (ystop << 16) | xstop;
0174
0175     /* Only progressive supported for now */
0176     video_bottom_field_start = video_top_field_start;
0177     video_bottom_field_stop = video_top_field_stop;
0178
0179     writel(video_top_field_start, regs + VTG_VID_TFO);
0180     writel(video_top_field_stop, regs + VTG_VID_TFS);
0181     writel(video_bottom_field_start, regs + VTG_VID_BFO);
0182     writel(video_bottom_field_stop, regs + VTG_VID_BFS);
0183 }
0184
0185 static void vtg_set_hsync_vsync_pos(struct sti_vtg_sync_params *sync,
0186                     int delay,
0187                     const struct drm_display_mode *mode)
0188 {
0189     long clocksperline, start, stop;
0190     u32 risesync_top, fallsync_top;
0191     u32 risesync_offs_top, fallsync_offs_top;
0192
0193     clocksperline = mode->htotal;
0194
0195     /* Get the hsync position */
0196     start = 0;
0197     stop = mode->hsync_end - mode->hsync_start;
0198
0199     start += delay;
0200     stop  += delay;
0201
0202     if (start < 0)
0203         start += clocksperline;
0204     else if (start >= clocksperline)
0205         start -= clocksperline;
0206
0207     if (stop < 0)
0208         stop += clocksperline;
0209     else if (stop >= clocksperline)
0210         stop -= clocksperline;
0211
0212     sync->hsync = (stop << 16) | start;
0213
0214     /* Get the vsync position */
0215     if (delay >= 0) {
0216         risesync_top = 1;
0217         fallsync_top = risesync_top;
0218         fallsync_top += mode->vsync_end - mode->vsync_start;
0219
0220         fallsync_offs_top = (u32)delay;
0221         risesync_offs_top = (u32)delay;
0222     } else {
0223         risesync_top = mode->vtotal;
0224         fallsync_top = mode->vsync_end - mode->vsync_start;
0225
0226         fallsync_offs_top = clocksperline + delay;
0227         risesync_offs_top = clocksperline + delay;
0228     }
0229
0230     sync->vsync_line_top = (fallsync_top << 16) | risesync_top;
0231     sync->vsync_off_top = (fallsync_offs_top << 16) | risesync_offs_top;
0232
0233     /* Only progressive supported for now */
0234     sync->vsync_line_bot = sync->vsync_line_top;
0235     sync->vsync_off_bot = sync->vsync_off_top;
0236 }
0237
0238 static void vtg_set_mode(struct sti_vtg *vtg,
0239              int type,
0240              struct sti_vtg_sync_params *sync,
0241              const struct drm_display_mode *mode)
0242 {
0243     unsigned int i;
0244
0245     /* Set the number of clock cycles per line */
0246     writel(mode->htotal, vtg->regs + VTG_CLKLN);
0247
0248     /* Set Half Line Per Field (only progressive supported for now) */
0249     writel(mode->vtotal * 2, vtg->regs + VTG_HLFLN);
0250
0251     /* Program output window */
0252     vtg_set_output_window(vtg->regs, mode);
0253
0254     /* Set hsync and vsync position for HDMI */
0255     vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDMI - 1], HDMI_DELAY, mode);
0256
0257     /* Set hsync and vsync position for HD DCS */
0258     vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDDCS - 1], 0, mode);
0259
0260     /* Set hsync and vsync position for HDF */
0261     vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_HDF - 1], AWG_DELAY_HD, mode);
0262
0263     /* Set hsync and vsync position for DVO */
0264     vtg_set_hsync_vsync_pos(&sync[VTG_SYNC_ID_DVO - 1], DVO_DELAY, mode);
0265
0266     /* Progam the syncs outputs */
0267     for (i = 0; i < VTG_MAX_SYNC_OUTPUT ; i++) {
0268         writel(sync[i].hsync,
0269                vtg->regs + vtg_regs_offs[i].h_hd);
0270         writel(sync[i].vsync_line_top,
0271                vtg->regs + vtg_regs_offs[i].top_v_vd);
0272         writel(sync[i].vsync_line_bot,
0273                vtg->regs + vtg_regs_offs[i].bot_v_vd);
0274         writel(sync[i].vsync_off_top,
0275                vtg->regs + vtg_regs_offs[i].top_v_hd);
0276         writel(sync[i].vsync_off_bot,
0277                vtg->regs + vtg_regs_offs[i].bot_v_hd);
0278     }
0279
0280     /* mode */
0281     writel(type, vtg->regs + VTG_MODE);
0282 }
0283
0284 static void vtg_enable_irq(struct sti_vtg *vtg)
0285 {
0286     /* clear interrupt status and mask */
0287     writel(0xFFFF, vtg->regs + VTG_HOST_ITS_BCLR);
0288     writel(0xFFFF, vtg->regs + VTG_HOST_ITM_BCLR);
0289     writel(VTG_IRQ_MASK, vtg->regs + VTG_HOST_ITM_BSET);
0290 }
0291
0292 void sti_vtg_set_config(struct sti_vtg *vtg,
0293         const struct drm_display_mode *mode)
0294 {
0295     /* write configuration */
0296     vtg_set_mode(vtg, VTG_MODE_MASTER, vtg->sync_params, mode);
0297
0298     vtg_reset(vtg);
0299
0300     vtg_enable_irq(vtg);
0301 }
0302
0303 /**
0304  * sti_vtg_get_line_number
0305  *
0306  * @mode: display mode to be used
0307  * @y:    line
0308  *
0309  * Return the line number according to the display mode taking
0310  * into account the Sync and Back Porch information.
0311  * Video frame line numbers start at 1, y starts at 0.
0312  * In interlaced modes the start line is the field line number of the odd
0313  * field, but y is still defined as a progressive frame.
0314  */
0315 u32 sti_vtg_get_line_number(struct drm_display_mode mode, int y)
0316 {
0317     u32 start_line = mode.vtotal - mode.vsync_start + 1;
0318
0319     if (mode.flags & DRM_MODE_FLAG_INTERLACE)
0320         start_line *= 2;
0321
0322     return start_line + y;
0323 }
0324
0325 /**
0326  * sti_vtg_get_pixel_number
0327  *
0328  * @mode: display mode to be used
0329  * @x:    row
0330  *
0331  * Return the pixel number according to the display mode taking
0332  * into account the Sync and Back Porch information.
0333  * Pixels are counted from 0.
0334  */
0335 u32 sti_vtg_get_pixel_number(struct drm_display_mode mode, int x)
0336 {
0337     return mode.htotal - mode.hsync_start + x;
0338 }
0339
0340 int sti_vtg_register_client(struct sti_vtg *vtg, struct notifier_block *nb,
0341                 struct drm_crtc *crtc)
0342 {
0343     vtg->crtc = crtc;
0344     return raw_notifier_chain_register(&vtg->notifier_list, nb);
0345 }
0346
0347 int sti_vtg_unregister_client(struct sti_vtg *vtg, struct notifier_block *nb)
0348 {
0349     return raw_notifier_chain_unregister(&vtg->notifier_list, nb);
0350 }
0351
0352 static irqreturn_t vtg_irq_thread(int irq, void *arg)
0353 {
0354     struct sti_vtg *vtg = arg;
0355     u32 event;
0356
0357     event = (vtg->irq_status & VTG_IRQ_TOP) ?
0358         VTG_TOP_FIELD_EVENT : VTG_BOTTOM_FIELD_EVENT;
0359
0360     raw_notifier_call_chain(&vtg->notifier_list, event, vtg->crtc);
0361
0362     return IRQ_HANDLED;
0363 }
0364
0365 static irqreturn_t vtg_irq(int irq, void *arg)
0366 {
0367     struct sti_vtg *vtg = arg;
0368
0369     vtg->irq_status = readl(vtg->regs + VTG_HOST_ITS);
0370
0371     writel(vtg->irq_status, vtg->regs + VTG_HOST_ITS_BCLR);
0372
0373     /* force sync bus write */
0374     readl(vtg->regs + VTG_HOST_ITS);
0375
0376     return IRQ_WAKE_THREAD;
0377 }
0378
0379 static int vtg_probe(struct platform_device *pdev)
0380 {
0381     struct device *dev = &pdev->dev;
0382     struct sti_vtg *vtg;
0383     struct resource *res;
0384     int ret;
0385
0386     vtg = devm_kzalloc(dev, sizeof(*vtg), GFP_KERNEL);
0387     if (!vtg)
0388         return -ENOMEM;
0389
0390     /* Get Memory ressources */
0391     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
0392     if (!res) {
0393         DRM_ERROR("Get memory resource failed\n");
0394         return -ENOMEM;
0395     }
0396     vtg->regs = devm_ioremap(dev, res->start, resource_size(res));
0397     if (!vtg->regs) {
0398         DRM_ERROR("failed to remap I/O memory\n");
0399         return -ENOMEM;
0400     }
0401
0402     vtg->irq = platform_get_irq(pdev, 0);
0403     if (vtg->irq < 0) {
0404         DRM_ERROR("Failed to get VTG interrupt\n");
0405         return vtg->irq;
0406     }
0407
0408     RAW_INIT_NOTIFIER_HEAD(&vtg->notifier_list);
0409
0410     ret = devm_request_threaded_irq(dev, vtg->irq, vtg_irq,
0411                     vtg_irq_thread, IRQF_ONESHOT,
0412                     dev_name(dev), vtg);
0413     if (ret < 0) {
0414         DRM_ERROR("Failed to register VTG interrupt\n");
0415         return ret;
0416     }
0417
0418     platform_set_drvdata(pdev, vtg);
0419
0420     DRM_INFO("%s %s\n", __func__, dev_name(dev));
0421
0422     return 0;
0423 }
0424
0425 static const struct of_device_id vtg_of_match[] = {
0426     { .compatible = "st,vtg", },
0427     { /* sentinel */ }
0428 };
0429 MODULE_DEVICE_TABLE(of, vtg_of_match);
0430
0431 struct platform_driver sti_vtg_driver = {
0432     .driver = {
0433         .name = "sti-vtg",
0434         .owner = THIS_MODULE,
0435         .of_match_table = vtg_of_match,
0436     },
0437     .probe  = vtg_probe,
0438 };
0439
0440 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
0441 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
0442 MODULE_LICENSE("GPL");