drm/sti/sti_vid.c

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) STMicroelectronics SA 2014
0004  * Author: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
0005  */
0006 #include <linux/seq_file.h>
0007
0008 #include <drm/drm_debugfs.h>
0009 #include <drm/drm_file.h>
0010 #include <drm/drm_print.h>
0011
0012 #include "sti_plane.h"
0013 #include "sti_vid.h"
0014 #include "sti_vtg.h"
0015
0016 /* Registers */
0017 #define VID_CTL                 0x00
0018 #define VID_ALP                 0x04
0019 #define VID_CLF                 0x08
0020 #define VID_VPO                 0x0C
0021 #define VID_VPS                 0x10
0022 #define VID_KEY1                0x28
0023 #define VID_KEY2                0x2C
0024 #define VID_MPR0                0x30
0025 #define VID_MPR1                0x34
0026 #define VID_MPR2                0x38
0027 #define VID_MPR3                0x3C
0028 #define VID_MST                 0x68
0029 #define VID_BC                  0x70
0030 #define VID_TINT                0x74
0031 #define VID_CSAT                0x78
0032
0033 /* Registers values */
0034 #define VID_CTL_IGNORE          (BIT(31) | BIT(30))
0035 #define VID_CTL_PSI_ENABLE      (BIT(2) | BIT(1) | BIT(0))
0036 #define VID_ALP_OPAQUE          0x00000080
0037 #define VID_BC_DFLT             0x00008000
0038 #define VID_TINT_DFLT           0x00000000
0039 #define VID_CSAT_DFLT           0x00000080
0040 /* YCbCr to RGB BT709:
0041  * R = Y+1.5391Cr
0042  * G = Y-0.4590Cr-0.1826Cb
0043  * B = Y+1.8125Cb */
0044 #define VID_MPR0_BT709          0x0A800000
0045 #define VID_MPR1_BT709          0x0AC50000
0046 #define VID_MPR2_BT709          0x07150545
0047 #define VID_MPR3_BT709          0x00000AE8
0048 /* YCbCr to RGB BT709:
0049  * R = Y+1.3711Cr
0050  * G = Y-0.6992Cr-0.3359Cb
0051  * B = Y+1.7344Cb
0052  */
0053 #define VID_MPR0_BT601          0x0A800000
0054 #define VID_MPR1_BT601          0x0AAF0000
0055 #define VID_MPR2_BT601          0x094E0754
0056 #define VID_MPR3_BT601          0x00000ADD
0057
0058 #define VID_MIN_HD_HEIGHT       720
0059
0060 #define DBGFS_DUMP(reg) seq_printf(s, "\n  %-25s 0x%08X", #reg, \
0061                    readl(vid->regs + reg))
0062
0063 static void vid_dbg_ctl(struct seq_file *s, int val)
0064 {
0065     val = val >> 30;
0066     seq_putc(s, '\t');
0067
0068     if (!(val & 1))
0069         seq_puts(s, "NOT ");
0070     seq_puts(s, "ignored on main mixer - ");
0071
0072     if (!(val & 2))
0073         seq_puts(s, "NOT ");
0074     seq_puts(s, "ignored on aux mixer");
0075 }
0076
0077 static void vid_dbg_vpo(struct seq_file *s, int val)
0078 {
0079     seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0x0FFF, (val >> 16) & 0x0FFF);
0080 }
0081
0082 static void vid_dbg_vps(struct seq_file *s, int val)
0083 {
0084     seq_printf(s, "\txds:%4d\tyds:%4d", val & 0x0FFF, (val >> 16) & 0x0FFF);
0085 }
0086
0087 static void vid_dbg_mst(struct seq_file *s, int val)
0088 {
0089     if (val & 1)
0090         seq_puts(s, "\tBUFFER UNDERFLOW!");
0091 }
0092
0093 static int vid_dbg_show(struct seq_file *s, void *arg)
0094 {
0095     struct drm_info_node *node = s->private;
0096     struct sti_vid *vid = (struct sti_vid *)node->info_ent->data;
0097
0098     seq_printf(s, "VID: (vaddr= 0x%p)", vid->regs);
0099
0100     DBGFS_DUMP(VID_CTL);
0101     vid_dbg_ctl(s, readl(vid->regs + VID_CTL));
0102     DBGFS_DUMP(VID_ALP);
0103     DBGFS_DUMP(VID_CLF);
0104     DBGFS_DUMP(VID_VPO);
0105     vid_dbg_vpo(s, readl(vid->regs + VID_VPO));
0106     DBGFS_DUMP(VID_VPS);
0107     vid_dbg_vps(s, readl(vid->regs + VID_VPS));
0108     DBGFS_DUMP(VID_KEY1);
0109     DBGFS_DUMP(VID_KEY2);
0110     DBGFS_DUMP(VID_MPR0);
0111     DBGFS_DUMP(VID_MPR1);
0112     DBGFS_DUMP(VID_MPR2);
0113     DBGFS_DUMP(VID_MPR3);
0114     DBGFS_DUMP(VID_MST);
0115     vid_dbg_mst(s, readl(vid->regs + VID_MST));
0116     DBGFS_DUMP(VID_BC);
0117     DBGFS_DUMP(VID_TINT);
0118     DBGFS_DUMP(VID_CSAT);
0119     seq_putc(s, '\n');
0120     return 0;
0121 }
0122
0123 static struct drm_info_list vid_debugfs_files[] = {
0124     { "vid", vid_dbg_show, 0, NULL },
0125 };
0126
0127 void vid_debugfs_init(struct sti_vid *vid, struct drm_minor *minor)
0128 {
0129     unsigned int i;
0130
0131     for (i = 0; i < ARRAY_SIZE(vid_debugfs_files); i++)
0132         vid_debugfs_files[i].data = vid;
0133
0134     drm_debugfs_create_files(vid_debugfs_files,
0135                  ARRAY_SIZE(vid_debugfs_files),
0136                  minor->debugfs_root, minor);
0137 }
0138
0139 void sti_vid_commit(struct sti_vid *vid,
0140             struct drm_plane_state *state)
0141 {
0142     struct drm_crtc *crtc = state->crtc;
0143     struct drm_display_mode *mode = &crtc->mode;
0144     int dst_x = state->crtc_x;
0145     int dst_y = state->crtc_y;
0146     int dst_w = clamp_val(state->crtc_w, 0, mode->hdisplay - dst_x);
0147     int dst_h = clamp_val(state->crtc_h, 0, mode->vdisplay - dst_y);
0148     int src_h = state->src_h >> 16;
0149     u32 val, ydo, xdo, yds, xds;
0150
0151     /* Input / output size
0152      * Align to upper even value */
0153     dst_w = ALIGN(dst_w, 2);
0154     dst_h = ALIGN(dst_h, 2);
0155
0156     /* Unmask */
0157     val = readl(vid->regs + VID_CTL);
0158     val &= ~VID_CTL_IGNORE;
0159     writel(val, vid->regs + VID_CTL);
0160
0161     ydo = sti_vtg_get_line_number(*mode, dst_y);
0162     yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1);
0163     xdo = sti_vtg_get_pixel_number(*mode, dst_x);
0164     xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1);
0165
0166     writel((ydo << 16) | xdo, vid->regs + VID_VPO);
0167     writel((yds << 16) | xds, vid->regs + VID_VPS);
0168
0169     /* Color conversion parameters */
0170     if (src_h >= VID_MIN_HD_HEIGHT) {
0171         writel(VID_MPR0_BT709, vid->regs + VID_MPR0);
0172         writel(VID_MPR1_BT709, vid->regs + VID_MPR1);
0173         writel(VID_MPR2_BT709, vid->regs + VID_MPR2);
0174         writel(VID_MPR3_BT709, vid->regs + VID_MPR3);
0175     } else {
0176         writel(VID_MPR0_BT601, vid->regs + VID_MPR0);
0177         writel(VID_MPR1_BT601, vid->regs + VID_MPR1);
0178         writel(VID_MPR2_BT601, vid->regs + VID_MPR2);
0179         writel(VID_MPR3_BT601, vid->regs + VID_MPR3);
0180     }
0181 }
0182
0183 void sti_vid_disable(struct sti_vid *vid)
0184 {
0185     u32 val;
0186
0187     /* Mask */
0188     val = readl(vid->regs + VID_CTL);
0189     val |= VID_CTL_IGNORE;
0190     writel(val, vid->regs + VID_CTL);
0191 }
0192
0193 static void sti_vid_init(struct sti_vid *vid)
0194 {
0195     /* Enable PSI, Mask layer */
0196     writel(VID_CTL_PSI_ENABLE | VID_CTL_IGNORE, vid->regs + VID_CTL);
0197
0198     /* Opaque */
0199     writel(VID_ALP_OPAQUE, vid->regs + VID_ALP);
0200
0201     /* Brightness, contrast, tint, saturation */
0202     writel(VID_BC_DFLT, vid->regs + VID_BC);
0203     writel(VID_TINT_DFLT, vid->regs + VID_TINT);
0204     writel(VID_CSAT_DFLT, vid->regs + VID_CSAT);
0205 }
0206
0207 struct sti_vid *sti_vid_create(struct device *dev, struct drm_device *drm_dev,
0208                    int id, void __iomem *baseaddr)
0209 {
0210     struct sti_vid *vid;
0211
0212     vid = devm_kzalloc(dev, sizeof(*vid), GFP_KERNEL);
0213     if (!vid) {
0214         DRM_ERROR("Failed to allocate memory for VID\n");
0215         return NULL;
0216     }
0217
0218     vid->dev = dev;
0219     vid->regs = baseaddr;
0220     vid->id = id;
0221
0222     sti_vid_init(vid);
0223
0224     return vid;
0225 }