Back to home page

OSCL-LXR
 
 

     

0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) STMicroelectronics SA 2014
0004  * Authors: Fabien Dessenne <fabien.dessenne@st.com> for STMicroelectronics.
0005  */
0006 
0007 #include <linux/component.h>
0008 #include <linux/delay.h>
0009 #include <linux/dma-mapping.h>
0010 #include <linux/firmware.h>
0011 #include <linux/io.h>
0012 #include <linux/module.h>
0013 #include <linux/of.h>
0014 #include <linux/reset.h>
0015 #include <linux/seq_file.h>
0016 
0017 #include <drm/drm_atomic.h>
0018 #include <drm/drm_device.h>
0019 #include <drm/drm_fb_cma_helper.h>
0020 #include <drm/drm_fourcc.h>
0021 #include <drm/drm_framebuffer.h>
0022 #include <drm/drm_gem_cma_helper.h>
0023 
0024 #include "sti_compositor.h"
0025 #include "sti_drv.h"
0026 #include "sti_hqvdp_lut.h"
0027 #include "sti_plane.h"
0028 #include "sti_vtg.h"
0029 
0030 /* Firmware name */
0031 #define HQVDP_FMW_NAME          "hqvdp-stih407.bin"
0032 
0033 /* Regs address */
0034 #define HQVDP_DMEM              0x00000000               /* 0x00000000 */
0035 #define HQVDP_PMEM              0x00040000               /* 0x00040000 */
0036 #define HQVDP_RD_PLUG           0x000E0000               /* 0x000E0000 */
0037 #define HQVDP_RD_PLUG_CONTROL   (HQVDP_RD_PLUG + 0x1000) /* 0x000E1000 */
0038 #define HQVDP_RD_PLUG_PAGE_SIZE (HQVDP_RD_PLUG + 0x1004) /* 0x000E1004 */
0039 #define HQVDP_RD_PLUG_MIN_OPC   (HQVDP_RD_PLUG + 0x1008) /* 0x000E1008 */
0040 #define HQVDP_RD_PLUG_MAX_OPC   (HQVDP_RD_PLUG + 0x100C) /* 0x000E100C */
0041 #define HQVDP_RD_PLUG_MAX_CHK   (HQVDP_RD_PLUG + 0x1010) /* 0x000E1010 */
0042 #define HQVDP_RD_PLUG_MAX_MSG   (HQVDP_RD_PLUG + 0x1014) /* 0x000E1014 */
0043 #define HQVDP_RD_PLUG_MIN_SPACE (HQVDP_RD_PLUG + 0x1018) /* 0x000E1018 */
0044 #define HQVDP_WR_PLUG           0x000E2000               /* 0x000E2000 */
0045 #define HQVDP_WR_PLUG_CONTROL   (HQVDP_WR_PLUG + 0x1000) /* 0x000E3000 */
0046 #define HQVDP_WR_PLUG_PAGE_SIZE (HQVDP_WR_PLUG + 0x1004) /* 0x000E3004 */
0047 #define HQVDP_WR_PLUG_MIN_OPC   (HQVDP_WR_PLUG + 0x1008) /* 0x000E3008 */
0048 #define HQVDP_WR_PLUG_MAX_OPC   (HQVDP_WR_PLUG + 0x100C) /* 0x000E300C */
0049 #define HQVDP_WR_PLUG_MAX_CHK   (HQVDP_WR_PLUG + 0x1010) /* 0x000E3010 */
0050 #define HQVDP_WR_PLUG_MAX_MSG   (HQVDP_WR_PLUG + 0x1014) /* 0x000E3014 */
0051 #define HQVDP_WR_PLUG_MIN_SPACE (HQVDP_WR_PLUG + 0x1018) /* 0x000E3018 */
0052 #define HQVDP_MBX               0x000E4000               /* 0x000E4000 */
0053 #define HQVDP_MBX_IRQ_TO_XP70   (HQVDP_MBX + 0x0000)     /* 0x000E4000 */
0054 #define HQVDP_MBX_INFO_HOST     (HQVDP_MBX + 0x0004)     /* 0x000E4004 */
0055 #define HQVDP_MBX_IRQ_TO_HOST   (HQVDP_MBX + 0x0008)     /* 0x000E4008 */
0056 #define HQVDP_MBX_INFO_XP70     (HQVDP_MBX + 0x000C)     /* 0x000E400C */
0057 #define HQVDP_MBX_SW_RESET_CTRL (HQVDP_MBX + 0x0010)     /* 0x000E4010 */
0058 #define HQVDP_MBX_STARTUP_CTRL1 (HQVDP_MBX + 0x0014)     /* 0x000E4014 */
0059 #define HQVDP_MBX_STARTUP_CTRL2 (HQVDP_MBX + 0x0018)     /* 0x000E4018 */
0060 #define HQVDP_MBX_GP_STATUS     (HQVDP_MBX + 0x001C)     /* 0x000E401C */
0061 #define HQVDP_MBX_NEXT_CMD      (HQVDP_MBX + 0x0020)     /* 0x000E4020 */
0062 #define HQVDP_MBX_CURRENT_CMD   (HQVDP_MBX + 0x0024)     /* 0x000E4024 */
0063 #define HQVDP_MBX_SOFT_VSYNC    (HQVDP_MBX + 0x0028)     /* 0x000E4028 */
0064 
0065 /* Plugs config */
0066 #define PLUG_CONTROL_ENABLE     0x00000001
0067 #define PLUG_PAGE_SIZE_256      0x00000002
0068 #define PLUG_MIN_OPC_8          0x00000003
0069 #define PLUG_MAX_OPC_64         0x00000006
0070 #define PLUG_MAX_CHK_2X         0x00000001
0071 #define PLUG_MAX_MSG_1X         0x00000000
0072 #define PLUG_MIN_SPACE_1        0x00000000
0073 
0074 /* SW reset CTRL */
0075 #define SW_RESET_CTRL_FULL      BIT(0)
0076 #define SW_RESET_CTRL_CORE      BIT(1)
0077 
0078 /* Startup ctrl 1 */
0079 #define STARTUP_CTRL1_RST_DONE  BIT(0)
0080 #define STARTUP_CTRL1_AUTH_IDLE BIT(2)
0081 
0082 /* Startup ctrl 2 */
0083 #define STARTUP_CTRL2_FETCH_EN  BIT(1)
0084 
0085 /* Info xP70 */
0086 #define INFO_XP70_FW_READY      BIT(15)
0087 #define INFO_XP70_FW_PROCESSING BIT(14)
0088 #define INFO_XP70_FW_INITQUEUES BIT(13)
0089 
0090 /* SOFT_VSYNC */
0091 #define SOFT_VSYNC_HW           0x00000000
0092 #define SOFT_VSYNC_SW_CMD       0x00000001
0093 #define SOFT_VSYNC_SW_CTRL_IRQ  0x00000003
0094 
0095 /* Reset & boot poll config */
0096 #define POLL_MAX_ATTEMPT        50
0097 #define POLL_DELAY_MS           20
0098 
0099 #define SCALE_FACTOR            8192
0100 #define SCALE_MAX_FOR_LEG_LUT_F 4096
0101 #define SCALE_MAX_FOR_LEG_LUT_E 4915
0102 #define SCALE_MAX_FOR_LEG_LUT_D 6654
0103 #define SCALE_MAX_FOR_LEG_LUT_C 8192
0104 
0105 enum sti_hvsrc_orient {
0106     HVSRC_HORI,
0107     HVSRC_VERT
0108 };
0109 
0110 /* Command structures */
0111 struct sti_hqvdp_top {
0112     u32 config;
0113     u32 mem_format;
0114     u32 current_luma;
0115     u32 current_enh_luma;
0116     u32 current_right_luma;
0117     u32 current_enh_right_luma;
0118     u32 current_chroma;
0119     u32 current_enh_chroma;
0120     u32 current_right_chroma;
0121     u32 current_enh_right_chroma;
0122     u32 output_luma;
0123     u32 output_chroma;
0124     u32 luma_src_pitch;
0125     u32 luma_enh_src_pitch;
0126     u32 luma_right_src_pitch;
0127     u32 luma_enh_right_src_pitch;
0128     u32 chroma_src_pitch;
0129     u32 chroma_enh_src_pitch;
0130     u32 chroma_right_src_pitch;
0131     u32 chroma_enh_right_src_pitch;
0132     u32 luma_processed_pitch;
0133     u32 chroma_processed_pitch;
0134     u32 input_frame_size;
0135     u32 input_viewport_ori;
0136     u32 input_viewport_ori_right;
0137     u32 input_viewport_size;
0138     u32 left_view_border_width;
0139     u32 right_view_border_width;
0140     u32 left_view_3d_offset_width;
0141     u32 right_view_3d_offset_width;
0142     u32 side_stripe_color;
0143     u32 crc_reset_ctrl;
0144 };
0145 
0146 /* Configs for interlaced : no IT, no pass thru, 3 fields */
0147 #define TOP_CONFIG_INTER_BTM            0x00000000
0148 #define TOP_CONFIG_INTER_TOP            0x00000002
0149 
0150 /* Config for progressive : no IT, no pass thru, 3 fields */
0151 #define TOP_CONFIG_PROGRESSIVE          0x00000001
0152 
0153 /* Default MemFormat: in=420_raster_dual out=444_raster;opaque Mem2Tv mode */
0154 #define TOP_MEM_FORMAT_DFLT             0x00018060
0155 
0156 /* Min/Max size */
0157 #define MAX_WIDTH                       0x1FFF
0158 #define MAX_HEIGHT                      0x0FFF
0159 #define MIN_WIDTH                       0x0030
0160 #define MIN_HEIGHT                      0x0010
0161 
0162 struct sti_hqvdp_vc1re {
0163     u32 ctrl_prv_csdi;
0164     u32 ctrl_cur_csdi;
0165     u32 ctrl_nxt_csdi;
0166     u32 ctrl_cur_fmd;
0167     u32 ctrl_nxt_fmd;
0168 };
0169 
0170 struct sti_hqvdp_fmd {
0171     u32 config;
0172     u32 viewport_ori;
0173     u32 viewport_size;
0174     u32 next_next_luma;
0175     u32 next_next_right_luma;
0176     u32 next_next_next_luma;
0177     u32 next_next_next_right_luma;
0178     u32 threshold_scd;
0179     u32 threshold_rfd;
0180     u32 threshold_move;
0181     u32 threshold_cfd;
0182 };
0183 
0184 struct sti_hqvdp_csdi {
0185     u32 config;
0186     u32 config2;
0187     u32 dcdi_config;
0188     u32 prev_luma;
0189     u32 prev_enh_luma;
0190     u32 prev_right_luma;
0191     u32 prev_enh_right_luma;
0192     u32 next_luma;
0193     u32 next_enh_luma;
0194     u32 next_right_luma;
0195     u32 next_enh_right_luma;
0196     u32 prev_chroma;
0197     u32 prev_enh_chroma;
0198     u32 prev_right_chroma;
0199     u32 prev_enh_right_chroma;
0200     u32 next_chroma;
0201     u32 next_enh_chroma;
0202     u32 next_right_chroma;
0203     u32 next_enh_right_chroma;
0204     u32 prev_motion;
0205     u32 prev_right_motion;
0206     u32 cur_motion;
0207     u32 cur_right_motion;
0208     u32 next_motion;
0209     u32 next_right_motion;
0210 };
0211 
0212 /* Config for progressive: by pass */
0213 #define CSDI_CONFIG_PROG                0x00000000
0214 /* Config for directional deinterlacing without motion */
0215 #define CSDI_CONFIG_INTER_DIR           0x00000016
0216 /* Additional configs for fader, blender, motion,... deinterlace algorithms */
0217 #define CSDI_CONFIG2_DFLT               0x000001B3
0218 #define CSDI_DCDI_CONFIG_DFLT           0x00203803
0219 
0220 struct sti_hqvdp_hvsrc {
0221     u32 hor_panoramic_ctrl;
0222     u32 output_picture_size;
0223     u32 init_horizontal;
0224     u32 init_vertical;
0225     u32 param_ctrl;
0226     u32 yh_coef[NB_COEF];
0227     u32 ch_coef[NB_COEF];
0228     u32 yv_coef[NB_COEF];
0229     u32 cv_coef[NB_COEF];
0230     u32 hori_shift;
0231     u32 vert_shift;
0232 };
0233 
0234 /* Default ParamCtrl: all controls enabled */
0235 #define HVSRC_PARAM_CTRL_DFLT           0xFFFFFFFF
0236 
0237 struct sti_hqvdp_iqi {
0238     u32 config;
0239     u32 demo_wind_size;
0240     u32 pk_config;
0241     u32 coeff0_coeff1;
0242     u32 coeff2_coeff3;
0243     u32 coeff4;
0244     u32 pk_lut;
0245     u32 pk_gain;
0246     u32 pk_coring_level;
0247     u32 cti_config;
0248     u32 le_config;
0249     u32 le_lut[64];
0250     u32 con_bri;
0251     u32 sat_gain;
0252     u32 pxf_conf;
0253     u32 default_color;
0254 };
0255 
0256 /* Default Config : IQI bypassed */
0257 #define IQI_CONFIG_DFLT                 0x00000001
0258 /* Default Contrast & Brightness gain = 256 */
0259 #define IQI_CON_BRI_DFLT                0x00000100
0260 /* Default Saturation gain = 256 */
0261 #define IQI_SAT_GAIN_DFLT               0x00000100
0262 /* Default PxfConf : P2I bypassed */
0263 #define IQI_PXF_CONF_DFLT               0x00000001
0264 
0265 struct sti_hqvdp_top_status {
0266     u32 processing_time;
0267     u32 input_y_crc;
0268     u32 input_uv_crc;
0269 };
0270 
0271 struct sti_hqvdp_fmd_status {
0272     u32 fmd_repeat_move_status;
0273     u32 fmd_scene_count_status;
0274     u32 cfd_sum;
0275     u32 field_sum;
0276     u32 next_y_fmd_crc;
0277     u32 next_next_y_fmd_crc;
0278     u32 next_next_next_y_fmd_crc;
0279 };
0280 
0281 struct sti_hqvdp_csdi_status {
0282     u32 prev_y_csdi_crc;
0283     u32 cur_y_csdi_crc;
0284     u32 next_y_csdi_crc;
0285     u32 prev_uv_csdi_crc;
0286     u32 cur_uv_csdi_crc;
0287     u32 next_uv_csdi_crc;
0288     u32 y_csdi_crc;
0289     u32 uv_csdi_crc;
0290     u32 uv_cup_crc;
0291     u32 mot_csdi_crc;
0292     u32 mot_cur_csdi_crc;
0293     u32 mot_prev_csdi_crc;
0294 };
0295 
0296 struct sti_hqvdp_hvsrc_status {
0297     u32 y_hvsrc_crc;
0298     u32 u_hvsrc_crc;
0299     u32 v_hvsrc_crc;
0300 };
0301 
0302 struct sti_hqvdp_iqi_status {
0303     u32 pxf_it_status;
0304     u32 y_iqi_crc;
0305     u32 u_iqi_crc;
0306     u32 v_iqi_crc;
0307 };
0308 
0309 /* Main commands. We use 2 commands one being processed by the firmware, one
0310  * ready to be fetched upon next Vsync*/
0311 #define NB_VDP_CMD  2
0312 
0313 struct sti_hqvdp_cmd {
0314     struct sti_hqvdp_top top;
0315     struct sti_hqvdp_vc1re vc1re;
0316     struct sti_hqvdp_fmd fmd;
0317     struct sti_hqvdp_csdi csdi;
0318     struct sti_hqvdp_hvsrc hvsrc;
0319     struct sti_hqvdp_iqi iqi;
0320     struct sti_hqvdp_top_status top_status;
0321     struct sti_hqvdp_fmd_status fmd_status;
0322     struct sti_hqvdp_csdi_status csdi_status;
0323     struct sti_hqvdp_hvsrc_status hvsrc_status;
0324     struct sti_hqvdp_iqi_status iqi_status;
0325 };
0326 
0327 /*
0328  * STI HQVDP structure
0329  *
0330  * @dev:               driver device
0331  * @drm_dev:           the drm device
0332  * @regs:              registers
0333  * @plane:             plane structure for hqvdp it self
0334  * @clk:               IP clock
0335  * @clk_pix_main:      pix main clock
0336  * @reset:             reset control
0337  * @vtg_nb:            notifier to handle VTG Vsync
0338  * @btm_field_pending: is there any bottom field (interlaced frame) to display
0339  * @hqvdp_cmd:         buffer of commands
0340  * @hqvdp_cmd_paddr:   physical address of hqvdp_cmd
0341  * @vtg:               vtg for main data path
0342  * @xp70_initialized:  true if xp70 is already initialized
0343  * @vtg_registered:    true if registered to VTG
0344  */
0345 struct sti_hqvdp {
0346     struct device *dev;
0347     struct drm_device *drm_dev;
0348     void __iomem *regs;
0349     struct sti_plane plane;
0350     struct clk *clk;
0351     struct clk *clk_pix_main;
0352     struct reset_control *reset;
0353     struct notifier_block vtg_nb;
0354     bool btm_field_pending;
0355     void *hqvdp_cmd;
0356     u32 hqvdp_cmd_paddr;
0357     struct sti_vtg *vtg;
0358     bool xp70_initialized;
0359     bool vtg_registered;
0360 };
0361 
0362 #define to_sti_hqvdp(x) container_of(x, struct sti_hqvdp, plane)
0363 
0364 static const uint32_t hqvdp_supported_formats[] = {
0365     DRM_FORMAT_NV12,
0366 };
0367 
0368 /**
0369  * sti_hqvdp_get_free_cmd
0370  * @hqvdp: hqvdp structure
0371  *
0372  * Look for a hqvdp_cmd that is not being used (or about to be used) by the FW.
0373  *
0374  * RETURNS:
0375  * the offset of the command to be used.
0376  * -1 in error cases
0377  */
0378 static int sti_hqvdp_get_free_cmd(struct sti_hqvdp *hqvdp)
0379 {
0380     u32 curr_cmd, next_cmd;
0381     u32 cmd = hqvdp->hqvdp_cmd_paddr;
0382     int i;
0383 
0384     curr_cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD);
0385     next_cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD);
0386 
0387     for (i = 0; i < NB_VDP_CMD; i++) {
0388         if ((cmd != curr_cmd) && (cmd != next_cmd))
0389             return i * sizeof(struct sti_hqvdp_cmd);
0390         cmd += sizeof(struct sti_hqvdp_cmd);
0391     }
0392 
0393     return -1;
0394 }
0395 
0396 /**
0397  * sti_hqvdp_get_curr_cmd
0398  * @hqvdp: hqvdp structure
0399  *
0400  * Look for the hqvdp_cmd that is being used by the FW.
0401  *
0402  * RETURNS:
0403  *  the offset of the command to be used.
0404  * -1 in error cases
0405  */
0406 static int sti_hqvdp_get_curr_cmd(struct sti_hqvdp *hqvdp)
0407 {
0408     u32 curr_cmd;
0409     u32 cmd = hqvdp->hqvdp_cmd_paddr;
0410     unsigned int i;
0411 
0412     curr_cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD);
0413 
0414     for (i = 0; i < NB_VDP_CMD; i++) {
0415         if (cmd == curr_cmd)
0416             return i * sizeof(struct sti_hqvdp_cmd);
0417 
0418         cmd += sizeof(struct sti_hqvdp_cmd);
0419     }
0420 
0421     return -1;
0422 }
0423 
0424 /**
0425  * sti_hqvdp_get_next_cmd
0426  * @hqvdp: hqvdp structure
0427  *
0428  * Look for the next hqvdp_cmd that will be used by the FW.
0429  *
0430  * RETURNS:
0431  *  the offset of the next command that will be used.
0432  * -1 in error cases
0433  */
0434 static int sti_hqvdp_get_next_cmd(struct sti_hqvdp *hqvdp)
0435 {
0436     int next_cmd;
0437     dma_addr_t cmd = hqvdp->hqvdp_cmd_paddr;
0438     unsigned int i;
0439 
0440     next_cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD);
0441 
0442     for (i = 0; i < NB_VDP_CMD; i++) {
0443         if (cmd == next_cmd)
0444             return i * sizeof(struct sti_hqvdp_cmd);
0445 
0446         cmd += sizeof(struct sti_hqvdp_cmd);
0447     }
0448 
0449     return -1;
0450 }
0451 
0452 #define DBGFS_DUMP(reg) seq_printf(s, "\n  %-25s 0x%08X", #reg, \
0453                    readl(hqvdp->regs + reg))
0454 
0455 static const char *hqvdp_dbg_get_lut(u32 *coef)
0456 {
0457     if (!memcmp(coef, coef_lut_a_legacy, 16))
0458         return "LUT A";
0459     if (!memcmp(coef, coef_lut_b, 16))
0460         return "LUT B";
0461     if (!memcmp(coef, coef_lut_c_y_legacy, 16))
0462         return "LUT C Y";
0463     if (!memcmp(coef, coef_lut_c_c_legacy, 16))
0464         return "LUT C C";
0465     if (!memcmp(coef, coef_lut_d_y_legacy, 16))
0466         return "LUT D Y";
0467     if (!memcmp(coef, coef_lut_d_c_legacy, 16))
0468         return "LUT D C";
0469     if (!memcmp(coef, coef_lut_e_y_legacy, 16))
0470         return "LUT E Y";
0471     if (!memcmp(coef, coef_lut_e_c_legacy, 16))
0472         return "LUT E C";
0473     if (!memcmp(coef, coef_lut_f_y_legacy, 16))
0474         return "LUT F Y";
0475     if (!memcmp(coef, coef_lut_f_c_legacy, 16))
0476         return "LUT F C";
0477     return "<UNKNOWN>";
0478 }
0479 
0480 static void hqvdp_dbg_dump_cmd(struct seq_file *s, struct sti_hqvdp_cmd *c)
0481 {
0482     int src_w, src_h, dst_w, dst_h;
0483 
0484     seq_puts(s, "\n\tTOP:");
0485     seq_printf(s, "\n\t %-20s 0x%08X", "Config", c->top.config);
0486     switch (c->top.config) {
0487     case TOP_CONFIG_PROGRESSIVE:
0488         seq_puts(s, "\tProgressive");
0489         break;
0490     case TOP_CONFIG_INTER_TOP:
0491         seq_puts(s, "\tInterlaced, top field");
0492         break;
0493     case TOP_CONFIG_INTER_BTM:
0494         seq_puts(s, "\tInterlaced, bottom field");
0495         break;
0496     default:
0497         seq_puts(s, "\t<UNKNOWN>");
0498         break;
0499     }
0500 
0501     seq_printf(s, "\n\t %-20s 0x%08X", "MemFormat", c->top.mem_format);
0502     seq_printf(s, "\n\t %-20s 0x%08X", "CurrentY", c->top.current_luma);
0503     seq_printf(s, "\n\t %-20s 0x%08X", "CurrentC", c->top.current_chroma);
0504     seq_printf(s, "\n\t %-20s 0x%08X", "YSrcPitch", c->top.luma_src_pitch);
0505     seq_printf(s, "\n\t %-20s 0x%08X", "CSrcPitch",
0506            c->top.chroma_src_pitch);
0507     seq_printf(s, "\n\t %-20s 0x%08X", "InputFrameSize",
0508            c->top.input_frame_size);
0509     seq_printf(s, "\t%dx%d",
0510            c->top.input_frame_size & 0x0000FFFF,
0511            c->top.input_frame_size >> 16);
0512     seq_printf(s, "\n\t %-20s 0x%08X", "InputViewportSize",
0513            c->top.input_viewport_size);
0514     src_w = c->top.input_viewport_size & 0x0000FFFF;
0515     src_h = c->top.input_viewport_size >> 16;
0516     seq_printf(s, "\t%dx%d", src_w, src_h);
0517 
0518     seq_puts(s, "\n\tHVSRC:");
0519     seq_printf(s, "\n\t %-20s 0x%08X", "OutputPictureSize",
0520            c->hvsrc.output_picture_size);
0521     dst_w = c->hvsrc.output_picture_size & 0x0000FFFF;
0522     dst_h = c->hvsrc.output_picture_size >> 16;
0523     seq_printf(s, "\t%dx%d", dst_w, dst_h);
0524     seq_printf(s, "\n\t %-20s 0x%08X", "ParamCtrl", c->hvsrc.param_ctrl);
0525 
0526     seq_printf(s, "\n\t %-20s %s", "yh_coef",
0527            hqvdp_dbg_get_lut(c->hvsrc.yh_coef));
0528     seq_printf(s, "\n\t %-20s %s", "ch_coef",
0529            hqvdp_dbg_get_lut(c->hvsrc.ch_coef));
0530     seq_printf(s, "\n\t %-20s %s", "yv_coef",
0531            hqvdp_dbg_get_lut(c->hvsrc.yv_coef));
0532     seq_printf(s, "\n\t %-20s %s", "cv_coef",
0533            hqvdp_dbg_get_lut(c->hvsrc.cv_coef));
0534 
0535     seq_printf(s, "\n\t %-20s", "ScaleH");
0536     if (dst_w > src_w)
0537         seq_printf(s, " %d/1", dst_w / src_w);
0538     else
0539         seq_printf(s, " 1/%d", src_w / dst_w);
0540 
0541     seq_printf(s, "\n\t %-20s", "tScaleV");
0542     if (dst_h > src_h)
0543         seq_printf(s, " %d/1", dst_h / src_h);
0544     else
0545         seq_printf(s, " 1/%d", src_h / dst_h);
0546 
0547     seq_puts(s, "\n\tCSDI:");
0548     seq_printf(s, "\n\t %-20s 0x%08X\t", "Config", c->csdi.config);
0549     switch (c->csdi.config) {
0550     case CSDI_CONFIG_PROG:
0551         seq_puts(s, "Bypass");
0552         break;
0553     case CSDI_CONFIG_INTER_DIR:
0554         seq_puts(s, "Deinterlace, directional");
0555         break;
0556     default:
0557         seq_puts(s, "<UNKNOWN>");
0558         break;
0559     }
0560 
0561     seq_printf(s, "\n\t %-20s 0x%08X", "Config2", c->csdi.config2);
0562     seq_printf(s, "\n\t %-20s 0x%08X", "DcdiConfig", c->csdi.dcdi_config);
0563 }
0564 
0565 static int hqvdp_dbg_show(struct seq_file *s, void *data)
0566 {
0567     struct drm_info_node *node = s->private;
0568     struct sti_hqvdp *hqvdp = (struct sti_hqvdp *)node->info_ent->data;
0569     int cmd, cmd_offset, infoxp70;
0570     void *virt;
0571 
0572     seq_printf(s, "%s: (vaddr = 0x%p)",
0573            sti_plane_to_str(&hqvdp->plane), hqvdp->regs);
0574 
0575     DBGFS_DUMP(HQVDP_MBX_IRQ_TO_XP70);
0576     DBGFS_DUMP(HQVDP_MBX_INFO_HOST);
0577     DBGFS_DUMP(HQVDP_MBX_IRQ_TO_HOST);
0578     DBGFS_DUMP(HQVDP_MBX_INFO_XP70);
0579     infoxp70 = readl(hqvdp->regs + HQVDP_MBX_INFO_XP70);
0580     seq_puts(s, "\tFirmware state: ");
0581     if (infoxp70 & INFO_XP70_FW_READY)
0582         seq_puts(s, "idle and ready");
0583     else if (infoxp70 & INFO_XP70_FW_PROCESSING)
0584         seq_puts(s, "processing a picture");
0585     else if (infoxp70 & INFO_XP70_FW_INITQUEUES)
0586         seq_puts(s, "programming queues");
0587     else
0588         seq_puts(s, "NOT READY");
0589 
0590     DBGFS_DUMP(HQVDP_MBX_SW_RESET_CTRL);
0591     DBGFS_DUMP(HQVDP_MBX_STARTUP_CTRL1);
0592     if (readl(hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1)
0593                     & STARTUP_CTRL1_RST_DONE)
0594         seq_puts(s, "\tReset is done");
0595     else
0596         seq_puts(s, "\tReset is NOT done");
0597     DBGFS_DUMP(HQVDP_MBX_STARTUP_CTRL2);
0598     if (readl(hqvdp->regs + HQVDP_MBX_STARTUP_CTRL2)
0599                     & STARTUP_CTRL2_FETCH_EN)
0600         seq_puts(s, "\tFetch is enabled");
0601     else
0602         seq_puts(s, "\tFetch is NOT enabled");
0603     DBGFS_DUMP(HQVDP_MBX_GP_STATUS);
0604     DBGFS_DUMP(HQVDP_MBX_NEXT_CMD);
0605     DBGFS_DUMP(HQVDP_MBX_CURRENT_CMD);
0606     DBGFS_DUMP(HQVDP_MBX_SOFT_VSYNC);
0607     if (!(readl(hqvdp->regs + HQVDP_MBX_SOFT_VSYNC) & 3))
0608         seq_puts(s, "\tHW Vsync");
0609     else
0610         seq_puts(s, "\tSW Vsync ?!?!");
0611 
0612     /* Last command */
0613     cmd = readl(hqvdp->regs + HQVDP_MBX_CURRENT_CMD);
0614     cmd_offset = sti_hqvdp_get_curr_cmd(hqvdp);
0615     if (cmd_offset == -1) {
0616         seq_puts(s, "\n\n  Last command: unknown");
0617     } else {
0618         virt = hqvdp->hqvdp_cmd + cmd_offset;
0619         seq_printf(s, "\n\n  Last command: address @ 0x%x (0x%p)",
0620                cmd, virt);
0621         hqvdp_dbg_dump_cmd(s, (struct sti_hqvdp_cmd *)virt);
0622     }
0623 
0624     /* Next command */
0625     cmd = readl(hqvdp->regs + HQVDP_MBX_NEXT_CMD);
0626     cmd_offset = sti_hqvdp_get_next_cmd(hqvdp);
0627     if (cmd_offset == -1) {
0628         seq_puts(s, "\n\n  Next command: unknown");
0629     } else {
0630         virt = hqvdp->hqvdp_cmd + cmd_offset;
0631         seq_printf(s, "\n\n  Next command address: @ 0x%x (0x%p)",
0632                cmd, virt);
0633         hqvdp_dbg_dump_cmd(s, (struct sti_hqvdp_cmd *)virt);
0634     }
0635 
0636     seq_putc(s, '\n');
0637     return 0;
0638 }
0639 
0640 static struct drm_info_list hqvdp_debugfs_files[] = {
0641     { "hqvdp", hqvdp_dbg_show, 0, NULL },
0642 };
0643 
0644 static void hqvdp_debugfs_init(struct sti_hqvdp *hqvdp, struct drm_minor *minor)
0645 {
0646     unsigned int i;
0647 
0648     for (i = 0; i < ARRAY_SIZE(hqvdp_debugfs_files); i++)
0649         hqvdp_debugfs_files[i].data = hqvdp;
0650 
0651     drm_debugfs_create_files(hqvdp_debugfs_files,
0652                  ARRAY_SIZE(hqvdp_debugfs_files),
0653                  minor->debugfs_root, minor);
0654 }
0655 
0656 /**
0657  * sti_hqvdp_update_hvsrc
0658  * @orient: horizontal or vertical
0659  * @scale:  scaling/zoom factor
0660  * @hvsrc:  the structure containing the LUT coef
0661  *
0662  * Update the Y and C Lut coef, as well as the shift param
0663  *
0664  * RETURNS:
0665  * None.
0666  */
0667 static void sti_hqvdp_update_hvsrc(enum sti_hvsrc_orient orient, int scale,
0668         struct sti_hqvdp_hvsrc *hvsrc)
0669 {
0670     const int *coef_c, *coef_y;
0671     int shift_c, shift_y;
0672 
0673     /* Get the appropriate coef tables */
0674     if (scale < SCALE_MAX_FOR_LEG_LUT_F) {
0675         coef_y = coef_lut_f_y_legacy;
0676         coef_c = coef_lut_f_c_legacy;
0677         shift_y = SHIFT_LUT_F_Y_LEGACY;
0678         shift_c = SHIFT_LUT_F_C_LEGACY;
0679     } else if (scale < SCALE_MAX_FOR_LEG_LUT_E) {
0680         coef_y = coef_lut_e_y_legacy;
0681         coef_c = coef_lut_e_c_legacy;
0682         shift_y = SHIFT_LUT_E_Y_LEGACY;
0683         shift_c = SHIFT_LUT_E_C_LEGACY;
0684     } else if (scale < SCALE_MAX_FOR_LEG_LUT_D) {
0685         coef_y = coef_lut_d_y_legacy;
0686         coef_c = coef_lut_d_c_legacy;
0687         shift_y = SHIFT_LUT_D_Y_LEGACY;
0688         shift_c = SHIFT_LUT_D_C_LEGACY;
0689     } else if (scale < SCALE_MAX_FOR_LEG_LUT_C) {
0690         coef_y = coef_lut_c_y_legacy;
0691         coef_c = coef_lut_c_c_legacy;
0692         shift_y = SHIFT_LUT_C_Y_LEGACY;
0693         shift_c = SHIFT_LUT_C_C_LEGACY;
0694     } else if (scale == SCALE_MAX_FOR_LEG_LUT_C) {
0695         coef_y = coef_c = coef_lut_b;
0696         shift_y = shift_c = SHIFT_LUT_B;
0697     } else {
0698         coef_y = coef_c = coef_lut_a_legacy;
0699         shift_y = shift_c = SHIFT_LUT_A_LEGACY;
0700     }
0701 
0702     if (orient == HVSRC_HORI) {
0703         hvsrc->hori_shift = (shift_c << 16) | shift_y;
0704         memcpy(hvsrc->yh_coef, coef_y, sizeof(hvsrc->yh_coef));
0705         memcpy(hvsrc->ch_coef, coef_c, sizeof(hvsrc->ch_coef));
0706     } else {
0707         hvsrc->vert_shift = (shift_c << 16) | shift_y;
0708         memcpy(hvsrc->yv_coef, coef_y, sizeof(hvsrc->yv_coef));
0709         memcpy(hvsrc->cv_coef, coef_c, sizeof(hvsrc->cv_coef));
0710     }
0711 }
0712 
0713 /**
0714  * sti_hqvdp_check_hw_scaling
0715  * @hqvdp: hqvdp pointer
0716  * @mode: display mode with timing constraints
0717  * @src_w: source width
0718  * @src_h: source height
0719  * @dst_w: destination width
0720  * @dst_h: destination height
0721  *
0722  * Check if the HW is able to perform the scaling request
0723  * The firmware scaling limitation is "CEIL(1/Zy) <= FLOOR(LFW)" where:
0724  *   Zy = OutputHeight / InputHeight
0725  *   LFW = (Tx * IPClock) / (MaxNbCycles * Cp)
0726  *     Tx : Total video mode horizontal resolution
0727  *     IPClock : HQVDP IP clock (Mhz)
0728  *     MaxNbCycles: max(InputWidth, OutputWidth)
0729  *     Cp: Video mode pixel clock (Mhz)
0730  *
0731  * RETURNS:
0732  * True if the HW can scale.
0733  */
0734 static bool sti_hqvdp_check_hw_scaling(struct sti_hqvdp *hqvdp,
0735                        struct drm_display_mode *mode,
0736                        int src_w, int src_h,
0737                        int dst_w, int dst_h)
0738 {
0739     unsigned long lfw;
0740     unsigned int inv_zy;
0741 
0742     lfw = mode->htotal * (clk_get_rate(hqvdp->clk) / 1000000);
0743     lfw /= max(src_w, dst_w) * mode->clock / 1000;
0744 
0745     inv_zy = DIV_ROUND_UP(src_h, dst_h);
0746 
0747     return (inv_zy <= lfw) ? true : false;
0748 }
0749 
0750 /**
0751  * sti_hqvdp_disable
0752  * @hqvdp: hqvdp pointer
0753  *
0754  * Disables the HQVDP plane
0755  */
0756 static void sti_hqvdp_disable(struct sti_hqvdp *hqvdp)
0757 {
0758     int i;
0759 
0760     DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&hqvdp->plane));
0761 
0762     /* Unregister VTG Vsync callback */
0763     if (sti_vtg_unregister_client(hqvdp->vtg, &hqvdp->vtg_nb))
0764         DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
0765 
0766     /* Set next cmd to NULL */
0767     writel(0, hqvdp->regs + HQVDP_MBX_NEXT_CMD);
0768 
0769     for (i = 0; i < POLL_MAX_ATTEMPT; i++) {
0770         if (readl(hqvdp->regs + HQVDP_MBX_INFO_XP70)
0771                 & INFO_XP70_FW_READY)
0772             break;
0773         msleep(POLL_DELAY_MS);
0774     }
0775 
0776     /* VTG can stop now */
0777     clk_disable_unprepare(hqvdp->clk_pix_main);
0778 
0779     if (i == POLL_MAX_ATTEMPT)
0780         DRM_ERROR("XP70 could not revert to idle\n");
0781 
0782     hqvdp->plane.status = STI_PLANE_DISABLED;
0783     hqvdp->vtg_registered = false;
0784 }
0785 
0786 /**
0787  * sti_hqvdp_vtg_cb
0788  * @nb: notifier block
0789  * @evt: event message
0790  * @data: private data
0791  *
0792  * Handle VTG Vsync event, display pending bottom field
0793  *
0794  * RETURNS:
0795  * 0 on success.
0796  */
0797 static int sti_hqvdp_vtg_cb(struct notifier_block *nb, unsigned long evt, void *data)
0798 {
0799     struct sti_hqvdp *hqvdp = container_of(nb, struct sti_hqvdp, vtg_nb);
0800     int btm_cmd_offset, top_cmd_offest;
0801     struct sti_hqvdp_cmd *btm_cmd, *top_cmd;
0802 
0803     if ((evt != VTG_TOP_FIELD_EVENT) && (evt != VTG_BOTTOM_FIELD_EVENT)) {
0804         DRM_DEBUG_DRIVER("Unknown event\n");
0805         return 0;
0806     }
0807 
0808     if (hqvdp->plane.status == STI_PLANE_FLUSHING) {
0809         /* disable need to be synchronize on vsync event */
0810         DRM_DEBUG_DRIVER("Vsync event received => disable %s\n",
0811                  sti_plane_to_str(&hqvdp->plane));
0812 
0813         sti_hqvdp_disable(hqvdp);
0814     }
0815 
0816     if (hqvdp->btm_field_pending) {
0817         /* Create the btm field command from the current one */
0818         btm_cmd_offset = sti_hqvdp_get_free_cmd(hqvdp);
0819         top_cmd_offest = sti_hqvdp_get_curr_cmd(hqvdp);
0820         if ((btm_cmd_offset == -1) || (top_cmd_offest == -1)) {
0821             DRM_DEBUG_DRIVER("Warning: no cmd, will skip field\n");
0822             return -EBUSY;
0823         }
0824 
0825         btm_cmd = hqvdp->hqvdp_cmd + btm_cmd_offset;
0826         top_cmd = hqvdp->hqvdp_cmd + top_cmd_offest;
0827 
0828         memcpy(btm_cmd, top_cmd, sizeof(*btm_cmd));
0829 
0830         btm_cmd->top.config = TOP_CONFIG_INTER_BTM;
0831         btm_cmd->top.current_luma +=
0832                 btm_cmd->top.luma_src_pitch / 2;
0833         btm_cmd->top.current_chroma +=
0834                 btm_cmd->top.chroma_src_pitch / 2;
0835 
0836         /* Post the command to mailbox */
0837         writel(hqvdp->hqvdp_cmd_paddr + btm_cmd_offset,
0838                 hqvdp->regs + HQVDP_MBX_NEXT_CMD);
0839 
0840         hqvdp->btm_field_pending = false;
0841 
0842         dev_dbg(hqvdp->dev, "%s Posted command:0x%x\n",
0843                 __func__, hqvdp->hqvdp_cmd_paddr);
0844 
0845         sti_plane_update_fps(&hqvdp->plane, false, true);
0846     }
0847 
0848     return 0;
0849 }
0850 
0851 static void sti_hqvdp_init(struct sti_hqvdp *hqvdp)
0852 {
0853     int size;
0854     dma_addr_t dma_addr;
0855 
0856     hqvdp->vtg_nb.notifier_call = sti_hqvdp_vtg_cb;
0857 
0858     /* Allocate memory for the VDP commands */
0859     size = NB_VDP_CMD * sizeof(struct sti_hqvdp_cmd);
0860     hqvdp->hqvdp_cmd = dma_alloc_wc(hqvdp->dev, size,
0861                     &dma_addr,
0862                     GFP_KERNEL | GFP_DMA);
0863     if (!hqvdp->hqvdp_cmd) {
0864         DRM_ERROR("Failed to allocate memory for VDP cmd\n");
0865         return;
0866     }
0867 
0868     hqvdp->hqvdp_cmd_paddr = (u32)dma_addr;
0869     memset(hqvdp->hqvdp_cmd, 0, size);
0870 }
0871 
0872 static void sti_hqvdp_init_plugs(struct sti_hqvdp *hqvdp)
0873 {
0874     /* Configure Plugs (same for RD & WR) */
0875     writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_RD_PLUG_PAGE_SIZE);
0876     writel(PLUG_MIN_OPC_8, hqvdp->regs + HQVDP_RD_PLUG_MIN_OPC);
0877     writel(PLUG_MAX_OPC_64, hqvdp->regs + HQVDP_RD_PLUG_MAX_OPC);
0878     writel(PLUG_MAX_CHK_2X, hqvdp->regs + HQVDP_RD_PLUG_MAX_CHK);
0879     writel(PLUG_MAX_MSG_1X, hqvdp->regs + HQVDP_RD_PLUG_MAX_MSG);
0880     writel(PLUG_MIN_SPACE_1, hqvdp->regs + HQVDP_RD_PLUG_MIN_SPACE);
0881     writel(PLUG_CONTROL_ENABLE, hqvdp->regs + HQVDP_RD_PLUG_CONTROL);
0882 
0883     writel(PLUG_PAGE_SIZE_256, hqvdp->regs + HQVDP_WR_PLUG_PAGE_SIZE);
0884     writel(PLUG_MIN_OPC_8, hqvdp->regs + HQVDP_WR_PLUG_MIN_OPC);
0885     writel(PLUG_MAX_OPC_64, hqvdp->regs + HQVDP_WR_PLUG_MAX_OPC);
0886     writel(PLUG_MAX_CHK_2X, hqvdp->regs + HQVDP_WR_PLUG_MAX_CHK);
0887     writel(PLUG_MAX_MSG_1X, hqvdp->regs + HQVDP_WR_PLUG_MAX_MSG);
0888     writel(PLUG_MIN_SPACE_1, hqvdp->regs + HQVDP_WR_PLUG_MIN_SPACE);
0889     writel(PLUG_CONTROL_ENABLE, hqvdp->regs + HQVDP_WR_PLUG_CONTROL);
0890 }
0891 
0892 /**
0893  * sti_hqvdp_start_xp70
0894  * @hqvdp: hqvdp pointer
0895  *
0896  * Run the xP70 initialization sequence
0897  */
0898 static void sti_hqvdp_start_xp70(struct sti_hqvdp *hqvdp)
0899 {
0900     const struct firmware *firmware;
0901     u32 *fw_rd_plug, *fw_wr_plug, *fw_pmem, *fw_dmem;
0902     u8 *data;
0903     int i;
0904     struct fw_header {
0905         int rd_size;
0906         int wr_size;
0907         int pmem_size;
0908         int dmem_size;
0909     } *header;
0910 
0911     DRM_DEBUG_DRIVER("\n");
0912 
0913     if (hqvdp->xp70_initialized) {
0914         DRM_DEBUG_DRIVER("HQVDP XP70 already initialized\n");
0915         return;
0916     }
0917 
0918     /* Request firmware */
0919     if (request_firmware(&firmware, HQVDP_FMW_NAME, hqvdp->dev)) {
0920         DRM_ERROR("Can't get HQVDP firmware\n");
0921         return;
0922     }
0923 
0924     /* Check firmware parts */
0925     if (!firmware) {
0926         DRM_ERROR("Firmware not available\n");
0927         return;
0928     }
0929 
0930     header = (struct fw_header *)firmware->data;
0931     if (firmware->size < sizeof(*header)) {
0932         DRM_ERROR("Invalid firmware size (%zu)\n", firmware->size);
0933         goto out;
0934     }
0935     if ((sizeof(*header) + header->rd_size + header->wr_size +
0936         header->pmem_size + header->dmem_size) != firmware->size) {
0937         DRM_ERROR("Invalid fmw structure (%zu+%d+%d+%d+%d != %zu)\n",
0938               sizeof(*header), header->rd_size, header->wr_size,
0939               header->pmem_size, header->dmem_size,
0940               firmware->size);
0941         goto out;
0942     }
0943 
0944     data = (u8 *)firmware->data;
0945     data += sizeof(*header);
0946     fw_rd_plug = (void *)data;
0947     data += header->rd_size;
0948     fw_wr_plug = (void *)data;
0949     data += header->wr_size;
0950     fw_pmem = (void *)data;
0951     data += header->pmem_size;
0952     fw_dmem = (void *)data;
0953 
0954     /* Enable clock */
0955     if (clk_prepare_enable(hqvdp->clk))
0956         DRM_ERROR("Failed to prepare/enable HQVDP clk\n");
0957 
0958     /* Reset */
0959     writel(SW_RESET_CTRL_FULL, hqvdp->regs + HQVDP_MBX_SW_RESET_CTRL);
0960 
0961     for (i = 0; i < POLL_MAX_ATTEMPT; i++) {
0962         if (readl(hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1)
0963                 & STARTUP_CTRL1_RST_DONE)
0964             break;
0965         msleep(POLL_DELAY_MS);
0966     }
0967     if (i == POLL_MAX_ATTEMPT) {
0968         DRM_ERROR("Could not reset\n");
0969         clk_disable_unprepare(hqvdp->clk);
0970         goto out;
0971     }
0972 
0973     /* Init Read & Write plugs */
0974     for (i = 0; i < header->rd_size / 4; i++)
0975         writel(fw_rd_plug[i], hqvdp->regs + HQVDP_RD_PLUG + i * 4);
0976     for (i = 0; i < header->wr_size / 4; i++)
0977         writel(fw_wr_plug[i], hqvdp->regs + HQVDP_WR_PLUG + i * 4);
0978 
0979     sti_hqvdp_init_plugs(hqvdp);
0980 
0981     /* Authorize Idle Mode */
0982     writel(STARTUP_CTRL1_AUTH_IDLE, hqvdp->regs + HQVDP_MBX_STARTUP_CTRL1);
0983 
0984     /* Prevent VTG interruption during the boot */
0985     writel(SOFT_VSYNC_SW_CTRL_IRQ, hqvdp->regs + HQVDP_MBX_SOFT_VSYNC);
0986     writel(0, hqvdp->regs + HQVDP_MBX_NEXT_CMD);
0987 
0988     /* Download PMEM & DMEM */
0989     for (i = 0; i < header->pmem_size / 4; i++)
0990         writel(fw_pmem[i], hqvdp->regs + HQVDP_PMEM + i * 4);
0991     for (i = 0; i < header->dmem_size / 4; i++)
0992         writel(fw_dmem[i], hqvdp->regs + HQVDP_DMEM + i * 4);
0993 
0994     /* Enable fetch */
0995     writel(STARTUP_CTRL2_FETCH_EN, hqvdp->regs + HQVDP_MBX_STARTUP_CTRL2);
0996 
0997     /* Wait end of boot */
0998     for (i = 0; i < POLL_MAX_ATTEMPT; i++) {
0999         if (readl(hqvdp->regs + HQVDP_MBX_INFO_XP70)
1000                 & INFO_XP70_FW_READY)
1001             break;
1002         msleep(POLL_DELAY_MS);
1003     }
1004     if (i == POLL_MAX_ATTEMPT) {
1005         DRM_ERROR("Could not boot\n");
1006         clk_disable_unprepare(hqvdp->clk);
1007         goto out;
1008     }
1009 
1010     /* Launch Vsync */
1011     writel(SOFT_VSYNC_HW, hqvdp->regs + HQVDP_MBX_SOFT_VSYNC);
1012 
1013     DRM_INFO("HQVDP XP70 initialized\n");
1014 
1015     hqvdp->xp70_initialized = true;
1016 
1017 out:
1018     release_firmware(firmware);
1019 }
1020 
1021 static int sti_hqvdp_atomic_check(struct drm_plane *drm_plane,
1022                   struct drm_atomic_state *state)
1023 {
1024     struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
1025                                          drm_plane);
1026     struct sti_plane *plane = to_sti_plane(drm_plane);
1027     struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane);
1028     struct drm_crtc *crtc = new_plane_state->crtc;
1029     struct drm_framebuffer *fb = new_plane_state->fb;
1030     struct drm_crtc_state *crtc_state;
1031     struct drm_display_mode *mode;
1032     int dst_x, dst_y, dst_w, dst_h;
1033     int src_x, src_y, src_w, src_h;
1034 
1035     /* no need for further checks if the plane is being disabled */
1036     if (!crtc || !fb)
1037         return 0;
1038 
1039     crtc_state = drm_atomic_get_crtc_state(state, crtc);
1040     mode = &crtc_state->mode;
1041     dst_x = new_plane_state->crtc_x;
1042     dst_y = new_plane_state->crtc_y;
1043     dst_w = clamp_val(new_plane_state->crtc_w, 0, mode->hdisplay - dst_x);
1044     dst_h = clamp_val(new_plane_state->crtc_h, 0, mode->vdisplay - dst_y);
1045     /* src_x are in 16.16 format */
1046     src_x = new_plane_state->src_x >> 16;
1047     src_y = new_plane_state->src_y >> 16;
1048     src_w = new_plane_state->src_w >> 16;
1049     src_h = new_plane_state->src_h >> 16;
1050 
1051     if (mode->clock && !sti_hqvdp_check_hw_scaling(hqvdp, mode,
1052                                src_w, src_h,
1053                                dst_w, dst_h)) {
1054         DRM_ERROR("Scaling beyond HW capabilities\n");
1055         return -EINVAL;
1056     }
1057 
1058     if (!drm_fb_cma_get_gem_obj(fb, 0)) {
1059         DRM_ERROR("Can't get CMA GEM object for fb\n");
1060         return -EINVAL;
1061     }
1062 
1063     /*
1064      * Input / output size
1065      * Align to upper even value
1066      */
1067     dst_w = ALIGN(dst_w, 2);
1068     dst_h = ALIGN(dst_h, 2);
1069 
1070     if ((src_w > MAX_WIDTH) || (src_w < MIN_WIDTH) ||
1071         (src_h > MAX_HEIGHT) || (src_h < MIN_HEIGHT) ||
1072         (dst_w > MAX_WIDTH) || (dst_w < MIN_WIDTH) ||
1073         (dst_h > MAX_HEIGHT) || (dst_h < MIN_HEIGHT)) {
1074         DRM_ERROR("Invalid in/out size %dx%d -> %dx%d\n",
1075               src_w, src_h,
1076               dst_w, dst_h);
1077         return -EINVAL;
1078     }
1079 
1080     if (!hqvdp->xp70_initialized)
1081         /* Start HQVDP XP70 coprocessor */
1082         sti_hqvdp_start_xp70(hqvdp);
1083 
1084     if (!hqvdp->vtg_registered) {
1085         /* Prevent VTG shutdown */
1086         if (clk_prepare_enable(hqvdp->clk_pix_main)) {
1087             DRM_ERROR("Failed to prepare/enable pix main clk\n");
1088             return -EINVAL;
1089         }
1090 
1091         /* Register VTG Vsync callback to handle bottom fields */
1092         if (sti_vtg_register_client(hqvdp->vtg,
1093                         &hqvdp->vtg_nb,
1094                         crtc)) {
1095             DRM_ERROR("Cannot register VTG notifier\n");
1096             clk_disable_unprepare(hqvdp->clk_pix_main);
1097             return -EINVAL;
1098         }
1099         hqvdp->vtg_registered = true;
1100     }
1101 
1102     DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n",
1103               crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc)),
1104               drm_plane->base.id, sti_plane_to_str(plane));
1105     DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n",
1106               sti_plane_to_str(plane),
1107               dst_w, dst_h, dst_x, dst_y,
1108               src_w, src_h, src_x, src_y);
1109 
1110     return 0;
1111 }
1112 
1113 static void sti_hqvdp_atomic_update(struct drm_plane *drm_plane,
1114                     struct drm_atomic_state *state)
1115 {
1116     struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state,
1117                                       drm_plane);
1118     struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state,
1119                                       drm_plane);
1120     struct sti_plane *plane = to_sti_plane(drm_plane);
1121     struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane);
1122     struct drm_crtc *crtc = newstate->crtc;
1123     struct drm_framebuffer *fb = newstate->fb;
1124     struct drm_display_mode *mode;
1125     int dst_x, dst_y, dst_w, dst_h;
1126     int src_x, src_y, src_w, src_h;
1127     struct drm_gem_cma_object *cma_obj;
1128     struct sti_hqvdp_cmd *cmd;
1129     int scale_h, scale_v;
1130     int cmd_offset;
1131 
1132     if (!crtc || !fb)
1133         return;
1134 
1135     if ((oldstate->fb == newstate->fb) &&
1136         (oldstate->crtc_x == newstate->crtc_x) &&
1137         (oldstate->crtc_y == newstate->crtc_y) &&
1138         (oldstate->crtc_w == newstate->crtc_w) &&
1139         (oldstate->crtc_h == newstate->crtc_h) &&
1140         (oldstate->src_x == newstate->src_x) &&
1141         (oldstate->src_y == newstate->src_y) &&
1142         (oldstate->src_w == newstate->src_w) &&
1143         (oldstate->src_h == newstate->src_h)) {
1144         /* No change since last update, do not post cmd */
1145         DRM_DEBUG_DRIVER("No change, not posting cmd\n");
1146         plane->status = STI_PLANE_UPDATED;
1147         return;
1148     }
1149 
1150     mode = &crtc->mode;
1151     dst_x = newstate->crtc_x;
1152     dst_y = newstate->crtc_y;
1153     dst_w = clamp_val(newstate->crtc_w, 0, mode->hdisplay - dst_x);
1154     dst_h = clamp_val(newstate->crtc_h, 0, mode->vdisplay - dst_y);
1155     /* src_x are in 16.16 format */
1156     src_x = newstate->src_x >> 16;
1157     src_y = newstate->src_y >> 16;
1158     src_w = newstate->src_w >> 16;
1159     src_h = newstate->src_h >> 16;
1160 
1161     cmd_offset = sti_hqvdp_get_free_cmd(hqvdp);
1162     if (cmd_offset == -1) {
1163         DRM_DEBUG_DRIVER("Warning: no cmd, will skip frame\n");
1164         return;
1165     }
1166     cmd = hqvdp->hqvdp_cmd + cmd_offset;
1167 
1168     /* Static parameters, defaulting to progressive mode */
1169     cmd->top.config = TOP_CONFIG_PROGRESSIVE;
1170     cmd->top.mem_format = TOP_MEM_FORMAT_DFLT;
1171     cmd->hvsrc.param_ctrl = HVSRC_PARAM_CTRL_DFLT;
1172     cmd->csdi.config = CSDI_CONFIG_PROG;
1173 
1174     /* VC1RE, FMD bypassed : keep everything set to 0
1175      * IQI/P2I bypassed */
1176     cmd->iqi.config = IQI_CONFIG_DFLT;
1177     cmd->iqi.con_bri = IQI_CON_BRI_DFLT;
1178     cmd->iqi.sat_gain = IQI_SAT_GAIN_DFLT;
1179     cmd->iqi.pxf_conf = IQI_PXF_CONF_DFLT;
1180 
1181     cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
1182 
1183     DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id,
1184              (char *)&fb->format->format,
1185              (unsigned long)cma_obj->paddr);
1186 
1187     /* Buffer planes address */
1188     cmd->top.current_luma = (u32)cma_obj->paddr + fb->offsets[0];
1189     cmd->top.current_chroma = (u32)cma_obj->paddr + fb->offsets[1];
1190 
1191     /* Pitches */
1192     cmd->top.luma_processed_pitch = fb->pitches[0];
1193     cmd->top.luma_src_pitch = fb->pitches[0];
1194     cmd->top.chroma_processed_pitch = fb->pitches[1];
1195     cmd->top.chroma_src_pitch = fb->pitches[1];
1196 
1197     /* Input / output size
1198      * Align to upper even value */
1199     dst_w = ALIGN(dst_w, 2);
1200     dst_h = ALIGN(dst_h, 2);
1201 
1202     cmd->top.input_viewport_size = src_h << 16 | src_w;
1203     cmd->top.input_frame_size = src_h << 16 | src_w;
1204     cmd->hvsrc.output_picture_size = dst_h << 16 | dst_w;
1205     cmd->top.input_viewport_ori = src_y << 16 | src_x;
1206 
1207     /* Handle interlaced */
1208     if (fb->flags & DRM_MODE_FB_INTERLACED) {
1209         /* Top field to display */
1210         cmd->top.config = TOP_CONFIG_INTER_TOP;
1211 
1212         /* Update pitches and vert size */
1213         cmd->top.input_frame_size = (src_h / 2) << 16 | src_w;
1214         cmd->top.luma_processed_pitch *= 2;
1215         cmd->top.luma_src_pitch *= 2;
1216         cmd->top.chroma_processed_pitch *= 2;
1217         cmd->top.chroma_src_pitch *= 2;
1218 
1219         /* Enable directional deinterlacing processing */
1220         cmd->csdi.config = CSDI_CONFIG_INTER_DIR;
1221         cmd->csdi.config2 = CSDI_CONFIG2_DFLT;
1222         cmd->csdi.dcdi_config = CSDI_DCDI_CONFIG_DFLT;
1223     }
1224 
1225     /* Update hvsrc lut coef */
1226     scale_h = SCALE_FACTOR * dst_w / src_w;
1227     sti_hqvdp_update_hvsrc(HVSRC_HORI, scale_h, &cmd->hvsrc);
1228 
1229     scale_v = SCALE_FACTOR * dst_h / src_h;
1230     sti_hqvdp_update_hvsrc(HVSRC_VERT, scale_v, &cmd->hvsrc);
1231 
1232     writel(hqvdp->hqvdp_cmd_paddr + cmd_offset,
1233            hqvdp->regs + HQVDP_MBX_NEXT_CMD);
1234 
1235     /* Interlaced : get ready to display the bottom field at next Vsync */
1236     if (fb->flags & DRM_MODE_FB_INTERLACED)
1237         hqvdp->btm_field_pending = true;
1238 
1239     dev_dbg(hqvdp->dev, "%s Posted command:0x%x\n",
1240         __func__, hqvdp->hqvdp_cmd_paddr + cmd_offset);
1241 
1242     sti_plane_update_fps(plane, true, true);
1243 
1244     plane->status = STI_PLANE_UPDATED;
1245 }
1246 
1247 static void sti_hqvdp_atomic_disable(struct drm_plane *drm_plane,
1248                      struct drm_atomic_state *state)
1249 {
1250     struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state,
1251                                       drm_plane);
1252     struct sti_plane *plane = to_sti_plane(drm_plane);
1253 
1254     if (!oldstate->crtc) {
1255         DRM_DEBUG_DRIVER("drm plane:%d not enabled\n",
1256                  drm_plane->base.id);
1257         return;
1258     }
1259 
1260     DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n",
1261              oldstate->crtc->base.id,
1262              sti_mixer_to_str(to_sti_mixer(oldstate->crtc)),
1263              drm_plane->base.id, sti_plane_to_str(plane));
1264 
1265     plane->status = STI_PLANE_DISABLING;
1266 }
1267 
1268 static const struct drm_plane_helper_funcs sti_hqvdp_helpers_funcs = {
1269     .atomic_check = sti_hqvdp_atomic_check,
1270     .atomic_update = sti_hqvdp_atomic_update,
1271     .atomic_disable = sti_hqvdp_atomic_disable,
1272 };
1273 
1274 static int sti_hqvdp_late_register(struct drm_plane *drm_plane)
1275 {
1276     struct sti_plane *plane = to_sti_plane(drm_plane);
1277     struct sti_hqvdp *hqvdp = to_sti_hqvdp(plane);
1278 
1279     hqvdp_debugfs_init(hqvdp, drm_plane->dev->primary);
1280 
1281     return 0;
1282 }
1283 
1284 static const struct drm_plane_funcs sti_hqvdp_plane_helpers_funcs = {
1285     .update_plane = drm_atomic_helper_update_plane,
1286     .disable_plane = drm_atomic_helper_disable_plane,
1287     .destroy = drm_plane_cleanup,
1288     .reset = drm_atomic_helper_plane_reset,
1289     .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1290     .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1291     .late_register = sti_hqvdp_late_register,
1292 };
1293 
1294 static struct drm_plane *sti_hqvdp_create(struct drm_device *drm_dev,
1295                       struct device *dev, int desc)
1296 {
1297     struct sti_hqvdp *hqvdp = dev_get_drvdata(dev);
1298     int res;
1299 
1300     hqvdp->plane.desc = desc;
1301     hqvdp->plane.status = STI_PLANE_DISABLED;
1302 
1303     sti_hqvdp_init(hqvdp);
1304 
1305     res = drm_universal_plane_init(drm_dev, &hqvdp->plane.drm_plane, 1,
1306                        &sti_hqvdp_plane_helpers_funcs,
1307                        hqvdp_supported_formats,
1308                        ARRAY_SIZE(hqvdp_supported_formats),
1309                        NULL, DRM_PLANE_TYPE_OVERLAY, NULL);
1310     if (res) {
1311         DRM_ERROR("Failed to initialize universal plane\n");
1312         return NULL;
1313     }
1314 
1315     drm_plane_helper_add(&hqvdp->plane.drm_plane, &sti_hqvdp_helpers_funcs);
1316 
1317     sti_plane_init_property(&hqvdp->plane, DRM_PLANE_TYPE_OVERLAY);
1318 
1319     return &hqvdp->plane.drm_plane;
1320 }
1321 
1322 static int sti_hqvdp_bind(struct device *dev, struct device *master, void *data)
1323 {
1324     struct sti_hqvdp *hqvdp = dev_get_drvdata(dev);
1325     struct drm_device *drm_dev = data;
1326     struct drm_plane *plane;
1327 
1328     DRM_DEBUG_DRIVER("\n");
1329 
1330     hqvdp->drm_dev = drm_dev;
1331 
1332     /* Create HQVDP plane once xp70 is initialized */
1333     plane = sti_hqvdp_create(drm_dev, hqvdp->dev, STI_HQVDP_0);
1334     if (!plane)
1335         DRM_ERROR("Can't create HQVDP plane\n");
1336 
1337     return 0;
1338 }
1339 
1340 static void sti_hqvdp_unbind(struct device *dev,
1341         struct device *master, void *data)
1342 {
1343     /* do nothing */
1344 }
1345 
1346 static const struct component_ops sti_hqvdp_ops = {
1347     .bind = sti_hqvdp_bind,
1348     .unbind = sti_hqvdp_unbind,
1349 };
1350 
1351 static int sti_hqvdp_probe(struct platform_device *pdev)
1352 {
1353     struct device *dev = &pdev->dev;
1354     struct device_node *vtg_np;
1355     struct sti_hqvdp *hqvdp;
1356     struct resource *res;
1357 
1358     DRM_DEBUG_DRIVER("\n");
1359 
1360     hqvdp = devm_kzalloc(dev, sizeof(*hqvdp), GFP_KERNEL);
1361     if (!hqvdp) {
1362         DRM_ERROR("Failed to allocate HQVDP context\n");
1363         return -ENOMEM;
1364     }
1365 
1366     hqvdp->dev = dev;
1367 
1368     /* Get Memory resources */
1369     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1370     if (!res) {
1371         DRM_ERROR("Get memory resource failed\n");
1372         return -ENXIO;
1373     }
1374     hqvdp->regs = devm_ioremap(dev, res->start, resource_size(res));
1375     if (!hqvdp->regs) {
1376         DRM_ERROR("Register mapping failed\n");
1377         return -ENXIO;
1378     }
1379 
1380     /* Get clock resources */
1381     hqvdp->clk = devm_clk_get(dev, "hqvdp");
1382     hqvdp->clk_pix_main = devm_clk_get(dev, "pix_main");
1383     if (IS_ERR(hqvdp->clk) || IS_ERR(hqvdp->clk_pix_main)) {
1384         DRM_ERROR("Cannot get clocks\n");
1385         return -ENXIO;
1386     }
1387 
1388     /* Get reset resources */
1389     hqvdp->reset = devm_reset_control_get(dev, "hqvdp");
1390     if (!IS_ERR(hqvdp->reset))
1391         reset_control_deassert(hqvdp->reset);
1392 
1393     vtg_np = of_parse_phandle(pdev->dev.of_node, "st,vtg", 0);
1394     if (vtg_np)
1395         hqvdp->vtg = of_vtg_find(vtg_np);
1396     of_node_put(vtg_np);
1397 
1398     platform_set_drvdata(pdev, hqvdp);
1399 
1400     return component_add(&pdev->dev, &sti_hqvdp_ops);
1401 }
1402 
1403 static int sti_hqvdp_remove(struct platform_device *pdev)
1404 {
1405     component_del(&pdev->dev, &sti_hqvdp_ops);
1406     return 0;
1407 }
1408 
1409 static const struct of_device_id hqvdp_of_match[] = {
1410     { .compatible = "st,stih407-hqvdp", },
1411     { /* end node */ }
1412 };
1413 MODULE_DEVICE_TABLE(of, hqvdp_of_match);
1414 
1415 struct platform_driver sti_hqvdp_driver = {
1416     .driver = {
1417         .name = "sti-hqvdp",
1418         .owner = THIS_MODULE,
1419         .of_match_table = hqvdp_of_match,
1420     },
1421     .probe = sti_hqvdp_probe,
1422     .remove = sti_hqvdp_remove,
1423 };
1424 
1425 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
1426 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
1427 MODULE_LICENSE("GPL");
[ Source navigation ] [ Diff markup ] [ Identifier search ] [ general search ]

This page was automatically generated by the 2.1.0 LXR engine.

The LXR team
Valid CSS 2.1! Valid HTML 4.01!