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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) STMicroelectronics SA 2014
0004  * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
0005  */
0006 
0007 #include <linux/clk.h>
0008 #include <linux/component.h>
0009 #include <linux/debugfs.h>
0010 #include <linux/hdmi.h>
0011 #include <linux/i2c.h>
0012 #include <linux/module.h>
0013 #include <linux/io.h>
0014 #include <linux/platform_device.h>
0015 #include <linux/reset.h>
0016 
0017 #include <drm/drm_atomic_helper.h>
0018 #include <drm/drm_bridge.h>
0019 #include <drm/drm_debugfs.h>
0020 #include <drm/drm_drv.h>
0021 #include <drm/drm_edid.h>
0022 #include <drm/drm_file.h>
0023 #include <drm/drm_print.h>
0024 #include <drm/drm_probe_helper.h>
0025 
0026 #include <sound/hdmi-codec.h>
0027 
0028 #include "sti_hdmi.h"
0029 #include "sti_hdmi_tx3g4c28phy.h"
0030 #include "sti_vtg.h"
0031 
0032 #define HDMI_CFG                        0x0000
0033 #define HDMI_INT_EN                     0x0004
0034 #define HDMI_INT_STA                    0x0008
0035 #define HDMI_INT_CLR                    0x000C
0036 #define HDMI_STA                        0x0010
0037 #define HDMI_ACTIVE_VID_XMIN            0x0100
0038 #define HDMI_ACTIVE_VID_XMAX            0x0104
0039 #define HDMI_ACTIVE_VID_YMIN            0x0108
0040 #define HDMI_ACTIVE_VID_YMAX            0x010C
0041 #define HDMI_DFLT_CHL0_DAT              0x0110
0042 #define HDMI_DFLT_CHL1_DAT              0x0114
0043 #define HDMI_DFLT_CHL2_DAT              0x0118
0044 #define HDMI_AUDIO_CFG                  0x0200
0045 #define HDMI_SPDIF_FIFO_STATUS          0x0204
0046 #define HDMI_SW_DI_1_HEAD_WORD          0x0210
0047 #define HDMI_SW_DI_1_PKT_WORD0          0x0214
0048 #define HDMI_SW_DI_1_PKT_WORD1          0x0218
0049 #define HDMI_SW_DI_1_PKT_WORD2          0x021C
0050 #define HDMI_SW_DI_1_PKT_WORD3          0x0220
0051 #define HDMI_SW_DI_1_PKT_WORD4          0x0224
0052 #define HDMI_SW_DI_1_PKT_WORD5          0x0228
0053 #define HDMI_SW_DI_1_PKT_WORD6          0x022C
0054 #define HDMI_SW_DI_CFG                  0x0230
0055 #define HDMI_SAMPLE_FLAT_MASK           0x0244
0056 #define HDMI_AUDN                       0x0400
0057 #define HDMI_AUD_CTS                    0x0404
0058 #define HDMI_SW_DI_2_HEAD_WORD          0x0600
0059 #define HDMI_SW_DI_2_PKT_WORD0          0x0604
0060 #define HDMI_SW_DI_2_PKT_WORD1          0x0608
0061 #define HDMI_SW_DI_2_PKT_WORD2          0x060C
0062 #define HDMI_SW_DI_2_PKT_WORD3          0x0610
0063 #define HDMI_SW_DI_2_PKT_WORD4          0x0614
0064 #define HDMI_SW_DI_2_PKT_WORD5          0x0618
0065 #define HDMI_SW_DI_2_PKT_WORD6          0x061C
0066 #define HDMI_SW_DI_3_HEAD_WORD          0x0620
0067 #define HDMI_SW_DI_3_PKT_WORD0          0x0624
0068 #define HDMI_SW_DI_3_PKT_WORD1          0x0628
0069 #define HDMI_SW_DI_3_PKT_WORD2          0x062C
0070 #define HDMI_SW_DI_3_PKT_WORD3          0x0630
0071 #define HDMI_SW_DI_3_PKT_WORD4          0x0634
0072 #define HDMI_SW_DI_3_PKT_WORD5          0x0638
0073 #define HDMI_SW_DI_3_PKT_WORD6          0x063C
0074 
0075 #define HDMI_IFRAME_SLOT_AVI            1
0076 #define HDMI_IFRAME_SLOT_AUDIO          2
0077 #define HDMI_IFRAME_SLOT_VENDOR         3
0078 
0079 #define  XCAT(prefix, x, suffix)        prefix ## x ## suffix
0080 #define  HDMI_SW_DI_N_HEAD_WORD(x)      XCAT(HDMI_SW_DI_, x, _HEAD_WORD)
0081 #define  HDMI_SW_DI_N_PKT_WORD0(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD0)
0082 #define  HDMI_SW_DI_N_PKT_WORD1(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD1)
0083 #define  HDMI_SW_DI_N_PKT_WORD2(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD2)
0084 #define  HDMI_SW_DI_N_PKT_WORD3(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD3)
0085 #define  HDMI_SW_DI_N_PKT_WORD4(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD4)
0086 #define  HDMI_SW_DI_N_PKT_WORD5(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD5)
0087 #define  HDMI_SW_DI_N_PKT_WORD6(x)      XCAT(HDMI_SW_DI_, x, _PKT_WORD6)
0088 
0089 #define HDMI_SW_DI_MAX_WORD             7
0090 
0091 #define HDMI_IFRAME_DISABLED            0x0
0092 #define HDMI_IFRAME_SINGLE_SHOT         0x1
0093 #define HDMI_IFRAME_FIELD               0x2
0094 #define HDMI_IFRAME_FRAME               0x3
0095 #define HDMI_IFRAME_MASK                0x3
0096 #define HDMI_IFRAME_CFG_DI_N(x, n)       ((x) << ((n-1)*4)) /* n from 1 to 6 */
0097 
0098 #define HDMI_CFG_DEVICE_EN              BIT(0)
0099 #define HDMI_CFG_HDMI_NOT_DVI           BIT(1)
0100 #define HDMI_CFG_HDCP_EN                BIT(2)
0101 #define HDMI_CFG_ESS_NOT_OESS           BIT(3)
0102 #define HDMI_CFG_H_SYNC_POL_NEG         BIT(4)
0103 #define HDMI_CFG_V_SYNC_POL_NEG         BIT(6)
0104 #define HDMI_CFG_422_EN                 BIT(8)
0105 #define HDMI_CFG_FIFO_OVERRUN_CLR       BIT(12)
0106 #define HDMI_CFG_FIFO_UNDERRUN_CLR      BIT(13)
0107 #define HDMI_CFG_SW_RST_EN              BIT(31)
0108 
0109 #define HDMI_INT_GLOBAL                 BIT(0)
0110 #define HDMI_INT_SW_RST                 BIT(1)
0111 #define HDMI_INT_PIX_CAP                BIT(3)
0112 #define HDMI_INT_HOT_PLUG               BIT(4)
0113 #define HDMI_INT_DLL_LCK                BIT(5)
0114 #define HDMI_INT_NEW_FRAME              BIT(6)
0115 #define HDMI_INT_GENCTRL_PKT            BIT(7)
0116 #define HDMI_INT_AUDIO_FIFO_XRUN        BIT(8)
0117 #define HDMI_INT_SINK_TERM_PRESENT      BIT(11)
0118 
0119 #define HDMI_DEFAULT_INT (HDMI_INT_SINK_TERM_PRESENT \
0120             | HDMI_INT_DLL_LCK \
0121             | HDMI_INT_HOT_PLUG \
0122             | HDMI_INT_GLOBAL)
0123 
0124 #define HDMI_WORKING_INT (HDMI_INT_SINK_TERM_PRESENT \
0125             | HDMI_INT_AUDIO_FIFO_XRUN \
0126             | HDMI_INT_GENCTRL_PKT \
0127             | HDMI_INT_NEW_FRAME \
0128             | HDMI_INT_DLL_LCK \
0129             | HDMI_INT_HOT_PLUG \
0130             | HDMI_INT_PIX_CAP \
0131             | HDMI_INT_SW_RST \
0132             | HDMI_INT_GLOBAL)
0133 
0134 #define HDMI_STA_SW_RST                 BIT(1)
0135 
0136 #define HDMI_AUD_CFG_8CH        BIT(0)
0137 #define HDMI_AUD_CFG_SPDIF_DIV_2    BIT(1)
0138 #define HDMI_AUD_CFG_SPDIF_DIV_3    BIT(2)
0139 #define HDMI_AUD_CFG_SPDIF_CLK_DIV_4    (BIT(1) | BIT(2))
0140 #define HDMI_AUD_CFG_CTS_CLK_256FS  BIT(12)
0141 #define HDMI_AUD_CFG_DTS_INVALID    BIT(16)
0142 #define HDMI_AUD_CFG_ONE_BIT_INVALID    (BIT(18) | BIT(19) | BIT(20) |  BIT(21))
0143 #define HDMI_AUD_CFG_CH12_VALID BIT(28)
0144 #define HDMI_AUD_CFG_CH34_VALID BIT(29)
0145 #define HDMI_AUD_CFG_CH56_VALID BIT(30)
0146 #define HDMI_AUD_CFG_CH78_VALID BIT(31)
0147 
0148 /* sample flat mask */
0149 #define HDMI_SAMPLE_FLAT_NO  0
0150 #define HDMI_SAMPLE_FLAT_SP0 BIT(0)
0151 #define HDMI_SAMPLE_FLAT_SP1 BIT(1)
0152 #define HDMI_SAMPLE_FLAT_SP2 BIT(2)
0153 #define HDMI_SAMPLE_FLAT_SP3 BIT(3)
0154 #define HDMI_SAMPLE_FLAT_ALL (HDMI_SAMPLE_FLAT_SP0 | HDMI_SAMPLE_FLAT_SP1 |\
0155                   HDMI_SAMPLE_FLAT_SP2 | HDMI_SAMPLE_FLAT_SP3)
0156 
0157 #define HDMI_INFOFRAME_HEADER_TYPE(x)    (((x) & 0xff) <<  0)
0158 #define HDMI_INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) <<  8)
0159 #define HDMI_INFOFRAME_HEADER_LEN(x)     (((x) & 0x0f) << 16)
0160 
0161 struct sti_hdmi_connector {
0162     struct drm_connector drm_connector;
0163     struct drm_encoder *encoder;
0164     struct sti_hdmi *hdmi;
0165     struct drm_property *colorspace_property;
0166 };
0167 
0168 #define to_sti_hdmi_connector(x) \
0169     container_of(x, struct sti_hdmi_connector, drm_connector)
0170 
0171 static const struct drm_prop_enum_list colorspace_mode_names[] = {
0172     { HDMI_COLORSPACE_RGB, "rgb" },
0173     { HDMI_COLORSPACE_YUV422, "yuv422" },
0174     { HDMI_COLORSPACE_YUV444, "yuv444" },
0175 };
0176 
0177 u32 hdmi_read(struct sti_hdmi *hdmi, int offset)
0178 {
0179     return readl(hdmi->regs + offset);
0180 }
0181 
0182 void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset)
0183 {
0184     writel(val, hdmi->regs + offset);
0185 }
0186 
0187 /*
0188  * HDMI interrupt handler threaded
0189  *
0190  * @irq: irq number
0191  * @arg: connector structure
0192  */
0193 static irqreturn_t hdmi_irq_thread(int irq, void *arg)
0194 {
0195     struct sti_hdmi *hdmi = arg;
0196 
0197     /* Hot plug/unplug IRQ */
0198     if (hdmi->irq_status & HDMI_INT_HOT_PLUG) {
0199         hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG;
0200         if (hdmi->drm_dev)
0201             drm_helper_hpd_irq_event(hdmi->drm_dev);
0202     }
0203 
0204     /* Sw reset and PLL lock are exclusive so we can use the same
0205      * event to signal them
0206      */
0207     if (hdmi->irq_status & (HDMI_INT_SW_RST | HDMI_INT_DLL_LCK)) {
0208         hdmi->event_received = true;
0209         wake_up_interruptible(&hdmi->wait_event);
0210     }
0211 
0212     /* Audio FIFO underrun IRQ */
0213     if (hdmi->irq_status & HDMI_INT_AUDIO_FIFO_XRUN)
0214         DRM_INFO("Warning: audio FIFO underrun occurs!\n");
0215 
0216     return IRQ_HANDLED;
0217 }
0218 
0219 /*
0220  * HDMI interrupt handler
0221  *
0222  * @irq: irq number
0223  * @arg: connector structure
0224  */
0225 static irqreturn_t hdmi_irq(int irq, void *arg)
0226 {
0227     struct sti_hdmi *hdmi = arg;
0228 
0229     /* read interrupt status */
0230     hdmi->irq_status = hdmi_read(hdmi, HDMI_INT_STA);
0231 
0232     /* clear interrupt status */
0233     hdmi_write(hdmi, hdmi->irq_status, HDMI_INT_CLR);
0234 
0235     /* force sync bus write */
0236     hdmi_read(hdmi, HDMI_INT_STA);
0237 
0238     return IRQ_WAKE_THREAD;
0239 }
0240 
0241 /*
0242  * Set hdmi active area depending on the drm display mode selected
0243  *
0244  * @hdmi: pointer on the hdmi internal structure
0245  */
0246 static void hdmi_active_area(struct sti_hdmi *hdmi)
0247 {
0248     u32 xmin, xmax;
0249     u32 ymin, ymax;
0250 
0251     xmin = sti_vtg_get_pixel_number(hdmi->mode, 1);
0252     xmax = sti_vtg_get_pixel_number(hdmi->mode, hdmi->mode.hdisplay);
0253     ymin = sti_vtg_get_line_number(hdmi->mode, 0);
0254     ymax = sti_vtg_get_line_number(hdmi->mode, hdmi->mode.vdisplay - 1);
0255 
0256     hdmi_write(hdmi, xmin, HDMI_ACTIVE_VID_XMIN);
0257     hdmi_write(hdmi, xmax, HDMI_ACTIVE_VID_XMAX);
0258     hdmi_write(hdmi, ymin, HDMI_ACTIVE_VID_YMIN);
0259     hdmi_write(hdmi, ymax, HDMI_ACTIVE_VID_YMAX);
0260 }
0261 
0262 /*
0263  * Overall hdmi configuration
0264  *
0265  * @hdmi: pointer on the hdmi internal structure
0266  */
0267 static void hdmi_config(struct sti_hdmi *hdmi)
0268 {
0269     u32 conf;
0270 
0271     DRM_DEBUG_DRIVER("\n");
0272 
0273     /* Clear overrun and underrun fifo */
0274     conf = HDMI_CFG_FIFO_OVERRUN_CLR | HDMI_CFG_FIFO_UNDERRUN_CLR;
0275 
0276     /* Select encryption type and the framing mode */
0277     conf |= HDMI_CFG_ESS_NOT_OESS;
0278     if (hdmi->hdmi_monitor)
0279         conf |= HDMI_CFG_HDMI_NOT_DVI;
0280 
0281     /* Set Hsync polarity */
0282     if (hdmi->mode.flags & DRM_MODE_FLAG_NHSYNC) {
0283         DRM_DEBUG_DRIVER("H Sync Negative\n");
0284         conf |= HDMI_CFG_H_SYNC_POL_NEG;
0285     }
0286 
0287     /* Set Vsync polarity */
0288     if (hdmi->mode.flags & DRM_MODE_FLAG_NVSYNC) {
0289         DRM_DEBUG_DRIVER("V Sync Negative\n");
0290         conf |= HDMI_CFG_V_SYNC_POL_NEG;
0291     }
0292 
0293     /* Enable HDMI */
0294     conf |= HDMI_CFG_DEVICE_EN;
0295 
0296     hdmi_write(hdmi, conf, HDMI_CFG);
0297 }
0298 
0299 /*
0300  * Helper to reset info frame
0301  *
0302  * @hdmi: pointer on the hdmi internal structure
0303  * @slot: infoframe to reset
0304  */
0305 static void hdmi_infoframe_reset(struct sti_hdmi *hdmi,
0306                  u32 slot)
0307 {
0308     u32 val, i;
0309     u32 head_offset, pack_offset;
0310 
0311     switch (slot) {
0312     case HDMI_IFRAME_SLOT_AVI:
0313         head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI);
0314         pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI);
0315         break;
0316     case HDMI_IFRAME_SLOT_AUDIO:
0317         head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO);
0318         pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO);
0319         break;
0320     case HDMI_IFRAME_SLOT_VENDOR:
0321         head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR);
0322         pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR);
0323         break;
0324     default:
0325         DRM_ERROR("unsupported infoframe slot: %#x\n", slot);
0326         return;
0327     }
0328 
0329     /* Disable transmission for the selected slot */
0330     val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
0331     val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot);
0332     hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
0333 
0334     /* Reset info frame registers */
0335     hdmi_write(hdmi, 0x0, head_offset);
0336     for (i = 0; i < HDMI_SW_DI_MAX_WORD; i += sizeof(u32))
0337         hdmi_write(hdmi, 0x0, pack_offset + i);
0338 }
0339 
0340 /*
0341  * Helper to concatenate infoframe in 32 bits word
0342  *
0343  * @ptr: pointer on the hdmi internal structure
0344  * @size: size to write
0345  */
0346 static inline unsigned int hdmi_infoframe_subpack(const u8 *ptr, size_t size)
0347 {
0348     unsigned long value = 0;
0349     size_t i;
0350 
0351     for (i = size; i > 0; i--)
0352         value = (value << 8) | ptr[i - 1];
0353 
0354     return value;
0355 }
0356 
0357 /*
0358  * Helper to write info frame
0359  *
0360  * @hdmi: pointer on the hdmi internal structure
0361  * @data: infoframe to write
0362  * @size: size to write
0363  */
0364 static void hdmi_infoframe_write_infopack(struct sti_hdmi *hdmi,
0365                       const u8 *data,
0366                       size_t size)
0367 {
0368     const u8 *ptr = data;
0369     u32 val, slot, mode, i;
0370     u32 head_offset, pack_offset;
0371 
0372     switch (*ptr) {
0373     case HDMI_INFOFRAME_TYPE_AVI:
0374         slot = HDMI_IFRAME_SLOT_AVI;
0375         mode = HDMI_IFRAME_FIELD;
0376         head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI);
0377         pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI);
0378         break;
0379     case HDMI_INFOFRAME_TYPE_AUDIO:
0380         slot = HDMI_IFRAME_SLOT_AUDIO;
0381         mode = HDMI_IFRAME_FRAME;
0382         head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO);
0383         pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO);
0384         break;
0385     case HDMI_INFOFRAME_TYPE_VENDOR:
0386         slot = HDMI_IFRAME_SLOT_VENDOR;
0387         mode = HDMI_IFRAME_FRAME;
0388         head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_VENDOR);
0389         pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_VENDOR);
0390         break;
0391     default:
0392         DRM_ERROR("unsupported infoframe type: %#x\n", *ptr);
0393         return;
0394     }
0395 
0396     /* Disable transmission slot for updated infoframe */
0397     val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
0398     val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot);
0399     hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
0400 
0401     val = HDMI_INFOFRAME_HEADER_TYPE(*ptr++);
0402     val |= HDMI_INFOFRAME_HEADER_VERSION(*ptr++);
0403     val |= HDMI_INFOFRAME_HEADER_LEN(*ptr++);
0404     writel(val, hdmi->regs + head_offset);
0405 
0406     /*
0407      * Each subpack contains 4 bytes
0408      * The First Bytes of the first subpacket must contain the checksum
0409      * Packet size is increase by one.
0410      */
0411     size = size - HDMI_INFOFRAME_HEADER_SIZE + 1;
0412     for (i = 0; i < size; i += sizeof(u32)) {
0413         size_t num;
0414 
0415         num = min_t(size_t, size - i, sizeof(u32));
0416         val = hdmi_infoframe_subpack(ptr, num);
0417         ptr += sizeof(u32);
0418         writel(val, hdmi->regs + pack_offset + i);
0419     }
0420 
0421     /* Enable transmission slot for updated infoframe */
0422     val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
0423     val |= HDMI_IFRAME_CFG_DI_N(mode, slot);
0424     hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
0425 }
0426 
0427 /*
0428  * Prepare and configure the AVI infoframe
0429  *
0430  * AVI infoframe are transmitted at least once per two video field and
0431  * contains information about HDMI transmission mode such as color space,
0432  * colorimetry, ...
0433  *
0434  * @hdmi: pointer on the hdmi internal structure
0435  *
0436  * Return negative value if error occurs
0437  */
0438 static int hdmi_avi_infoframe_config(struct sti_hdmi *hdmi)
0439 {
0440     struct drm_display_mode *mode = &hdmi->mode;
0441     struct hdmi_avi_infoframe infoframe;
0442     u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
0443     int ret;
0444 
0445     DRM_DEBUG_DRIVER("\n");
0446 
0447     ret = drm_hdmi_avi_infoframe_from_display_mode(&infoframe,
0448                                hdmi->drm_connector, mode);
0449     if (ret < 0) {
0450         DRM_ERROR("failed to setup AVI infoframe: %d\n", ret);
0451         return ret;
0452     }
0453 
0454     /* fixed infoframe configuration not linked to the mode */
0455     infoframe.colorspace = hdmi->colorspace;
0456     infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
0457     infoframe.colorimetry = HDMI_COLORIMETRY_NONE;
0458 
0459     ret = hdmi_avi_infoframe_pack(&infoframe, buffer, sizeof(buffer));
0460     if (ret < 0) {
0461         DRM_ERROR("failed to pack AVI infoframe: %d\n", ret);
0462         return ret;
0463     }
0464 
0465     hdmi_infoframe_write_infopack(hdmi, buffer, ret);
0466 
0467     return 0;
0468 }
0469 
0470 /*
0471  * Prepare and configure the AUDIO infoframe
0472  *
0473  * AUDIO infoframe are transmitted once per frame and
0474  * contains information about HDMI transmission mode such as audio codec,
0475  * sample size, ...
0476  *
0477  * @hdmi: pointer on the hdmi internal structure
0478  *
0479  * Return negative value if error occurs
0480  */
0481 static int hdmi_audio_infoframe_config(struct sti_hdmi *hdmi)
0482 {
0483     struct hdmi_audio_params *audio = &hdmi->audio;
0484     u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
0485     int ret, val;
0486 
0487     DRM_DEBUG_DRIVER("enter %s, AIF %s\n", __func__,
0488              audio->enabled ? "enable" : "disable");
0489     if (audio->enabled) {
0490         /* set audio parameters stored*/
0491         ret = hdmi_audio_infoframe_pack(&audio->cea, buffer,
0492                         sizeof(buffer));
0493         if (ret < 0) {
0494             DRM_ERROR("failed to pack audio infoframe: %d\n", ret);
0495             return ret;
0496         }
0497         hdmi_infoframe_write_infopack(hdmi, buffer, ret);
0498     } else {
0499         /*disable audio info frame transmission */
0500         val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
0501         val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK,
0502                          HDMI_IFRAME_SLOT_AUDIO);
0503         hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
0504     }
0505 
0506     return 0;
0507 }
0508 
0509 /*
0510  * Prepare and configure the VS infoframe
0511  *
0512  * Vendor Specific infoframe are transmitted once per frame and
0513  * contains vendor specific information.
0514  *
0515  * @hdmi: pointer on the hdmi internal structure
0516  *
0517  * Return negative value if error occurs
0518  */
0519 #define HDMI_VENDOR_INFOFRAME_MAX_SIZE 6
0520 static int hdmi_vendor_infoframe_config(struct sti_hdmi *hdmi)
0521 {
0522     struct drm_display_mode *mode = &hdmi->mode;
0523     struct hdmi_vendor_infoframe infoframe;
0524     u8 buffer[HDMI_INFOFRAME_HEADER_SIZE + HDMI_VENDOR_INFOFRAME_MAX_SIZE];
0525     int ret;
0526 
0527     DRM_DEBUG_DRIVER("\n");
0528 
0529     ret = drm_hdmi_vendor_infoframe_from_display_mode(&infoframe,
0530                               hdmi->drm_connector,
0531                               mode);
0532     if (ret < 0) {
0533         /*
0534          * Going into that statement does not means vendor infoframe
0535          * fails. It just informed us that vendor infoframe is not
0536          * needed for the selected mode. Only  4k or stereoscopic 3D
0537          * mode requires vendor infoframe. So just simply return 0.
0538          */
0539         return 0;
0540     }
0541 
0542     ret = hdmi_vendor_infoframe_pack(&infoframe, buffer, sizeof(buffer));
0543     if (ret < 0) {
0544         DRM_ERROR("failed to pack VS infoframe: %d\n", ret);
0545         return ret;
0546     }
0547 
0548     hdmi_infoframe_write_infopack(hdmi, buffer, ret);
0549 
0550     return 0;
0551 }
0552 
0553 #define HDMI_TIMEOUT_SWRESET  100   /*milliseconds */
0554 
0555 /*
0556  * Software reset of the hdmi subsystem
0557  *
0558  * @hdmi: pointer on the hdmi internal structure
0559  *
0560  */
0561 static void hdmi_swreset(struct sti_hdmi *hdmi)
0562 {
0563     u32 val;
0564 
0565     DRM_DEBUG_DRIVER("\n");
0566 
0567     /* Enable hdmi_audio clock only during hdmi reset */
0568     if (clk_prepare_enable(hdmi->clk_audio))
0569         DRM_INFO("Failed to prepare/enable hdmi_audio clk\n");
0570 
0571     /* Sw reset */
0572     hdmi->event_received = false;
0573 
0574     val = hdmi_read(hdmi, HDMI_CFG);
0575     val |= HDMI_CFG_SW_RST_EN;
0576     hdmi_write(hdmi, val, HDMI_CFG);
0577 
0578     /* Wait reset completed */
0579     wait_event_interruptible_timeout(hdmi->wait_event,
0580                      hdmi->event_received,
0581                      msecs_to_jiffies
0582                      (HDMI_TIMEOUT_SWRESET));
0583 
0584     /*
0585      * HDMI_STA_SW_RST bit is set to '1' when SW_RST bit in HDMI_CFG is
0586      * set to '1' and clk_audio is running.
0587      */
0588     if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_SW_RST) == 0)
0589         DRM_DEBUG_DRIVER("Warning: HDMI sw reset timeout occurs\n");
0590 
0591     val = hdmi_read(hdmi, HDMI_CFG);
0592     val &= ~HDMI_CFG_SW_RST_EN;
0593     hdmi_write(hdmi, val, HDMI_CFG);
0594 
0595     /* Disable hdmi_audio clock. Not used anymore for drm purpose */
0596     clk_disable_unprepare(hdmi->clk_audio);
0597 }
0598 
0599 #define DBGFS_PRINT_STR(str1, str2) seq_printf(s, "%-24s %s\n", str1, str2)
0600 #define DBGFS_PRINT_INT(str1, int2) seq_printf(s, "%-24s %d\n", str1, int2)
0601 #define DBGFS_DUMP(str, reg) seq_printf(s, "%s  %-25s 0x%08X", str, #reg, \
0602                     hdmi_read(hdmi, reg))
0603 #define DBGFS_DUMP_DI(reg, slot) DBGFS_DUMP("\n", reg(slot))
0604 
0605 static void hdmi_dbg_cfg(struct seq_file *s, int val)
0606 {
0607     int tmp;
0608 
0609     seq_putc(s, '\t');
0610     tmp = val & HDMI_CFG_HDMI_NOT_DVI;
0611     DBGFS_PRINT_STR("mode:", tmp ? "HDMI" : "DVI");
0612     seq_puts(s, "\t\t\t\t\t");
0613     tmp = val & HDMI_CFG_HDCP_EN;
0614     DBGFS_PRINT_STR("HDCP:", tmp ? "enable" : "disable");
0615     seq_puts(s, "\t\t\t\t\t");
0616     tmp = val & HDMI_CFG_ESS_NOT_OESS;
0617     DBGFS_PRINT_STR("HDCP mode:", tmp ? "ESS enable" : "OESS enable");
0618     seq_puts(s, "\t\t\t\t\t");
0619     tmp = val & HDMI_CFG_H_SYNC_POL_NEG;
0620     DBGFS_PRINT_STR("Hsync polarity:", tmp ? "inverted" : "normal");
0621     seq_puts(s, "\t\t\t\t\t");
0622     tmp = val & HDMI_CFG_V_SYNC_POL_NEG;
0623     DBGFS_PRINT_STR("Vsync polarity:", tmp ? "inverted" : "normal");
0624     seq_puts(s, "\t\t\t\t\t");
0625     tmp = val & HDMI_CFG_422_EN;
0626     DBGFS_PRINT_STR("YUV422 format:", tmp ? "enable" : "disable");
0627 }
0628 
0629 static void hdmi_dbg_sta(struct seq_file *s, int val)
0630 {
0631     int tmp;
0632 
0633     seq_putc(s, '\t');
0634     tmp = (val & HDMI_STA_DLL_LCK);
0635     DBGFS_PRINT_STR("pll:", tmp ? "locked" : "not locked");
0636     seq_puts(s, "\t\t\t\t\t");
0637     tmp = (val & HDMI_STA_HOT_PLUG);
0638     DBGFS_PRINT_STR("hdmi cable:", tmp ? "connected" : "not connected");
0639 }
0640 
0641 static void hdmi_dbg_sw_di_cfg(struct seq_file *s, int val)
0642 {
0643     int tmp;
0644     char *const en_di[] = {"no transmission",
0645                    "single transmission",
0646                    "once every field",
0647                    "once every frame"};
0648 
0649     seq_putc(s, '\t');
0650     tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 1));
0651     DBGFS_PRINT_STR("Data island 1:", en_di[tmp]);
0652     seq_puts(s, "\t\t\t\t\t");
0653     tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 2)) >> 4;
0654     DBGFS_PRINT_STR("Data island 2:", en_di[tmp]);
0655     seq_puts(s, "\t\t\t\t\t");
0656     tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 3)) >> 8;
0657     DBGFS_PRINT_STR("Data island 3:", en_di[tmp]);
0658     seq_puts(s, "\t\t\t\t\t");
0659     tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 4)) >> 12;
0660     DBGFS_PRINT_STR("Data island 4:", en_di[tmp]);
0661     seq_puts(s, "\t\t\t\t\t");
0662     tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 5)) >> 16;
0663     DBGFS_PRINT_STR("Data island 5:", en_di[tmp]);
0664     seq_puts(s, "\t\t\t\t\t");
0665     tmp = (val & HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, 6)) >> 20;
0666     DBGFS_PRINT_STR("Data island 6:", en_di[tmp]);
0667 }
0668 
0669 static int hdmi_dbg_show(struct seq_file *s, void *data)
0670 {
0671     struct drm_info_node *node = s->private;
0672     struct sti_hdmi *hdmi = (struct sti_hdmi *)node->info_ent->data;
0673 
0674     seq_printf(s, "HDMI: (vaddr = 0x%p)", hdmi->regs);
0675     DBGFS_DUMP("\n", HDMI_CFG);
0676     hdmi_dbg_cfg(s, hdmi_read(hdmi, HDMI_CFG));
0677     DBGFS_DUMP("", HDMI_INT_EN);
0678     DBGFS_DUMP("\n", HDMI_STA);
0679     hdmi_dbg_sta(s, hdmi_read(hdmi, HDMI_STA));
0680     DBGFS_DUMP("", HDMI_ACTIVE_VID_XMIN);
0681     seq_putc(s, '\t');
0682     DBGFS_PRINT_INT("Xmin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMIN));
0683     DBGFS_DUMP("", HDMI_ACTIVE_VID_XMAX);
0684     seq_putc(s, '\t');
0685     DBGFS_PRINT_INT("Xmax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_XMAX));
0686     DBGFS_DUMP("", HDMI_ACTIVE_VID_YMIN);
0687     seq_putc(s, '\t');
0688     DBGFS_PRINT_INT("Ymin:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMIN));
0689     DBGFS_DUMP("", HDMI_ACTIVE_VID_YMAX);
0690     seq_putc(s, '\t');
0691     DBGFS_PRINT_INT("Ymax:", hdmi_read(hdmi, HDMI_ACTIVE_VID_YMAX));
0692     DBGFS_DUMP("", HDMI_SW_DI_CFG);
0693     hdmi_dbg_sw_di_cfg(s, hdmi_read(hdmi, HDMI_SW_DI_CFG));
0694 
0695     DBGFS_DUMP("\n", HDMI_AUDIO_CFG);
0696     DBGFS_DUMP("\n", HDMI_SPDIF_FIFO_STATUS);
0697     DBGFS_DUMP("\n", HDMI_AUDN);
0698 
0699     seq_printf(s, "\n AVI Infoframe (Data Island slot N=%d):",
0700            HDMI_IFRAME_SLOT_AVI);
0701     DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AVI);
0702     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AVI);
0703     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AVI);
0704     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AVI);
0705     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AVI);
0706     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AVI);
0707     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AVI);
0708     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AVI);
0709     seq_printf(s, "\n\n AUDIO Infoframe (Data Island slot N=%d):",
0710            HDMI_IFRAME_SLOT_AUDIO);
0711     DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_AUDIO);
0712     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_AUDIO);
0713     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_AUDIO);
0714     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_AUDIO);
0715     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_AUDIO);
0716     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_AUDIO);
0717     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_AUDIO);
0718     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_AUDIO);
0719     seq_printf(s, "\n\n VENDOR SPECIFIC Infoframe (Data Island slot N=%d):",
0720            HDMI_IFRAME_SLOT_VENDOR);
0721     DBGFS_DUMP_DI(HDMI_SW_DI_N_HEAD_WORD, HDMI_IFRAME_SLOT_VENDOR);
0722     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD0, HDMI_IFRAME_SLOT_VENDOR);
0723     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD1, HDMI_IFRAME_SLOT_VENDOR);
0724     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD2, HDMI_IFRAME_SLOT_VENDOR);
0725     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD3, HDMI_IFRAME_SLOT_VENDOR);
0726     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD4, HDMI_IFRAME_SLOT_VENDOR);
0727     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD5, HDMI_IFRAME_SLOT_VENDOR);
0728     DBGFS_DUMP_DI(HDMI_SW_DI_N_PKT_WORD6, HDMI_IFRAME_SLOT_VENDOR);
0729     seq_putc(s, '\n');
0730     return 0;
0731 }
0732 
0733 static struct drm_info_list hdmi_debugfs_files[] = {
0734     { "hdmi", hdmi_dbg_show, 0, NULL },
0735 };
0736 
0737 static void hdmi_debugfs_init(struct sti_hdmi *hdmi, struct drm_minor *minor)
0738 {
0739     unsigned int i;
0740 
0741     for (i = 0; i < ARRAY_SIZE(hdmi_debugfs_files); i++)
0742         hdmi_debugfs_files[i].data = hdmi;
0743 
0744     drm_debugfs_create_files(hdmi_debugfs_files,
0745                  ARRAY_SIZE(hdmi_debugfs_files),
0746                  minor->debugfs_root, minor);
0747 }
0748 
0749 static void sti_hdmi_disable(struct drm_bridge *bridge)
0750 {
0751     struct sti_hdmi *hdmi = bridge->driver_private;
0752 
0753     u32 val = hdmi_read(hdmi, HDMI_CFG);
0754 
0755     if (!hdmi->enabled)
0756         return;
0757 
0758     DRM_DEBUG_DRIVER("\n");
0759 
0760     /* Disable HDMI */
0761     val &= ~HDMI_CFG_DEVICE_EN;
0762     hdmi_write(hdmi, val, HDMI_CFG);
0763 
0764     hdmi_write(hdmi, 0xffffffff, HDMI_INT_CLR);
0765 
0766     /* Stop the phy */
0767     hdmi->phy_ops->stop(hdmi);
0768 
0769     /* Reset info frame transmission */
0770     hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AVI);
0771     hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_AUDIO);
0772     hdmi_infoframe_reset(hdmi, HDMI_IFRAME_SLOT_VENDOR);
0773 
0774     /* Set the default channel data to be a dark red */
0775     hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL0_DAT);
0776     hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL1_DAT);
0777     hdmi_write(hdmi, 0x0060, HDMI_DFLT_CHL2_DAT);
0778 
0779     /* Disable/unprepare hdmi clock */
0780     clk_disable_unprepare(hdmi->clk_phy);
0781     clk_disable_unprepare(hdmi->clk_tmds);
0782     clk_disable_unprepare(hdmi->clk_pix);
0783 
0784     hdmi->enabled = false;
0785 
0786     cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID);
0787 }
0788 
0789 /*
0790  * sti_hdmi_audio_get_non_coherent_n() - get N parameter for non-coherent
0791  * clocks. None-coherent clocks means that audio and TMDS clocks have not the
0792  * same source (drifts between clocks). In this case assumption is that CTS is
0793  * automatically calculated by hardware.
0794  *
0795  * @audio_fs: audio frame clock frequency in Hz
0796  *
0797  * Values computed are based on table described in HDMI specification 1.4b
0798  *
0799  * Returns n value.
0800  */
0801 static int sti_hdmi_audio_get_non_coherent_n(unsigned int audio_fs)
0802 {
0803     unsigned int n;
0804 
0805     switch (audio_fs) {
0806     case 32000:
0807         n = 4096;
0808         break;
0809     case 44100:
0810         n = 6272;
0811         break;
0812     case 48000:
0813         n = 6144;
0814         break;
0815     case 88200:
0816         n = 6272 * 2;
0817         break;
0818     case 96000:
0819         n = 6144 * 2;
0820         break;
0821     case 176400:
0822         n = 6272 * 4;
0823         break;
0824     case 192000:
0825         n = 6144 * 4;
0826         break;
0827     default:
0828         /* Not pre-defined, recommended value: 128 * fs / 1000 */
0829         n = (audio_fs * 128) / 1000;
0830     }
0831 
0832     return n;
0833 }
0834 
0835 static int hdmi_audio_configure(struct sti_hdmi *hdmi)
0836 {
0837     int audio_cfg, n;
0838     struct hdmi_audio_params *params = &hdmi->audio;
0839     struct hdmi_audio_infoframe *info = &params->cea;
0840 
0841     DRM_DEBUG_DRIVER("\n");
0842 
0843     if (!hdmi->enabled)
0844         return 0;
0845 
0846     /* update N parameter */
0847     n = sti_hdmi_audio_get_non_coherent_n(params->sample_rate);
0848 
0849     DRM_DEBUG_DRIVER("Audio rate = %d Hz, TMDS clock = %d Hz, n = %d\n",
0850              params->sample_rate, hdmi->mode.clock * 1000, n);
0851     hdmi_write(hdmi, n, HDMI_AUDN);
0852 
0853     /* update HDMI registers according to configuration */
0854     audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID |
0855             HDMI_AUD_CFG_ONE_BIT_INVALID;
0856 
0857     switch (info->channels) {
0858     case 8:
0859         audio_cfg |= HDMI_AUD_CFG_CH78_VALID;
0860         fallthrough;
0861     case 6:
0862         audio_cfg |= HDMI_AUD_CFG_CH56_VALID;
0863         fallthrough;
0864     case 4:
0865         audio_cfg |= HDMI_AUD_CFG_CH34_VALID | HDMI_AUD_CFG_8CH;
0866         fallthrough;
0867     case 2:
0868         audio_cfg |= HDMI_AUD_CFG_CH12_VALID;
0869         break;
0870     default:
0871         DRM_ERROR("ERROR: Unsupported number of channels (%d)!\n",
0872               info->channels);
0873         return -EINVAL;
0874     }
0875 
0876     hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG);
0877 
0878     return hdmi_audio_infoframe_config(hdmi);
0879 }
0880 
0881 static void sti_hdmi_pre_enable(struct drm_bridge *bridge)
0882 {
0883     struct sti_hdmi *hdmi = bridge->driver_private;
0884 
0885     DRM_DEBUG_DRIVER("\n");
0886 
0887     if (hdmi->enabled)
0888         return;
0889 
0890     /* Prepare/enable clocks */
0891     if (clk_prepare_enable(hdmi->clk_pix))
0892         DRM_ERROR("Failed to prepare/enable hdmi_pix clk\n");
0893     if (clk_prepare_enable(hdmi->clk_tmds))
0894         DRM_ERROR("Failed to prepare/enable hdmi_tmds clk\n");
0895     if (clk_prepare_enable(hdmi->clk_phy))
0896         DRM_ERROR("Failed to prepare/enable hdmi_rejection_pll clk\n");
0897 
0898     hdmi->enabled = true;
0899 
0900     /* Program hdmi serializer and start phy */
0901     if (!hdmi->phy_ops->start(hdmi)) {
0902         DRM_ERROR("Unable to start hdmi phy\n");
0903         return;
0904     }
0905 
0906     /* Program hdmi active area */
0907     hdmi_active_area(hdmi);
0908 
0909     /* Enable working interrupts */
0910     hdmi_write(hdmi, HDMI_WORKING_INT, HDMI_INT_EN);
0911 
0912     /* Program hdmi config */
0913     hdmi_config(hdmi);
0914 
0915     /* Program AVI infoframe */
0916     if (hdmi_avi_infoframe_config(hdmi))
0917         DRM_ERROR("Unable to configure AVI infoframe\n");
0918 
0919     if (hdmi->audio.enabled) {
0920         if (hdmi_audio_configure(hdmi))
0921             DRM_ERROR("Unable to configure audio\n");
0922     } else {
0923         hdmi_audio_infoframe_config(hdmi);
0924     }
0925 
0926     /* Program VS infoframe */
0927     if (hdmi_vendor_infoframe_config(hdmi))
0928         DRM_ERROR("Unable to configure VS infoframe\n");
0929 
0930     /* Sw reset */
0931     hdmi_swreset(hdmi);
0932 }
0933 
0934 static void sti_hdmi_set_mode(struct drm_bridge *bridge,
0935                   const struct drm_display_mode *mode,
0936                   const struct drm_display_mode *adjusted_mode)
0937 {
0938     struct sti_hdmi *hdmi = bridge->driver_private;
0939     int ret;
0940 
0941     DRM_DEBUG_DRIVER("\n");
0942 
0943     /* Copy the drm display mode in the connector local structure */
0944     memcpy(&hdmi->mode, mode, sizeof(struct drm_display_mode));
0945 
0946     /* Update clock framerate according to the selected mode */
0947     ret = clk_set_rate(hdmi->clk_pix, mode->clock * 1000);
0948     if (ret < 0) {
0949         DRM_ERROR("Cannot set rate (%dHz) for hdmi_pix clk\n",
0950               mode->clock * 1000);
0951         return;
0952     }
0953     ret = clk_set_rate(hdmi->clk_phy, mode->clock * 1000);
0954     if (ret < 0) {
0955         DRM_ERROR("Cannot set rate (%dHz) for hdmi_rejection_pll clk\n",
0956               mode->clock * 1000);
0957         return;
0958     }
0959 }
0960 
0961 static void sti_hdmi_bridge_nope(struct drm_bridge *bridge)
0962 {
0963     /* do nothing */
0964 }
0965 
0966 static const struct drm_bridge_funcs sti_hdmi_bridge_funcs = {
0967     .pre_enable = sti_hdmi_pre_enable,
0968     .enable = sti_hdmi_bridge_nope,
0969     .disable = sti_hdmi_disable,
0970     .post_disable = sti_hdmi_bridge_nope,
0971     .mode_set = sti_hdmi_set_mode,
0972 };
0973 
0974 static int sti_hdmi_connector_get_modes(struct drm_connector *connector)
0975 {
0976     struct sti_hdmi_connector *hdmi_connector
0977         = to_sti_hdmi_connector(connector);
0978     struct sti_hdmi *hdmi = hdmi_connector->hdmi;
0979     struct edid *edid;
0980     int count;
0981 
0982     DRM_DEBUG_DRIVER("\n");
0983 
0984     edid = drm_get_edid(connector, hdmi->ddc_adapt);
0985     if (!edid)
0986         goto fail;
0987 
0988     hdmi->hdmi_monitor = drm_detect_hdmi_monitor(edid);
0989     DRM_DEBUG_KMS("%s : %dx%d cm\n",
0990               (hdmi->hdmi_monitor ? "hdmi monitor" : "dvi monitor"),
0991               edid->width_cm, edid->height_cm);
0992     cec_notifier_set_phys_addr_from_edid(hdmi->notifier, edid);
0993 
0994     count = drm_add_edid_modes(connector, edid);
0995     drm_connector_update_edid_property(connector, edid);
0996 
0997     kfree(edid);
0998     return count;
0999 
1000 fail:
1001     DRM_ERROR("Can't read HDMI EDID\n");
1002     return 0;
1003 }
1004 
1005 #define CLK_TOLERANCE_HZ 50
1006 
1007 static int sti_hdmi_connector_mode_valid(struct drm_connector *connector,
1008                     struct drm_display_mode *mode)
1009 {
1010     int target = mode->clock * 1000;
1011     int target_min = target - CLK_TOLERANCE_HZ;
1012     int target_max = target + CLK_TOLERANCE_HZ;
1013     int result;
1014     struct sti_hdmi_connector *hdmi_connector
1015         = to_sti_hdmi_connector(connector);
1016     struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1017 
1018 
1019     result = clk_round_rate(hdmi->clk_pix, target);
1020 
1021     DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
1022              target, result);
1023 
1024     if ((result < target_min) || (result > target_max)) {
1025         DRM_DEBUG_DRIVER("hdmi pixclk=%d not supported\n", target);
1026         return MODE_BAD;
1027     }
1028 
1029     return MODE_OK;
1030 }
1031 
1032 static const
1033 struct drm_connector_helper_funcs sti_hdmi_connector_helper_funcs = {
1034     .get_modes = sti_hdmi_connector_get_modes,
1035     .mode_valid = sti_hdmi_connector_mode_valid,
1036 };
1037 
1038 /* get detection status of display device */
1039 static enum drm_connector_status
1040 sti_hdmi_connector_detect(struct drm_connector *connector, bool force)
1041 {
1042     struct sti_hdmi_connector *hdmi_connector
1043         = to_sti_hdmi_connector(connector);
1044     struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1045 
1046     DRM_DEBUG_DRIVER("\n");
1047 
1048     if (hdmi->hpd) {
1049         DRM_DEBUG_DRIVER("hdmi cable connected\n");
1050         return connector_status_connected;
1051     }
1052 
1053     DRM_DEBUG_DRIVER("hdmi cable disconnected\n");
1054     cec_notifier_set_phys_addr(hdmi->notifier, CEC_PHYS_ADDR_INVALID);
1055     return connector_status_disconnected;
1056 }
1057 
1058 static void sti_hdmi_connector_init_property(struct drm_device *drm_dev,
1059                          struct drm_connector *connector)
1060 {
1061     struct sti_hdmi_connector *hdmi_connector
1062         = to_sti_hdmi_connector(connector);
1063     struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1064     struct drm_property *prop;
1065 
1066     /* colorspace property */
1067     hdmi->colorspace = DEFAULT_COLORSPACE_MODE;
1068     prop = drm_property_create_enum(drm_dev, 0, "colorspace",
1069                     colorspace_mode_names,
1070                     ARRAY_SIZE(colorspace_mode_names));
1071     if (!prop) {
1072         DRM_ERROR("fails to create colorspace property\n");
1073         return;
1074     }
1075     hdmi_connector->colorspace_property = prop;
1076     drm_object_attach_property(&connector->base, prop, hdmi->colorspace);
1077 }
1078 
1079 static int
1080 sti_hdmi_connector_set_property(struct drm_connector *connector,
1081                 struct drm_connector_state *state,
1082                 struct drm_property *property,
1083                 uint64_t val)
1084 {
1085     struct sti_hdmi_connector *hdmi_connector
1086         = to_sti_hdmi_connector(connector);
1087     struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1088 
1089     if (property == hdmi_connector->colorspace_property) {
1090         hdmi->colorspace = val;
1091         return 0;
1092     }
1093 
1094     DRM_ERROR("failed to set hdmi connector property\n");
1095     return -EINVAL;
1096 }
1097 
1098 static int
1099 sti_hdmi_connector_get_property(struct drm_connector *connector,
1100                 const struct drm_connector_state *state,
1101                 struct drm_property *property,
1102                 uint64_t *val)
1103 {
1104     struct sti_hdmi_connector *hdmi_connector
1105         = to_sti_hdmi_connector(connector);
1106     struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1107 
1108     if (property == hdmi_connector->colorspace_property) {
1109         *val = hdmi->colorspace;
1110         return 0;
1111     }
1112 
1113     DRM_ERROR("failed to get hdmi connector property\n");
1114     return -EINVAL;
1115 }
1116 
1117 static int sti_hdmi_late_register(struct drm_connector *connector)
1118 {
1119     struct sti_hdmi_connector *hdmi_connector
1120         = to_sti_hdmi_connector(connector);
1121     struct sti_hdmi *hdmi = hdmi_connector->hdmi;
1122 
1123     hdmi_debugfs_init(hdmi, hdmi->drm_dev->primary);
1124 
1125     return 0;
1126 }
1127 
1128 static const struct drm_connector_funcs sti_hdmi_connector_funcs = {
1129     .fill_modes = drm_helper_probe_single_connector_modes,
1130     .detect = sti_hdmi_connector_detect,
1131     .destroy = drm_connector_cleanup,
1132     .reset = drm_atomic_helper_connector_reset,
1133     .atomic_set_property = sti_hdmi_connector_set_property,
1134     .atomic_get_property = sti_hdmi_connector_get_property,
1135     .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
1136     .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
1137     .late_register = sti_hdmi_late_register,
1138 };
1139 
1140 static struct drm_encoder *sti_hdmi_find_encoder(struct drm_device *dev)
1141 {
1142     struct drm_encoder *encoder;
1143 
1144     list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
1145         if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
1146             return encoder;
1147     }
1148 
1149     return NULL;
1150 }
1151 
1152 static void hdmi_audio_shutdown(struct device *dev, void *data)
1153 {
1154     struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1155     int audio_cfg;
1156 
1157     DRM_DEBUG_DRIVER("\n");
1158 
1159     /* disable audio */
1160     audio_cfg = HDMI_AUD_CFG_SPDIF_DIV_2 | HDMI_AUD_CFG_DTS_INVALID |
1161             HDMI_AUD_CFG_ONE_BIT_INVALID;
1162     hdmi_write(hdmi, audio_cfg, HDMI_AUDIO_CFG);
1163 
1164     hdmi->audio.enabled = false;
1165     hdmi_audio_infoframe_config(hdmi);
1166 }
1167 
1168 static int hdmi_audio_hw_params(struct device *dev,
1169                 void *data,
1170                 struct hdmi_codec_daifmt *daifmt,
1171                 struct hdmi_codec_params *params)
1172 {
1173     struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1174     int ret;
1175 
1176     DRM_DEBUG_DRIVER("\n");
1177 
1178     if ((daifmt->fmt != HDMI_I2S) || daifmt->bit_clk_inv ||
1179         daifmt->frame_clk_inv || daifmt->bit_clk_provider ||
1180         daifmt->frame_clk_provider) {
1181         dev_err(dev, "%s: Bad flags %d %d %d %d\n", __func__,
1182             daifmt->bit_clk_inv, daifmt->frame_clk_inv,
1183             daifmt->bit_clk_provider,
1184             daifmt->frame_clk_provider);
1185         return -EINVAL;
1186     }
1187 
1188     hdmi->audio.sample_width = params->sample_width;
1189     hdmi->audio.sample_rate = params->sample_rate;
1190     hdmi->audio.cea = params->cea;
1191 
1192     hdmi->audio.enabled = true;
1193 
1194     ret = hdmi_audio_configure(hdmi);
1195     if (ret < 0)
1196         return ret;
1197 
1198     return 0;
1199 }
1200 
1201 static int hdmi_audio_mute(struct device *dev, void *data,
1202                bool enable, int direction)
1203 {
1204     struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1205 
1206     DRM_DEBUG_DRIVER("%s\n", enable ? "enable" : "disable");
1207 
1208     if (enable)
1209         hdmi_write(hdmi, HDMI_SAMPLE_FLAT_ALL, HDMI_SAMPLE_FLAT_MASK);
1210     else
1211         hdmi_write(hdmi, HDMI_SAMPLE_FLAT_NO, HDMI_SAMPLE_FLAT_MASK);
1212 
1213     return 0;
1214 }
1215 
1216 static int hdmi_audio_get_eld(struct device *dev, void *data, uint8_t *buf, size_t len)
1217 {
1218     struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1219     struct drm_connector *connector = hdmi->drm_connector;
1220 
1221     DRM_DEBUG_DRIVER("\n");
1222     memcpy(buf, connector->eld, min(sizeof(connector->eld), len));
1223 
1224     return 0;
1225 }
1226 
1227 static const struct hdmi_codec_ops audio_codec_ops = {
1228     .hw_params = hdmi_audio_hw_params,
1229     .audio_shutdown = hdmi_audio_shutdown,
1230     .mute_stream = hdmi_audio_mute,
1231     .get_eld = hdmi_audio_get_eld,
1232     .no_capture_mute = 1,
1233 };
1234 
1235 static int sti_hdmi_register_audio_driver(struct device *dev,
1236                       struct sti_hdmi *hdmi)
1237 {
1238     struct hdmi_codec_pdata codec_data = {
1239         .ops = &audio_codec_ops,
1240         .max_i2s_channels = 8,
1241         .i2s = 1,
1242     };
1243 
1244     DRM_DEBUG_DRIVER("\n");
1245 
1246     hdmi->audio.enabled = false;
1247 
1248     hdmi->audio_pdev = platform_device_register_data(
1249         dev, HDMI_CODEC_DRV_NAME, PLATFORM_DEVID_AUTO,
1250         &codec_data, sizeof(codec_data));
1251 
1252     if (IS_ERR(hdmi->audio_pdev))
1253         return PTR_ERR(hdmi->audio_pdev);
1254 
1255     DRM_INFO("%s Driver bound %s\n", HDMI_CODEC_DRV_NAME, dev_name(dev));
1256 
1257     return 0;
1258 }
1259 
1260 static int sti_hdmi_bind(struct device *dev, struct device *master, void *data)
1261 {
1262     struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1263     struct drm_device *drm_dev = data;
1264     struct drm_encoder *encoder;
1265     struct sti_hdmi_connector *connector;
1266     struct cec_connector_info conn_info;
1267     struct drm_connector *drm_connector;
1268     struct drm_bridge *bridge;
1269     int err;
1270 
1271     /* Set the drm device handle */
1272     hdmi->drm_dev = drm_dev;
1273 
1274     encoder = sti_hdmi_find_encoder(drm_dev);
1275     if (!encoder)
1276         return -EINVAL;
1277 
1278     connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL);
1279     if (!connector)
1280         return -EINVAL;
1281 
1282     connector->hdmi = hdmi;
1283 
1284     bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
1285     if (!bridge)
1286         return -EINVAL;
1287 
1288     bridge->driver_private = hdmi;
1289     bridge->funcs = &sti_hdmi_bridge_funcs;
1290     drm_bridge_attach(encoder, bridge, NULL, 0);
1291 
1292     connector->encoder = encoder;
1293 
1294     drm_connector = (struct drm_connector *)connector;
1295 
1296     drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
1297 
1298     drm_connector_init_with_ddc(drm_dev, drm_connector,
1299                     &sti_hdmi_connector_funcs,
1300                     DRM_MODE_CONNECTOR_HDMIA,
1301                     hdmi->ddc_adapt);
1302     drm_connector_helper_add(drm_connector,
1303             &sti_hdmi_connector_helper_funcs);
1304 
1305     /* initialise property */
1306     sti_hdmi_connector_init_property(drm_dev, drm_connector);
1307 
1308     hdmi->drm_connector = drm_connector;
1309 
1310     err = drm_connector_attach_encoder(drm_connector, encoder);
1311     if (err) {
1312         DRM_ERROR("Failed to attach a connector to a encoder\n");
1313         goto err_sysfs;
1314     }
1315 
1316     err = sti_hdmi_register_audio_driver(dev, hdmi);
1317     if (err) {
1318         DRM_ERROR("Failed to attach an audio codec\n");
1319         goto err_sysfs;
1320     }
1321 
1322     /* Initialize audio infoframe */
1323     err = hdmi_audio_infoframe_init(&hdmi->audio.cea);
1324     if (err) {
1325         DRM_ERROR("Failed to init audio infoframe\n");
1326         goto err_sysfs;
1327     }
1328 
1329     cec_fill_conn_info_from_drm(&conn_info, drm_connector);
1330     hdmi->notifier = cec_notifier_conn_register(&hdmi->dev, NULL,
1331                             &conn_info);
1332     if (!hdmi->notifier) {
1333         hdmi->drm_connector = NULL;
1334         return -ENOMEM;
1335     }
1336 
1337     /* Enable default interrupts */
1338     hdmi_write(hdmi, HDMI_DEFAULT_INT, HDMI_INT_EN);
1339 
1340     return 0;
1341 
1342 err_sysfs:
1343     hdmi->drm_connector = NULL;
1344     return -EINVAL;
1345 }
1346 
1347 static void sti_hdmi_unbind(struct device *dev,
1348         struct device *master, void *data)
1349 {
1350     struct sti_hdmi *hdmi = dev_get_drvdata(dev);
1351 
1352     cec_notifier_conn_unregister(hdmi->notifier);
1353 }
1354 
1355 static const struct component_ops sti_hdmi_ops = {
1356     .bind = sti_hdmi_bind,
1357     .unbind = sti_hdmi_unbind,
1358 };
1359 
1360 static const struct of_device_id hdmi_of_match[] = {
1361     {
1362         .compatible = "st,stih407-hdmi",
1363         .data = &tx3g4c28phy_ops,
1364     }, {
1365         /* end node */
1366     }
1367 };
1368 MODULE_DEVICE_TABLE(of, hdmi_of_match);
1369 
1370 static int sti_hdmi_probe(struct platform_device *pdev)
1371 {
1372     struct device *dev = &pdev->dev;
1373     struct sti_hdmi *hdmi;
1374     struct device_node *np = dev->of_node;
1375     struct resource *res;
1376     struct device_node *ddc;
1377     int ret;
1378 
1379     DRM_INFO("%s\n", __func__);
1380 
1381     hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
1382     if (!hdmi)
1383         return -ENOMEM;
1384 
1385     ddc = of_parse_phandle(pdev->dev.of_node, "ddc", 0);
1386     if (ddc) {
1387         hdmi->ddc_adapt = of_get_i2c_adapter_by_node(ddc);
1388         of_node_put(ddc);
1389         if (!hdmi->ddc_adapt)
1390             return -EPROBE_DEFER;
1391     }
1392 
1393     hdmi->dev = pdev->dev;
1394 
1395     /* Get resources */
1396     res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi-reg");
1397     if (!res) {
1398         DRM_ERROR("Invalid hdmi resource\n");
1399         ret = -ENOMEM;
1400         goto release_adapter;
1401     }
1402     hdmi->regs = devm_ioremap(dev, res->start, resource_size(res));
1403     if (!hdmi->regs) {
1404         ret = -ENOMEM;
1405         goto release_adapter;
1406     }
1407 
1408     hdmi->phy_ops = (struct hdmi_phy_ops *)
1409         of_match_node(hdmi_of_match, np)->data;
1410 
1411     /* Get clock resources */
1412     hdmi->clk_pix = devm_clk_get(dev, "pix");
1413     if (IS_ERR(hdmi->clk_pix)) {
1414         DRM_ERROR("Cannot get hdmi_pix clock\n");
1415         ret = PTR_ERR(hdmi->clk_pix);
1416         goto release_adapter;
1417     }
1418 
1419     hdmi->clk_tmds = devm_clk_get(dev, "tmds");
1420     if (IS_ERR(hdmi->clk_tmds)) {
1421         DRM_ERROR("Cannot get hdmi_tmds clock\n");
1422         ret = PTR_ERR(hdmi->clk_tmds);
1423         goto release_adapter;
1424     }
1425 
1426     hdmi->clk_phy = devm_clk_get(dev, "phy");
1427     if (IS_ERR(hdmi->clk_phy)) {
1428         DRM_ERROR("Cannot get hdmi_phy clock\n");
1429         ret = PTR_ERR(hdmi->clk_phy);
1430         goto release_adapter;
1431     }
1432 
1433     hdmi->clk_audio = devm_clk_get(dev, "audio");
1434     if (IS_ERR(hdmi->clk_audio)) {
1435         DRM_ERROR("Cannot get hdmi_audio clock\n");
1436         ret = PTR_ERR(hdmi->clk_audio);
1437         goto release_adapter;
1438     }
1439 
1440     hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG;
1441 
1442     init_waitqueue_head(&hdmi->wait_event);
1443 
1444     hdmi->irq = platform_get_irq_byname(pdev, "irq");
1445     if (hdmi->irq < 0) {
1446         DRM_ERROR("Cannot get HDMI irq\n");
1447         ret = hdmi->irq;
1448         goto release_adapter;
1449     }
1450 
1451     ret = devm_request_threaded_irq(dev, hdmi->irq, hdmi_irq,
1452             hdmi_irq_thread, IRQF_ONESHOT, dev_name(dev), hdmi);
1453     if (ret) {
1454         DRM_ERROR("Failed to register HDMI interrupt\n");
1455         goto release_adapter;
1456     }
1457 
1458     hdmi->reset = devm_reset_control_get(dev, "hdmi");
1459     /* Take hdmi out of reset */
1460     if (!IS_ERR(hdmi->reset))
1461         reset_control_deassert(hdmi->reset);
1462 
1463     platform_set_drvdata(pdev, hdmi);
1464 
1465     return component_add(&pdev->dev, &sti_hdmi_ops);
1466 
1467  release_adapter:
1468     i2c_put_adapter(hdmi->ddc_adapt);
1469 
1470     return ret;
1471 }
1472 
1473 static int sti_hdmi_remove(struct platform_device *pdev)
1474 {
1475     struct sti_hdmi *hdmi = dev_get_drvdata(&pdev->dev);
1476 
1477     i2c_put_adapter(hdmi->ddc_adapt);
1478     if (hdmi->audio_pdev)
1479         platform_device_unregister(hdmi->audio_pdev);
1480     component_del(&pdev->dev, &sti_hdmi_ops);
1481 
1482     return 0;
1483 }
1484 
1485 struct platform_driver sti_hdmi_driver = {
1486     .driver = {
1487         .name = "sti-hdmi",
1488         .owner = THIS_MODULE,
1489         .of_match_table = hdmi_of_match,
1490     },
1491     .probe = sti_hdmi_probe,
1492     .remove = sti_hdmi_remove,
1493 };
1494 
1495 MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
1496 MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
1497 MODULE_LICENSE("GPL");
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