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0001 // SPDX-License-Identifier: GPL-2.0
0002 /*
0003  * Copyright (C) STMicroelectronics SA 2014
0004  * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
0005  *          Fabien Dessenne <fabien.dessenne@st.com>
0006  *          for STMicroelectronics.
0007  */
0008 
0009 #include <linux/dma-mapping.h>
0010 #include <linux/of.h>
0011 #include <linux/seq_file.h>
0012 
0013 #include <drm/drm_atomic.h>
0014 #include <drm/drm_device.h>
0015 #include <drm/drm_fb_cma_helper.h>
0016 #include <drm/drm_fourcc.h>
0017 #include <drm/drm_framebuffer.h>
0018 #include <drm/drm_gem_cma_helper.h>
0019 
0020 #include "sti_compositor.h"
0021 #include "sti_gdp.h"
0022 #include "sti_plane.h"
0023 #include "sti_vtg.h"
0024 
0025 #define ALPHASWITCH     BIT(6)
0026 #define ENA_COLOR_FILL  BIT(8)
0027 #define BIGNOTLITTLE    BIT(23)
0028 #define WAIT_NEXT_VSYNC BIT(31)
0029 
0030 /* GDP color formats */
0031 #define GDP_RGB565      0x00
0032 #define GDP_RGB888      0x01
0033 #define GDP_RGB888_32   0x02
0034 #define GDP_XBGR8888    (GDP_RGB888_32 | BIGNOTLITTLE | ALPHASWITCH)
0035 #define GDP_ARGB8565    0x04
0036 #define GDP_ARGB8888    0x05
0037 #define GDP_ABGR8888    (GDP_ARGB8888 | BIGNOTLITTLE | ALPHASWITCH)
0038 #define GDP_ARGB1555    0x06
0039 #define GDP_ARGB4444    0x07
0040 
0041 #define GDP2STR(fmt) { GDP_ ## fmt, #fmt }
0042 
0043 static struct gdp_format_to_str {
0044     int format;
0045     char name[20];
0046 } gdp_format_to_str[] = {
0047         GDP2STR(RGB565),
0048         GDP2STR(RGB888),
0049         GDP2STR(RGB888_32),
0050         GDP2STR(XBGR8888),
0051         GDP2STR(ARGB8565),
0052         GDP2STR(ARGB8888),
0053         GDP2STR(ABGR8888),
0054         GDP2STR(ARGB1555),
0055         GDP2STR(ARGB4444)
0056         };
0057 
0058 #define GAM_GDP_CTL_OFFSET      0x00
0059 #define GAM_GDP_AGC_OFFSET      0x04
0060 #define GAM_GDP_VPO_OFFSET      0x0C
0061 #define GAM_GDP_VPS_OFFSET      0x10
0062 #define GAM_GDP_PML_OFFSET      0x14
0063 #define GAM_GDP_PMP_OFFSET      0x18
0064 #define GAM_GDP_SIZE_OFFSET     0x1C
0065 #define GAM_GDP_NVN_OFFSET      0x24
0066 #define GAM_GDP_KEY1_OFFSET     0x28
0067 #define GAM_GDP_KEY2_OFFSET     0x2C
0068 #define GAM_GDP_PPT_OFFSET      0x34
0069 #define GAM_GDP_CML_OFFSET      0x3C
0070 #define GAM_GDP_MST_OFFSET      0x68
0071 
0072 #define GAM_GDP_ALPHARANGE_255  BIT(5)
0073 #define GAM_GDP_AGC_FULL_RANGE  0x00808080
0074 #define GAM_GDP_PPT_IGNORE      (BIT(1) | BIT(0))
0075 
0076 #define GAM_GDP_SIZE_MAX_WIDTH  3840
0077 #define GAM_GDP_SIZE_MAX_HEIGHT 2160
0078 
0079 #define GDP_NODE_NB_BANK        2
0080 #define GDP_NODE_PER_FIELD      2
0081 
0082 struct sti_gdp_node {
0083     u32 gam_gdp_ctl;
0084     u32 gam_gdp_agc;
0085     u32 reserved1;
0086     u32 gam_gdp_vpo;
0087     u32 gam_gdp_vps;
0088     u32 gam_gdp_pml;
0089     u32 gam_gdp_pmp;
0090     u32 gam_gdp_size;
0091     u32 reserved2;
0092     u32 gam_gdp_nvn;
0093     u32 gam_gdp_key1;
0094     u32 gam_gdp_key2;
0095     u32 reserved3;
0096     u32 gam_gdp_ppt;
0097     u32 reserved4;
0098     u32 gam_gdp_cml;
0099 };
0100 
0101 struct sti_gdp_node_list {
0102     struct sti_gdp_node *top_field;
0103     dma_addr_t top_field_paddr;
0104     struct sti_gdp_node *btm_field;
0105     dma_addr_t btm_field_paddr;
0106 };
0107 
0108 /*
0109  * STI GDP structure
0110  *
0111  * @sti_plane:          sti_plane structure
0112  * @dev:                driver device
0113  * @regs:               gdp registers
0114  * @clk_pix:            pixel clock for the current gdp
0115  * @clk_main_parent:    gdp parent clock if main path used
0116  * @clk_aux_parent:     gdp parent clock if aux path used
0117  * @vtg_field_nb:       callback for VTG FIELD (top or bottom) notification
0118  * @is_curr_top:        true if the current node processed is the top field
0119  * @node_list:          array of node list
0120  * @vtg:                registered vtg
0121  */
0122 struct sti_gdp {
0123     struct sti_plane plane;
0124     struct device *dev;
0125     void __iomem *regs;
0126     struct clk *clk_pix;
0127     struct clk *clk_main_parent;
0128     struct clk *clk_aux_parent;
0129     struct notifier_block vtg_field_nb;
0130     bool is_curr_top;
0131     struct sti_gdp_node_list node_list[GDP_NODE_NB_BANK];
0132     struct sti_vtg *vtg;
0133 };
0134 
0135 #define to_sti_gdp(x) container_of(x, struct sti_gdp, plane)
0136 
0137 static const uint32_t gdp_supported_formats[] = {
0138     DRM_FORMAT_XRGB8888,
0139     DRM_FORMAT_XBGR8888,
0140     DRM_FORMAT_ARGB8888,
0141     DRM_FORMAT_ABGR8888,
0142     DRM_FORMAT_ARGB4444,
0143     DRM_FORMAT_ARGB1555,
0144     DRM_FORMAT_RGB565,
0145     DRM_FORMAT_RGB888,
0146 };
0147 
0148 #define DBGFS_DUMP(reg) seq_printf(s, "\n  %-25s 0x%08X", #reg, \
0149                    readl(gdp->regs + reg ## _OFFSET))
0150 
0151 static void gdp_dbg_ctl(struct seq_file *s, int val)
0152 {
0153     int i;
0154 
0155     seq_puts(s, "\tColor:");
0156     for (i = 0; i < ARRAY_SIZE(gdp_format_to_str); i++) {
0157         if (gdp_format_to_str[i].format == (val & 0x1F)) {
0158             seq_puts(s, gdp_format_to_str[i].name);
0159             break;
0160         }
0161     }
0162     if (i == ARRAY_SIZE(gdp_format_to_str))
0163         seq_puts(s, "<UNKNOWN>");
0164 
0165     seq_printf(s, "\tWaitNextVsync:%d", val & WAIT_NEXT_VSYNC ? 1 : 0);
0166 }
0167 
0168 static void gdp_dbg_vpo(struct seq_file *s, int val)
0169 {
0170     seq_printf(s, "\txdo:%4d\tydo:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF);
0171 }
0172 
0173 static void gdp_dbg_vps(struct seq_file *s, int val)
0174 {
0175     seq_printf(s, "\txds:%4d\tyds:%4d", val & 0xFFFF, (val >> 16) & 0xFFFF);
0176 }
0177 
0178 static void gdp_dbg_size(struct seq_file *s, int val)
0179 {
0180     seq_printf(s, "\t%d x %d", val & 0xFFFF, (val >> 16) & 0xFFFF);
0181 }
0182 
0183 static void gdp_dbg_nvn(struct seq_file *s, struct sti_gdp *gdp, int val)
0184 {
0185     void *base = NULL;
0186     unsigned int i;
0187 
0188     for (i = 0; i < GDP_NODE_NB_BANK; i++) {
0189         if (gdp->node_list[i].top_field_paddr == val) {
0190             base = gdp->node_list[i].top_field;
0191             break;
0192         }
0193         if (gdp->node_list[i].btm_field_paddr == val) {
0194             base = gdp->node_list[i].btm_field;
0195             break;
0196         }
0197     }
0198 
0199     if (base)
0200         seq_printf(s, "\tVirt @: %p", base);
0201 }
0202 
0203 static void gdp_dbg_ppt(struct seq_file *s, int val)
0204 {
0205     if (val & GAM_GDP_PPT_IGNORE)
0206         seq_puts(s, "\tNot displayed on mixer!");
0207 }
0208 
0209 static void gdp_dbg_mst(struct seq_file *s, int val)
0210 {
0211     if (val & 1)
0212         seq_puts(s, "\tBUFFER UNDERFLOW!");
0213 }
0214 
0215 static int gdp_dbg_show(struct seq_file *s, void *data)
0216 {
0217     struct drm_info_node *node = s->private;
0218     struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data;
0219     struct drm_plane *drm_plane = &gdp->plane.drm_plane;
0220     struct drm_crtc *crtc;
0221 
0222     drm_modeset_lock(&drm_plane->mutex, NULL);
0223     crtc = drm_plane->state->crtc;
0224     drm_modeset_unlock(&drm_plane->mutex);
0225 
0226     seq_printf(s, "%s: (vaddr = 0x%p)",
0227            sti_plane_to_str(&gdp->plane), gdp->regs);
0228 
0229     DBGFS_DUMP(GAM_GDP_CTL);
0230     gdp_dbg_ctl(s, readl(gdp->regs + GAM_GDP_CTL_OFFSET));
0231     DBGFS_DUMP(GAM_GDP_AGC);
0232     DBGFS_DUMP(GAM_GDP_VPO);
0233     gdp_dbg_vpo(s, readl(gdp->regs + GAM_GDP_VPO_OFFSET));
0234     DBGFS_DUMP(GAM_GDP_VPS);
0235     gdp_dbg_vps(s, readl(gdp->regs + GAM_GDP_VPS_OFFSET));
0236     DBGFS_DUMP(GAM_GDP_PML);
0237     DBGFS_DUMP(GAM_GDP_PMP);
0238     DBGFS_DUMP(GAM_GDP_SIZE);
0239     gdp_dbg_size(s, readl(gdp->regs + GAM_GDP_SIZE_OFFSET));
0240     DBGFS_DUMP(GAM_GDP_NVN);
0241     gdp_dbg_nvn(s, gdp, readl(gdp->regs + GAM_GDP_NVN_OFFSET));
0242     DBGFS_DUMP(GAM_GDP_KEY1);
0243     DBGFS_DUMP(GAM_GDP_KEY2);
0244     DBGFS_DUMP(GAM_GDP_PPT);
0245     gdp_dbg_ppt(s, readl(gdp->regs + GAM_GDP_PPT_OFFSET));
0246     DBGFS_DUMP(GAM_GDP_CML);
0247     DBGFS_DUMP(GAM_GDP_MST);
0248     gdp_dbg_mst(s, readl(gdp->regs + GAM_GDP_MST_OFFSET));
0249 
0250     seq_puts(s, "\n\n");
0251     if (!crtc)
0252         seq_puts(s, "  Not connected to any DRM CRTC\n");
0253     else
0254         seq_printf(s, "  Connected to DRM CRTC #%d (%s)\n",
0255                crtc->base.id, sti_mixer_to_str(to_sti_mixer(crtc)));
0256 
0257     return 0;
0258 }
0259 
0260 static void gdp_node_dump_node(struct seq_file *s, struct sti_gdp_node *node)
0261 {
0262     seq_printf(s, "\t@:0x%p", node);
0263     seq_printf(s, "\n\tCTL  0x%08X", node->gam_gdp_ctl);
0264     gdp_dbg_ctl(s, node->gam_gdp_ctl);
0265     seq_printf(s, "\n\tAGC  0x%08X", node->gam_gdp_agc);
0266     seq_printf(s, "\n\tVPO  0x%08X", node->gam_gdp_vpo);
0267     gdp_dbg_vpo(s, node->gam_gdp_vpo);
0268     seq_printf(s, "\n\tVPS  0x%08X", node->gam_gdp_vps);
0269     gdp_dbg_vps(s, node->gam_gdp_vps);
0270     seq_printf(s, "\n\tPML  0x%08X", node->gam_gdp_pml);
0271     seq_printf(s, "\n\tPMP  0x%08X", node->gam_gdp_pmp);
0272     seq_printf(s, "\n\tSIZE 0x%08X", node->gam_gdp_size);
0273     gdp_dbg_size(s, node->gam_gdp_size);
0274     seq_printf(s, "\n\tNVN  0x%08X", node->gam_gdp_nvn);
0275     seq_printf(s, "\n\tKEY1 0x%08X", node->gam_gdp_key1);
0276     seq_printf(s, "\n\tKEY2 0x%08X", node->gam_gdp_key2);
0277     seq_printf(s, "\n\tPPT  0x%08X", node->gam_gdp_ppt);
0278     gdp_dbg_ppt(s, node->gam_gdp_ppt);
0279     seq_printf(s, "\n\tCML  0x%08X\n", node->gam_gdp_cml);
0280 }
0281 
0282 static int gdp_node_dbg_show(struct seq_file *s, void *arg)
0283 {
0284     struct drm_info_node *node = s->private;
0285     struct sti_gdp *gdp = (struct sti_gdp *)node->info_ent->data;
0286     unsigned int b;
0287 
0288     for (b = 0; b < GDP_NODE_NB_BANK; b++) {
0289         seq_printf(s, "\n%s[%d].top", sti_plane_to_str(&gdp->plane), b);
0290         gdp_node_dump_node(s, gdp->node_list[b].top_field);
0291         seq_printf(s, "\n%s[%d].btm", sti_plane_to_str(&gdp->plane), b);
0292         gdp_node_dump_node(s, gdp->node_list[b].btm_field);
0293     }
0294 
0295     return 0;
0296 }
0297 
0298 static struct drm_info_list gdp0_debugfs_files[] = {
0299     { "gdp0", gdp_dbg_show, 0, NULL },
0300     { "gdp0_node", gdp_node_dbg_show, 0, NULL },
0301 };
0302 
0303 static struct drm_info_list gdp1_debugfs_files[] = {
0304     { "gdp1", gdp_dbg_show, 0, NULL },
0305     { "gdp1_node", gdp_node_dbg_show, 0, NULL },
0306 };
0307 
0308 static struct drm_info_list gdp2_debugfs_files[] = {
0309     { "gdp2", gdp_dbg_show, 0, NULL },
0310     { "gdp2_node", gdp_node_dbg_show, 0, NULL },
0311 };
0312 
0313 static struct drm_info_list gdp3_debugfs_files[] = {
0314     { "gdp3", gdp_dbg_show, 0, NULL },
0315     { "gdp3_node", gdp_node_dbg_show, 0, NULL },
0316 };
0317 
0318 static int gdp_debugfs_init(struct sti_gdp *gdp, struct drm_minor *minor)
0319 {
0320     unsigned int i;
0321     struct drm_info_list *gdp_debugfs_files;
0322     int nb_files;
0323 
0324     switch (gdp->plane.desc) {
0325     case STI_GDP_0:
0326         gdp_debugfs_files = gdp0_debugfs_files;
0327         nb_files = ARRAY_SIZE(gdp0_debugfs_files);
0328         break;
0329     case STI_GDP_1:
0330         gdp_debugfs_files = gdp1_debugfs_files;
0331         nb_files = ARRAY_SIZE(gdp1_debugfs_files);
0332         break;
0333     case STI_GDP_2:
0334         gdp_debugfs_files = gdp2_debugfs_files;
0335         nb_files = ARRAY_SIZE(gdp2_debugfs_files);
0336         break;
0337     case STI_GDP_3:
0338         gdp_debugfs_files = gdp3_debugfs_files;
0339         nb_files = ARRAY_SIZE(gdp3_debugfs_files);
0340         break;
0341     default:
0342         return -EINVAL;
0343     }
0344 
0345     for (i = 0; i < nb_files; i++)
0346         gdp_debugfs_files[i].data = gdp;
0347 
0348     drm_debugfs_create_files(gdp_debugfs_files,
0349                  nb_files,
0350                  minor->debugfs_root, minor);
0351     return 0;
0352 }
0353 
0354 static int sti_gdp_fourcc2format(int fourcc)
0355 {
0356     switch (fourcc) {
0357     case DRM_FORMAT_XRGB8888:
0358         return GDP_RGB888_32;
0359     case DRM_FORMAT_XBGR8888:
0360         return GDP_XBGR8888;
0361     case DRM_FORMAT_ARGB8888:
0362         return GDP_ARGB8888;
0363     case DRM_FORMAT_ABGR8888:
0364         return GDP_ABGR8888;
0365     case DRM_FORMAT_ARGB4444:
0366         return GDP_ARGB4444;
0367     case DRM_FORMAT_ARGB1555:
0368         return GDP_ARGB1555;
0369     case DRM_FORMAT_RGB565:
0370         return GDP_RGB565;
0371     case DRM_FORMAT_RGB888:
0372         return GDP_RGB888;
0373     }
0374     return -1;
0375 }
0376 
0377 static int sti_gdp_get_alpharange(int format)
0378 {
0379     switch (format) {
0380     case GDP_ARGB8565:
0381     case GDP_ARGB8888:
0382     case GDP_ABGR8888:
0383         return GAM_GDP_ALPHARANGE_255;
0384     }
0385     return 0;
0386 }
0387 
0388 /**
0389  * sti_gdp_get_free_nodes
0390  * @gdp: gdp pointer
0391  *
0392  * Look for a GDP node list that is not currently read by the HW.
0393  *
0394  * RETURNS:
0395  * Pointer to the free GDP node list
0396  */
0397 static struct sti_gdp_node_list *sti_gdp_get_free_nodes(struct sti_gdp *gdp)
0398 {
0399     int hw_nvn;
0400     unsigned int i;
0401 
0402     hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
0403     if (!hw_nvn)
0404         goto end;
0405 
0406     for (i = 0; i < GDP_NODE_NB_BANK; i++)
0407         if ((hw_nvn != gdp->node_list[i].btm_field_paddr) &&
0408             (hw_nvn != gdp->node_list[i].top_field_paddr))
0409             return &gdp->node_list[i];
0410 
0411     /* in hazardous cases restart with the first node */
0412     DRM_ERROR("inconsistent NVN for %s: 0x%08X\n",
0413             sti_plane_to_str(&gdp->plane), hw_nvn);
0414 
0415 end:
0416     return &gdp->node_list[0];
0417 }
0418 
0419 /**
0420  * sti_gdp_get_current_nodes
0421  * @gdp: gdp pointer
0422  *
0423  * Look for GDP nodes that are currently read by the HW.
0424  *
0425  * RETURNS:
0426  * Pointer to the current GDP node list
0427  */
0428 static
0429 struct sti_gdp_node_list *sti_gdp_get_current_nodes(struct sti_gdp *gdp)
0430 {
0431     int hw_nvn;
0432     unsigned int i;
0433 
0434     hw_nvn = readl(gdp->regs + GAM_GDP_NVN_OFFSET);
0435     if (!hw_nvn)
0436         goto end;
0437 
0438     for (i = 0; i < GDP_NODE_NB_BANK; i++)
0439         if ((hw_nvn == gdp->node_list[i].btm_field_paddr) ||
0440                 (hw_nvn == gdp->node_list[i].top_field_paddr))
0441             return &gdp->node_list[i];
0442 
0443 end:
0444     DRM_DEBUG_DRIVER("Warning, NVN 0x%08X for %s does not match any node\n",
0445                 hw_nvn, sti_plane_to_str(&gdp->plane));
0446 
0447     return NULL;
0448 }
0449 
0450 /**
0451  * sti_gdp_disable
0452  * @gdp: gdp pointer
0453  *
0454  * Disable a GDP.
0455  */
0456 static void sti_gdp_disable(struct sti_gdp *gdp)
0457 {
0458     unsigned int i;
0459 
0460     DRM_DEBUG_DRIVER("%s\n", sti_plane_to_str(&gdp->plane));
0461 
0462     /* Set the nodes as 'to be ignored on mixer' */
0463     for (i = 0; i < GDP_NODE_NB_BANK; i++) {
0464         gdp->node_list[i].top_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
0465         gdp->node_list[i].btm_field->gam_gdp_ppt |= GAM_GDP_PPT_IGNORE;
0466     }
0467 
0468     if (sti_vtg_unregister_client(gdp->vtg, &gdp->vtg_field_nb))
0469         DRM_DEBUG_DRIVER("Warning: cannot unregister VTG notifier\n");
0470 
0471     if (gdp->clk_pix)
0472         clk_disable_unprepare(gdp->clk_pix);
0473 
0474     gdp->plane.status = STI_PLANE_DISABLED;
0475     gdp->vtg = NULL;
0476 }
0477 
0478 /**
0479  * sti_gdp_field_cb
0480  * @nb: notifier block
0481  * @event: event message
0482  * @data: private data
0483  *
0484  * Handle VTG top field and bottom field event.
0485  *
0486  * RETURNS:
0487  * 0 on success.
0488  */
0489 static int sti_gdp_field_cb(struct notifier_block *nb,
0490                 unsigned long event, void *data)
0491 {
0492     struct sti_gdp *gdp = container_of(nb, struct sti_gdp, vtg_field_nb);
0493 
0494     if (gdp->plane.status == STI_PLANE_FLUSHING) {
0495         /* disable need to be synchronize on vsync event */
0496         DRM_DEBUG_DRIVER("Vsync event received => disable %s\n",
0497                  sti_plane_to_str(&gdp->plane));
0498 
0499         sti_gdp_disable(gdp);
0500     }
0501 
0502     switch (event) {
0503     case VTG_TOP_FIELD_EVENT:
0504         gdp->is_curr_top = true;
0505         break;
0506     case VTG_BOTTOM_FIELD_EVENT:
0507         gdp->is_curr_top = false;
0508         break;
0509     default:
0510         DRM_ERROR("unsupported event: %lu\n", event);
0511         break;
0512     }
0513 
0514     return 0;
0515 }
0516 
0517 static void sti_gdp_init(struct sti_gdp *gdp)
0518 {
0519     struct device_node *np = gdp->dev->of_node;
0520     dma_addr_t dma_addr;
0521     void *base;
0522     unsigned int i, size;
0523 
0524     /* Allocate all the nodes within a single memory page */
0525     size = sizeof(struct sti_gdp_node) *
0526         GDP_NODE_PER_FIELD * GDP_NODE_NB_BANK;
0527     base = dma_alloc_wc(gdp->dev, size, &dma_addr, GFP_KERNEL);
0528 
0529     if (!base) {
0530         DRM_ERROR("Failed to allocate memory for GDP node\n");
0531         return;
0532     }
0533     memset(base, 0, size);
0534 
0535     for (i = 0; i < GDP_NODE_NB_BANK; i++) {
0536         if (dma_addr & 0xF) {
0537             DRM_ERROR("Mem alignment failed\n");
0538             return;
0539         }
0540         gdp->node_list[i].top_field = base;
0541         gdp->node_list[i].top_field_paddr = dma_addr;
0542 
0543         DRM_DEBUG_DRIVER("node[%d].top_field=%p\n", i, base);
0544         base += sizeof(struct sti_gdp_node);
0545         dma_addr += sizeof(struct sti_gdp_node);
0546 
0547         if (dma_addr & 0xF) {
0548             DRM_ERROR("Mem alignment failed\n");
0549             return;
0550         }
0551         gdp->node_list[i].btm_field = base;
0552         gdp->node_list[i].btm_field_paddr = dma_addr;
0553         DRM_DEBUG_DRIVER("node[%d].btm_field=%p\n", i, base);
0554         base += sizeof(struct sti_gdp_node);
0555         dma_addr += sizeof(struct sti_gdp_node);
0556     }
0557 
0558     if (of_device_is_compatible(np, "st,stih407-compositor")) {
0559         /* GDP of STiH407 chip have its own pixel clock */
0560         char *clk_name;
0561 
0562         switch (gdp->plane.desc) {
0563         case STI_GDP_0:
0564             clk_name = "pix_gdp1";
0565             break;
0566         case STI_GDP_1:
0567             clk_name = "pix_gdp2";
0568             break;
0569         case STI_GDP_2:
0570             clk_name = "pix_gdp3";
0571             break;
0572         case STI_GDP_3:
0573             clk_name = "pix_gdp4";
0574             break;
0575         default:
0576             DRM_ERROR("GDP id not recognized\n");
0577             return;
0578         }
0579 
0580         gdp->clk_pix = devm_clk_get(gdp->dev, clk_name);
0581         if (IS_ERR(gdp->clk_pix))
0582             DRM_ERROR("Cannot get %s clock\n", clk_name);
0583 
0584         gdp->clk_main_parent = devm_clk_get(gdp->dev, "main_parent");
0585         if (IS_ERR(gdp->clk_main_parent))
0586             DRM_ERROR("Cannot get main_parent clock\n");
0587 
0588         gdp->clk_aux_parent = devm_clk_get(gdp->dev, "aux_parent");
0589         if (IS_ERR(gdp->clk_aux_parent))
0590             DRM_ERROR("Cannot get aux_parent clock\n");
0591     }
0592 }
0593 
0594 /**
0595  * sti_gdp_get_dst
0596  * @dev: device
0597  * @dst: requested destination size
0598  * @src: source size
0599  *
0600  * Return the cropped / clamped destination size
0601  *
0602  * RETURNS:
0603  * cropped / clamped destination size
0604  */
0605 static int sti_gdp_get_dst(struct device *dev, int dst, int src)
0606 {
0607     if (dst == src)
0608         return dst;
0609 
0610     if (dst < src) {
0611         dev_dbg(dev, "WARNING: GDP scale not supported, will crop\n");
0612         return dst;
0613     }
0614 
0615     dev_dbg(dev, "WARNING: GDP scale not supported, will clamp\n");
0616     return src;
0617 }
0618 
0619 static int sti_gdp_atomic_check(struct drm_plane *drm_plane,
0620                 struct drm_atomic_state *state)
0621 {
0622     struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
0623                                          drm_plane);
0624     struct sti_plane *plane = to_sti_plane(drm_plane);
0625     struct sti_gdp *gdp = to_sti_gdp(plane);
0626     struct drm_crtc *crtc = new_plane_state->crtc;
0627     struct drm_framebuffer *fb =  new_plane_state->fb;
0628     struct drm_crtc_state *crtc_state;
0629     struct sti_mixer *mixer;
0630     struct drm_display_mode *mode;
0631     int dst_x, dst_y, dst_w, dst_h;
0632     int src_x, src_y, src_w, src_h;
0633     int format;
0634 
0635     /* no need for further checks if the plane is being disabled */
0636     if (!crtc || !fb)
0637         return 0;
0638 
0639     mixer = to_sti_mixer(crtc);
0640     crtc_state = drm_atomic_get_crtc_state(state, crtc);
0641     mode = &crtc_state->mode;
0642     dst_x = new_plane_state->crtc_x;
0643     dst_y = new_plane_state->crtc_y;
0644     dst_w = clamp_val(new_plane_state->crtc_w, 0, mode->hdisplay - dst_x);
0645     dst_h = clamp_val(new_plane_state->crtc_h, 0, mode->vdisplay - dst_y);
0646     /* src_x are in 16.16 format */
0647     src_x = new_plane_state->src_x >> 16;
0648     src_y = new_plane_state->src_y >> 16;
0649     src_w = clamp_val(new_plane_state->src_w >> 16, 0,
0650               GAM_GDP_SIZE_MAX_WIDTH);
0651     src_h = clamp_val(new_plane_state->src_h >> 16, 0,
0652               GAM_GDP_SIZE_MAX_HEIGHT);
0653 
0654     format = sti_gdp_fourcc2format(fb->format->format);
0655     if (format == -1) {
0656         DRM_ERROR("Format not supported by GDP %.4s\n",
0657               (char *)&fb->format->format);
0658         return -EINVAL;
0659     }
0660 
0661     if (!drm_fb_cma_get_gem_obj(fb, 0)) {
0662         DRM_ERROR("Can't get CMA GEM object for fb\n");
0663         return -EINVAL;
0664     }
0665 
0666     /* Set gdp clock */
0667     if (mode->clock && gdp->clk_pix) {
0668         struct clk *clkp;
0669         int rate = mode->clock * 1000;
0670         int res;
0671 
0672         /*
0673          * According to the mixer used, the gdp pixel clock
0674          * should have a different parent clock.
0675          */
0676         if (mixer->id == STI_MIXER_MAIN)
0677             clkp = gdp->clk_main_parent;
0678         else
0679             clkp = gdp->clk_aux_parent;
0680 
0681         if (clkp)
0682             clk_set_parent(gdp->clk_pix, clkp);
0683 
0684         res = clk_set_rate(gdp->clk_pix, rate);
0685         if (res < 0) {
0686             DRM_ERROR("Cannot set rate (%dHz) for gdp\n",
0687                   rate);
0688             return -EINVAL;
0689         }
0690     }
0691 
0692     DRM_DEBUG_KMS("CRTC:%d (%s) drm plane:%d (%s)\n",
0693               crtc->base.id, sti_mixer_to_str(mixer),
0694               drm_plane->base.id, sti_plane_to_str(plane));
0695     DRM_DEBUG_KMS("%s dst=(%dx%d)@(%d,%d) - src=(%dx%d)@(%d,%d)\n",
0696               sti_plane_to_str(plane),
0697               dst_w, dst_h, dst_x, dst_y,
0698               src_w, src_h, src_x, src_y);
0699 
0700     return 0;
0701 }
0702 
0703 static void sti_gdp_atomic_update(struct drm_plane *drm_plane,
0704                   struct drm_atomic_state *state)
0705 {
0706     struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state,
0707                                       drm_plane);
0708     struct drm_plane_state *newstate = drm_atomic_get_new_plane_state(state,
0709                                       drm_plane);
0710     struct sti_plane *plane = to_sti_plane(drm_plane);
0711     struct sti_gdp *gdp = to_sti_gdp(plane);
0712     struct drm_crtc *crtc = newstate->crtc;
0713     struct drm_framebuffer *fb =  newstate->fb;
0714     struct drm_display_mode *mode;
0715     int dst_x, dst_y, dst_w, dst_h;
0716     int src_x, src_y, src_w, src_h;
0717     struct drm_gem_cma_object *cma_obj;
0718     struct sti_gdp_node_list *list;
0719     struct sti_gdp_node_list *curr_list;
0720     struct sti_gdp_node *top_field, *btm_field;
0721     u32 dma_updated_top;
0722     u32 dma_updated_btm;
0723     int format;
0724     unsigned int bpp;
0725     u32 ydo, xdo, yds, xds;
0726 
0727     if (!crtc || !fb)
0728         return;
0729 
0730     if ((oldstate->fb == newstate->fb) &&
0731         (oldstate->crtc_x == newstate->crtc_x) &&
0732         (oldstate->crtc_y == newstate->crtc_y) &&
0733         (oldstate->crtc_w == newstate->crtc_w) &&
0734         (oldstate->crtc_h == newstate->crtc_h) &&
0735         (oldstate->src_x == newstate->src_x) &&
0736         (oldstate->src_y == newstate->src_y) &&
0737         (oldstate->src_w == newstate->src_w) &&
0738         (oldstate->src_h == newstate->src_h)) {
0739         /* No change since last update, do not post cmd */
0740         DRM_DEBUG_DRIVER("No change, not posting cmd\n");
0741         plane->status = STI_PLANE_UPDATED;
0742         return;
0743     }
0744 
0745     if (!gdp->vtg) {
0746         struct sti_compositor *compo = dev_get_drvdata(gdp->dev);
0747         struct sti_mixer *mixer = to_sti_mixer(crtc);
0748 
0749         /* Register gdp callback */
0750         gdp->vtg = compo->vtg[mixer->id];
0751         sti_vtg_register_client(gdp->vtg, &gdp->vtg_field_nb, crtc);
0752         clk_prepare_enable(gdp->clk_pix);
0753     }
0754 
0755     mode = &crtc->mode;
0756     dst_x = newstate->crtc_x;
0757     dst_y = newstate->crtc_y;
0758     dst_w = clamp_val(newstate->crtc_w, 0, mode->hdisplay - dst_x);
0759     dst_h = clamp_val(newstate->crtc_h, 0, mode->vdisplay - dst_y);
0760     /* src_x are in 16.16 format */
0761     src_x = newstate->src_x >> 16;
0762     src_y = newstate->src_y >> 16;
0763     src_w = clamp_val(newstate->src_w >> 16, 0, GAM_GDP_SIZE_MAX_WIDTH);
0764     src_h = clamp_val(newstate->src_h >> 16, 0, GAM_GDP_SIZE_MAX_HEIGHT);
0765 
0766     list = sti_gdp_get_free_nodes(gdp);
0767     top_field = list->top_field;
0768     btm_field = list->btm_field;
0769 
0770     dev_dbg(gdp->dev, "%s %s top_node:0x%p btm_node:0x%p\n", __func__,
0771         sti_plane_to_str(plane), top_field, btm_field);
0772 
0773     /* build the top field */
0774     top_field->gam_gdp_agc = GAM_GDP_AGC_FULL_RANGE;
0775     top_field->gam_gdp_ctl = WAIT_NEXT_VSYNC;
0776     format = sti_gdp_fourcc2format(fb->format->format);
0777     top_field->gam_gdp_ctl |= format;
0778     top_field->gam_gdp_ctl |= sti_gdp_get_alpharange(format);
0779     top_field->gam_gdp_ppt &= ~GAM_GDP_PPT_IGNORE;
0780 
0781     cma_obj = drm_fb_cma_get_gem_obj(fb, 0);
0782 
0783     DRM_DEBUG_DRIVER("drm FB:%d format:%.4s phys@:0x%lx\n", fb->base.id,
0784              (char *)&fb->format->format,
0785              (unsigned long)cma_obj->paddr);
0786 
0787     /* pixel memory location */
0788     bpp = fb->format->cpp[0];
0789     top_field->gam_gdp_pml = (u32)cma_obj->paddr + fb->offsets[0];
0790     top_field->gam_gdp_pml += src_x * bpp;
0791     top_field->gam_gdp_pml += src_y * fb->pitches[0];
0792 
0793     /* output parameters (clamped / cropped) */
0794     dst_w = sti_gdp_get_dst(gdp->dev, dst_w, src_w);
0795     dst_h = sti_gdp_get_dst(gdp->dev, dst_h, src_h);
0796     ydo = sti_vtg_get_line_number(*mode, dst_y);
0797     yds = sti_vtg_get_line_number(*mode, dst_y + dst_h - 1);
0798     xdo = sti_vtg_get_pixel_number(*mode, dst_x);
0799     xds = sti_vtg_get_pixel_number(*mode, dst_x + dst_w - 1);
0800     top_field->gam_gdp_vpo = (ydo << 16) | xdo;
0801     top_field->gam_gdp_vps = (yds << 16) | xds;
0802 
0803     /* input parameters */
0804     src_w = dst_w;
0805     top_field->gam_gdp_pmp = fb->pitches[0];
0806     top_field->gam_gdp_size = src_h << 16 | src_w;
0807 
0808     /* Same content and chained together */
0809     memcpy(btm_field, top_field, sizeof(*btm_field));
0810     top_field->gam_gdp_nvn = list->btm_field_paddr;
0811     btm_field->gam_gdp_nvn = list->top_field_paddr;
0812 
0813     /* Interlaced mode */
0814     if (mode->flags & DRM_MODE_FLAG_INTERLACE)
0815         btm_field->gam_gdp_pml = top_field->gam_gdp_pml +
0816                      fb->pitches[0];
0817 
0818     /* Update the NVN field of the 'right' field of the current GDP node
0819      * (being used by the HW) with the address of the updated ('free') top
0820      * field GDP node.
0821      * - In interlaced mode the 'right' field is the bottom field as we
0822      *   update frames starting from their top field
0823      * - In progressive mode, we update both bottom and top fields which
0824      *   are equal nodes.
0825      * At the next VSYNC, the updated node list will be used by the HW.
0826      */
0827     curr_list = sti_gdp_get_current_nodes(gdp);
0828     dma_updated_top = list->top_field_paddr;
0829     dma_updated_btm = list->btm_field_paddr;
0830 
0831     dev_dbg(gdp->dev, "Current NVN:0x%X\n",
0832         readl(gdp->regs + GAM_GDP_NVN_OFFSET));
0833     dev_dbg(gdp->dev, "Posted buff: %lx current buff: %x\n",
0834         (unsigned long)cma_obj->paddr,
0835         readl(gdp->regs + GAM_GDP_PML_OFFSET));
0836 
0837     if (!curr_list) {
0838         /* First update or invalid node should directly write in the
0839          * hw register */
0840         DRM_DEBUG_DRIVER("%s first update (or invalid node)\n",
0841                  sti_plane_to_str(plane));
0842 
0843         writel(gdp->is_curr_top ?
0844                 dma_updated_btm : dma_updated_top,
0845                 gdp->regs + GAM_GDP_NVN_OFFSET);
0846         goto end;
0847     }
0848 
0849     if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
0850         if (gdp->is_curr_top) {
0851             /* Do not update in the middle of the frame, but
0852              * postpone the update after the bottom field has
0853              * been displayed */
0854             curr_list->btm_field->gam_gdp_nvn = dma_updated_top;
0855         } else {
0856             /* Direct update to avoid one frame delay */
0857             writel(dma_updated_top,
0858                    gdp->regs + GAM_GDP_NVN_OFFSET);
0859         }
0860     } else {
0861         /* Direct update for progressive to avoid one frame delay */
0862         writel(dma_updated_top, gdp->regs + GAM_GDP_NVN_OFFSET);
0863     }
0864 
0865 end:
0866     sti_plane_update_fps(plane, true, false);
0867 
0868     plane->status = STI_PLANE_UPDATED;
0869 }
0870 
0871 static void sti_gdp_atomic_disable(struct drm_plane *drm_plane,
0872                    struct drm_atomic_state *state)
0873 {
0874     struct drm_plane_state *oldstate = drm_atomic_get_old_plane_state(state,
0875                                       drm_plane);
0876     struct sti_plane *plane = to_sti_plane(drm_plane);
0877 
0878     if (!oldstate->crtc) {
0879         DRM_DEBUG_DRIVER("drm plane:%d not enabled\n",
0880                  drm_plane->base.id);
0881         return;
0882     }
0883 
0884     DRM_DEBUG_DRIVER("CRTC:%d (%s) drm plane:%d (%s)\n",
0885              oldstate->crtc->base.id,
0886              sti_mixer_to_str(to_sti_mixer(oldstate->crtc)),
0887              drm_plane->base.id, sti_plane_to_str(plane));
0888 
0889     plane->status = STI_PLANE_DISABLING;
0890 }
0891 
0892 static const struct drm_plane_helper_funcs sti_gdp_helpers_funcs = {
0893     .atomic_check = sti_gdp_atomic_check,
0894     .atomic_update = sti_gdp_atomic_update,
0895     .atomic_disable = sti_gdp_atomic_disable,
0896 };
0897 
0898 static int sti_gdp_late_register(struct drm_plane *drm_plane)
0899 {
0900     struct sti_plane *plane = to_sti_plane(drm_plane);
0901     struct sti_gdp *gdp = to_sti_gdp(plane);
0902 
0903     return gdp_debugfs_init(gdp, drm_plane->dev->primary);
0904 }
0905 
0906 static const struct drm_plane_funcs sti_gdp_plane_helpers_funcs = {
0907     .update_plane = drm_atomic_helper_update_plane,
0908     .disable_plane = drm_atomic_helper_disable_plane,
0909     .destroy = drm_plane_cleanup,
0910     .reset = drm_atomic_helper_plane_reset,
0911     .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
0912     .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
0913     .late_register = sti_gdp_late_register,
0914 };
0915 
0916 struct drm_plane *sti_gdp_create(struct drm_device *drm_dev,
0917                  struct device *dev, int desc,
0918                  void __iomem *baseaddr,
0919                  unsigned int possible_crtcs,
0920                  enum drm_plane_type type)
0921 {
0922     struct sti_gdp *gdp;
0923     int res;
0924 
0925     gdp = devm_kzalloc(dev, sizeof(*gdp), GFP_KERNEL);
0926     if (!gdp) {
0927         DRM_ERROR("Failed to allocate memory for GDP\n");
0928         return NULL;
0929     }
0930 
0931     gdp->dev = dev;
0932     gdp->regs = baseaddr;
0933     gdp->plane.desc = desc;
0934     gdp->plane.status = STI_PLANE_DISABLED;
0935 
0936     gdp->vtg_field_nb.notifier_call = sti_gdp_field_cb;
0937 
0938     sti_gdp_init(gdp);
0939 
0940     res = drm_universal_plane_init(drm_dev, &gdp->plane.drm_plane,
0941                        possible_crtcs,
0942                        &sti_gdp_plane_helpers_funcs,
0943                        gdp_supported_formats,
0944                        ARRAY_SIZE(gdp_supported_formats),
0945                        NULL, type, NULL);
0946     if (res) {
0947         DRM_ERROR("Failed to initialize universal plane\n");
0948         goto err;
0949     }
0950 
0951     drm_plane_helper_add(&gdp->plane.drm_plane, &sti_gdp_helpers_funcs);
0952 
0953     sti_plane_init_property(&gdp->plane, type);
0954 
0955     return &gdp->plane.drm_plane;
0956 
0957 err:
0958     devm_kfree(dev, gdp);
0959     return NULL;
0960 }
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