0001 1. stiH display hardware IP
0002 ---------------------------
0003 The STMicroelectronics stiH SoCs use a common chain of HW display IP blocks:
0004 - The High Quality Video Display Processor (HQVDP) gets video frames from a
0005 video decoder and does high quality video processing, including scaling.
0006
0007 - The Compositor is a multiplane, dual-mixer (Main & Aux) digital processor. It
0008 has several inputs:
0009 - The graphics planes are internally processed by the Generic Display
0010 Pipeline (GDP).
0011 - The video plug (VID) connects to the HQVDP output.
0012 - The cursor handles ... a cursor.
0013 - The TV OUT pre-formats (convert, clip, round) the compositor output data
0014 - The HDMI / DVO / HD Analog / SD analog IP builds the video signals
0015 - DVO (Digital Video Output) handles a 24bits parallel signal
0016 - The HD analog signal is typically driven by a YCbCr cable, supporting up to
0017 1080i mode.
0018 - The SD analog signal is typically used for legacy TV
0019 - The VTG (Video Timing Generators) build Vsync signals used by the other HW IP
0020 Note that some stiH drivers support only a subset of thee HW IP.
0021
0022 .-------------. .-----------. .-----------.
0023 GPU >-------------+GDP Main | | +---+ HDMI +--> HDMI
0024 GPU >-------------+GDP mixer+---+ | :===========:
0025 GPU >-------------+Cursor | | +---+ DVO +--> 24b//
0026 ------- | COMPOSITOR | | TV OUT | :===========:
0027 | | | | | +---+ HD analog +--> YCbCr
0028 Vid >--+ HQVDP +--+VID Aux +---+ | :===========:
0029 dec | | | mixer| | +---+ SD analog +--> CVBS
0030 '-------' '-------------' '-----------' '-----------'
0031 .-----------.
0032 | main+--> Vsync
0033 | VTG |
0034 | aux+--> Vsync
0035 '-----------'
0036
0037 2. DRM / HW mapping
0038 -------------------
0039 These IP are mapped to the DRM objects as following:
0040 - The CRTCs are mapped to the Compositor Main and Aux Mixers
0041 - The Framebuffers and planes are mapped to the Compositor GDP (non video
0042 buffers) and to HQVDP+VID (video buffers)
0043 - The Cursor is mapped to the Compositor Cursor
0044 - The Encoders are mapped to the TVOut
0045 - The Bridges/Connectors are mapped to the HDMI / DVO / HD Analog / SD analog
0046
0047 FB & planes Cursor CRTC Encoders Bridges/Connectors
0048 | | | | |
0049 | | | | |
0050 | .-------------. | .-----------. .-----------. |
0051 +------------> |GDP | Main | | | +-> | | HDMI | <-+
0052 +------------> |GDP v mixer|<+ | | | :===========: |
0053 | |Cursor | | | +-> | | DVO | <-+
0054 | ------- | COMPOSITOR | | |TV OUT | | :===========: |
0055 | | | | | | | +-> | | HD analog | <-+
0056 +-> | HQVDP | |VID Aux |<+ | | | :===========: |
0057 | | | mixer| | +-> | | SD analog | <-+
0058 '-------' '-------------' '-----------' '-----------'
