drm/sprd/sprd_dsi.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2020 Unisoc Inc.
0004  */
0005
0006 #ifndef __SPRD_DSI_H__
0007 #define __SPRD_DSI_H__
0008
0009 #include <linux/of.h>
0010 #include <linux/device.h>
0011 #include <linux/regmap.h>
0012 #include <video/videomode.h>
0013
0014 #include <drm/drm_bridge.h>
0015 #include <drm/drm_connector.h>
0016 #include <drm/drm_encoder.h>
0017 #include <drm/drm_mipi_dsi.h>
0018 #include <drm/drm_print.h>
0019 #include <drm/drm_panel.h>
0020
0021 #define encoder_to_dsi(encoder) \
0022     container_of(encoder, struct sprd_dsi, encoder)
0023
0024 enum dsi_work_mode {
0025     DSI_MODE_CMD = 0,
0026     DSI_MODE_VIDEO
0027 };
0028
0029 enum video_burst_mode {
0030     VIDEO_NON_BURST_WITH_SYNC_PULSES = 0,
0031     VIDEO_NON_BURST_WITH_SYNC_EVENTS,
0032     VIDEO_BURST_WITH_SYNC_PULSES
0033 };
0034
0035 enum dsi_color_coding {
0036     COLOR_CODE_16BIT_CONFIG1 = 0,
0037     COLOR_CODE_16BIT_CONFIG2,
0038     COLOR_CODE_16BIT_CONFIG3,
0039     COLOR_CODE_18BIT_CONFIG1,
0040     COLOR_CODE_18BIT_CONFIG2,
0041     COLOR_CODE_24BIT,
0042     COLOR_CODE_20BIT_YCC422_LOOSELY,
0043     COLOR_CODE_24BIT_YCC422,
0044     COLOR_CODE_16BIT_YCC422,
0045     COLOR_CODE_30BIT,
0046     COLOR_CODE_36BIT,
0047     COLOR_CODE_12BIT_YCC420,
0048     COLOR_CODE_COMPRESSTION,
0049     COLOR_CODE_MAX
0050 };
0051
0052 enum pll_timing {
0053     NONE,
0054     REQUEST_TIME,
0055     PREPARE_TIME,
0056     SETTLE_TIME,
0057     ZERO_TIME,
0058     TRAIL_TIME,
0059     EXIT_TIME,
0060     CLKPOST_TIME,
0061     TA_GET,
0062     TA_GO,
0063     TA_SURE,
0064     TA_WAIT,
0065 };
0066
0067 struct dphy_pll {
0068     u8 refin; /* Pre-divider control signal */
0069     u8 cp_s; /* 00: SDM_EN=1, 10: SDM_EN=0 */
0070     u8 fdk_s; /* PLL mode control: integer or fraction */
0071     u8 sdm_en;
0072     u8 div;
0073     u8 int_n; /* integer N PLL */
0074     u32 ref_clk; /* dphy reference clock, unit: MHz */
0075     u32 freq; /* panel config, unit: KHz */
0076     u32 fvco;
0077     u32 potential_fvco;
0078     u32 nint; /* sigma delta modulator NINT control */
0079     u32 kint; /* sigma delta modulator KINT control */
0080     u8 lpf_sel; /* low pass filter control */
0081     u8 out_sel; /* post divider control */
0082     u8 vco_band; /* vco range */
0083     u8 det_delay;
0084 };
0085
0086 struct dsi_context {
0087     void __iomem *base;
0088     struct regmap *regmap;
0089     struct dphy_pll pll;
0090     struct videomode vm;
0091     bool enabled;
0092
0093     u8 work_mode;
0094     u8 burst_mode;
0095     u32 int0_mask;
0096     u32 int1_mask;
0097
0098     /* maximum time (ns) for data lanes from HS to LP */
0099     u16 data_hs2lp;
0100     /* maximum time (ns) for data lanes from LP to HS */
0101     u16 data_lp2hs;
0102     /* maximum time (ns) for clk lanes from HS to LP */
0103     u16 clk_hs2lp;
0104     /* maximum time (ns) for clk lanes from LP to HS */
0105     u16 clk_lp2hs;
0106     /* maximum time (ns) for BTA operation - REQUIRED */
0107     u16 max_rd_time;
0108     /* enable receiving frame ack packets - for video mode */
0109     bool frame_ack_en;
0110     /* enable receiving tear effect ack packets - for cmd mode */
0111     bool te_ack_en;
0112 };
0113
0114 struct sprd_dsi {
0115     struct drm_device *drm;
0116     struct mipi_dsi_host host;
0117     struct mipi_dsi_device *slave;
0118     struct drm_encoder encoder;
0119     struct drm_bridge *panel_bridge;
0120     struct dsi_context ctx;
0121 };
0122
0123 int dphy_pll_config(struct dsi_context *ctx);
0124 void dphy_timing_config(struct dsi_context *ctx);
0125
0126 #endif /* __SPRD_DSI_H__ */